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GET /api/patches/79664/?format=api
{ "id": 79664, "url": "http://patches.dpdk.org/api/patches/79664/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-47-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005120910.189343-47-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-47-jiawenwu@trustnetic.com", "date": "2020-10-05T12:09:00", "name": "[v2,46/56] net/txgbe: add priority flow control support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "12f8cf39d148d70c8145fa4cd0cec35e0572719c", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-47-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12690, "url": "http://patches.dpdk.org/api/series/12690/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12690", "date": "2020-10-05T12:08:14", "name": "net: txgbe PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/12690/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/79664/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/79664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 33508A04B1;\n\tMon, 5 Oct 2020 14:28:13 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 330BE1C131;\n\tMon, 5 Oct 2020 14:10:05 +0200 (CEST)", "from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142])\n by dpdk.org (Postfix) with ESMTP id 7C9171BEDD\n for <dev@dpdk.org>; Mon, 5 Oct 2020 14:09:39 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 05 Oct 2020 20:09:34 +0800 (CST)" ], "X-QQ-mid": "bizesmtp9t1601899775tklvlrgek", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "OthLD3hRvFEhRijeaXlEWNmU9a/SVUUVs4OOJncsSnO0rZZ3W6Gs+Um6emO6R\n B0EhwR8QMfcCIoxzP7pBxN2uMGxvfXQ676Lwu53qbxtUyfUVTFMODqe4ZGUh2Bf6AXeNnNn\n N4795gvrLU2Zcx/aXImQo9Gp0goM/fL9nrj7fOz6orL+6xlpoT2CD26/t9DZltAyF6Tz7nc\n 7qYvA2k2EpR83LGW2Li13xXPazGkY6M4SPHTyXoAHGwL7OYuIaSdVGnVTV2mpP9B8x6bOnR\n /1cdGG/eWp02V/yLeQMJPufixs0U/N4sLL/L3v75X4jOcJP8dt32x2bNEItYmwrNJhWeBDY\n gysFK7wvEtJKW+PWiQ=", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "jiawenwu <jiawenwu@trustnetic.com>", "Date": "Mon, 5 Oct 2020 20:09:00 +0800", "Message-Id": "<20201005120910.189343-47-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign6", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 46/56] net/txgbe: add priority flow control\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd priority flow control support.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_dcb.c | 148 ++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_dcb.h | 2 +\n drivers/net/txgbe/base/txgbe_dcb_hw.c | 73 +++++++++++++\n drivers/net/txgbe/txgbe_ethdev.c | 53 +++++++++\n drivers/net/txgbe/txgbe_rxtx.c | 22 +++-\n 5 files changed, 297 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/txgbe/base/txgbe_dcb.c b/drivers/net/txgbe/base/txgbe_dcb.c\nindex da6a3a7c8..7e9a16cfe 100644\n--- a/drivers/net/txgbe/base/txgbe_dcb.c\n+++ b/drivers/net/txgbe/base/txgbe_dcb.c\n@@ -7,6 +7,146 @@\n #include \"txgbe_dcb.h\"\n #include \"txgbe_dcb_hw.h\"\n \n+/**\n+ * txgbe_pfc_enable - Enable flow control\n+ * @hw: pointer to hardware structure\n+ * @tc_num: traffic class number\n+ * Enable flow control according to the current settings.\n+ */\n+int\n+txgbe_dcb_pfc_enable(struct txgbe_hw *hw, uint8_t tc_num)\n+{\n+\tint ret_val = 0;\n+\tuint32_t mflcn_reg, fccfg_reg;\n+\tuint32_t pause_time;\n+\tuint32_t fcrtl, fcrth;\n+\tuint8_t i;\n+\tuint8_t nb_rx_en;\n+\n+\t/* Validate the water mark configuration */\n+\tif (!hw->fc.pause_time) {\n+\t\tret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Low water mark of zero causes XOFF floods */\n+\tif (hw->fc.current_mode & txgbe_fc_tx_pause) {\n+\t\t /* High/Low water can not be 0 */\n+\t\tif (!hw->fc.high_water[tc_num] ||\n+\t\t !hw->fc.low_water[tc_num]) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Invalid water mark configuration\");\n+\t\t\tret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Invalid water mark configuration\");\n+\t\t\tret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+\t/* Negotiate the fc mode to use */\n+\ttxgbe_fc_autoneg(hw);\n+\n+\t/* Disable any previous flow control settings */\n+\tmflcn_reg = rd32(hw, TXGBE_RXFCCFG);\n+\tmflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);\n+\n+\tfccfg_reg = rd32(hw, TXGBE_TXFCCFG);\n+\tfccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);\n+\n+\tswitch (hw->fc.current_mode) {\n+\tcase txgbe_fc_none:\n+\t\t/*\n+\t\t * If the count of enabled RX Priority Flow control > 1,\n+\t\t * and the TX pause can not be disabled\n+\t\t */\n+\t\tnb_rx_en = 0;\n+\t\tfor (i = 0; i < TXGBE_DCB_TC_MAX; i++) {\n+\t\t\tuint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));\n+\t\t\tif (reg & TXGBE_FCWTRHI_XOFF)\n+\t\t\t\tnb_rx_en++;\n+\t\t}\n+\t\tif (nb_rx_en > 1)\n+\t\t\tfccfg_reg |= TXGBE_TXFCCFG_PFC;\n+\t\tbreak;\n+\tcase txgbe_fc_rx_pause:\n+\t\t/*\n+\t\t * Rx Flow control is enabled and Tx Flow control is\n+\t\t * disabled by software override. Since there really\n+\t\t * isn't a way to advertise that we are capable of RX\n+\t\t * Pause ONLY, we will advertise that we support both\n+\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n+\t\t * disable the adapter's ability to send PAUSE frames.\n+\t\t */\n+\t\tmflcn_reg |= TXGBE_RXFCCFG_PFC;\n+\t\t/*\n+\t\t * If the count of enabled RX Priority Flow control > 1,\n+\t\t * and the TX pause can not be disabled\n+\t\t */\n+\t\tnb_rx_en = 0;\n+\t\tfor (i = 0; i < TXGBE_DCB_TC_MAX; i++) {\n+\t\t\tuint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));\n+\t\t\tif (reg & TXGBE_FCWTRHI_XOFF)\n+\t\t\t\tnb_rx_en++;\n+\t\t}\n+\t\tif (nb_rx_en > 1)\n+\t\t\tfccfg_reg |= TXGBE_TXFCCFG_PFC;\n+\t\tbreak;\n+\tcase txgbe_fc_tx_pause:\n+\t\t/*\n+\t\t * Tx Flow control is enabled, and Rx Flow control is\n+\t\t * disabled by software override.\n+\t\t */\n+\t\tfccfg_reg |= TXGBE_TXFCCFG_PFC;\n+\t\tbreak;\n+\tcase txgbe_fc_full:\n+\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n+\t\tmflcn_reg |= TXGBE_RXFCCFG_PFC;\n+\t\tfccfg_reg |= TXGBE_TXFCCFG_PFC;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(DEBUG, \"Flow control param set incorrectly\");\n+\t\tret_val = TXGBE_ERR_CONFIG;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Set 802.3x based flow control settings. */\n+\twr32(hw, TXGBE_RXFCCFG, mflcn_reg);\n+\twr32(hw, TXGBE_TXFCCFG, fccfg_reg);\n+\n+\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n+\tif ((hw->fc.current_mode & txgbe_fc_tx_pause) &&\n+\t\thw->fc.high_water[tc_num]) {\n+\t\tfcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[tc_num]) |\n+\t\t\tTXGBE_FCWTRLO_XON;\n+\t\tfcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[tc_num]) |\n+\t\t\tTXGBE_FCWTRHI_XOFF;\n+\t} else {\n+\t\t/*\n+\t\t * In order to prevent Tx hangs when the internal Tx\n+\t\t * switch is enabled we must set the high water mark\n+\t\t * to the maximum FCRTH value. This allows the Tx\n+\t\t * switch to function even under heavy Rx workloads.\n+\t\t */\n+\t\tfcrtl = 0;\n+\t\tfcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32;\n+\t}\n+\twr32(hw, TXGBE_FCWTRLO(tc_num), fcrtl);\n+\twr32(hw, TXGBE_FCWTRHI(tc_num), fcrth);\n+\n+\t/* Configure pause time (2 TCs per register) */\n+\tpause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);\n+\tfor (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)\n+\t\twr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);\n+\n+\t/* Configure flow control refresh threshold value */\n+\twr32(hw, TXGBE_RXFCRFSH, pause_time / 2);\n+\n+out:\n+\treturn ret_val;\n+}\n+\n /**\n * txgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits\n * @hw: pointer to hardware structure\n@@ -210,3 +350,11 @@ void txgbe_dcb_unpack_map_cee(struct txgbe_dcb_config *cfg, int direction,\n \t\tmap[up] = txgbe_dcb_get_tc_from_up(cfg, direction, up);\n }\n \n+/* Helper routines to abstract HW specifics from DCB netlink ops */\n+s32 txgbe_dcb_config_pfc(struct txgbe_hw *hw, u8 pfc_en, u8 *map)\n+{\n+\tint ret = TXGBE_ERR_PARAM;\n+\tret = txgbe_dcb_config_pfc_raptor(hw, pfc_en, map);\n+\treturn ret;\n+}\n+\ndiff --git a/drivers/net/txgbe/base/txgbe_dcb.h b/drivers/net/txgbe/base/txgbe_dcb.h\nindex 4370a627d..c679f1d75 100644\n--- a/drivers/net/txgbe/base/txgbe_dcb.h\n+++ b/drivers/net/txgbe/base/txgbe_dcb.h\n@@ -90,6 +90,8 @@ struct txgbe_dcb_config {\n \tbool vt_mode;\n };\n \n+int txgbe_dcb_pfc_enable(struct txgbe_hw *hw, u8 tc_num);\n+\n /* DCB credits calculation */\n s32 txgbe_dcb_calculate_tc_credits_cee(struct txgbe_hw *,\n \t\t\t\t struct txgbe_dcb_config *, u32, u8);\ndiff --git a/drivers/net/txgbe/base/txgbe_dcb_hw.c b/drivers/net/txgbe/base/txgbe_dcb_hw.c\nindex 778c0ef49..68901012b 100644\n--- a/drivers/net/txgbe/base/txgbe_dcb_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_dcb_hw.c\n@@ -181,6 +181,79 @@ s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,\n \treturn 0;\n }\n \n+/**\n+ * txgbe_dcb_config_pfc_raptor - Configure priority flow control\n+ * @hw: pointer to hardware structure\n+ * @pfc_en: enabled pfc bitmask\n+ * @map: priority to tc assignments indexed by priority\n+ *\n+ * Configure Priority Flow Control (PFC) for each traffic class.\n+ */\n+s32 txgbe_dcb_config_pfc_raptor(struct txgbe_hw *hw, u8 pfc_en, u8 *map)\n+{\n+\tu32 i, j, fcrtl, reg;\n+\tu8 max_tc = 0;\n+\n+\t/* Enable Transmit Priority Flow Control */\n+\twr32(hw, TXGBE_TXFCCFG, TXGBE_TXFCCFG_PFC);\n+\n+\t/* Enable Receive Priority Flow Control */\n+\twr32m(hw, TXGBE_RXFCCFG, TXGBE_RXFCCFG_PFC,\n+\t\tpfc_en ? TXGBE_RXFCCFG_PFC : 0);\n+\n+\tfor (i = 0; i < TXGBE_DCB_UP_MAX; i++) {\n+\t\tif (map[i] > max_tc)\n+\t\t\tmax_tc = map[i];\n+\t}\n+\n+\t/* Configure PFC Tx thresholds per TC */\n+\tfor (i = 0; i <= max_tc; i++) {\n+\t\tint enabled = 0;\n+\n+\t\tfor (j = 0; j < TXGBE_DCB_UP_MAX; j++) {\n+\t\t\tif ((map[j] == i) && (pfc_en & (1 << j))) {\n+\t\t\t\tenabled = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (enabled) {\n+\t\t\treg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |\n+\t\t\t TXGBE_FCWTRHI_XOFF;\n+\t\t\tfcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |\n+\t\t\t\tTXGBE_FCWTRLO_XON;\n+\t\t\twr32(hw, TXGBE_FCWTRLO(i), fcrtl);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * In order to prevent Tx hangs when the internal Tx\n+\t\t\t * switch is enabled we must set the high water mark\n+\t\t\t * to the Rx packet buffer size - 24KB. This allows\n+\t\t\t * the Tx switch to function even under heavy Rx\n+\t\t\t * workloads.\n+\t\t\t */\n+\t\t\treg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;\n+\t\t\twr32(hw, TXGBE_FCWTRLO(i), 0);\n+\t\t}\n+\n+\t\twr32(hw, TXGBE_FCWTRHI(i), reg);\n+\t}\n+\n+\tfor (; i < TXGBE_DCB_TC_MAX; i++) {\n+\t\twr32(hw, TXGBE_FCWTRLO(i), 0);\n+\t\twr32(hw, TXGBE_FCWTRHI(i), 0);\n+\t}\n+\n+\t/* Configure pause time (2 TCs per register) */\n+\treg = hw->fc.pause_time | (hw->fc.pause_time << 16);\n+\tfor (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)\n+\t\twr32(hw, TXGBE_FCXOFFTM(i), reg);\n+\n+\t/* Configure flow control refresh threshold value */\n+\twr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);\n+\n+\treturn 0;\n+}\n+\n /**\n * txgbe_dcb_config_tc_stats_raptor - Config traffic class statistics\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex a91112ee6..2a766af36 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -2799,6 +2799,58 @@ txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \treturn -EIO;\n }\n \n+static int\n+txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)\n+{\n+\tint err;\n+\tuint32_t rx_buf_size;\n+\tuint32_t max_high_water;\n+\tuint8_t tc_num;\n+\tuint8_t map[TXGBE_DCB_UP_MAX] = { 0 };\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);\n+\n+\tenum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {\n+\t\ttxgbe_fc_none,\n+\t\ttxgbe_fc_rx_pause,\n+\t\ttxgbe_fc_tx_pause,\n+\t\ttxgbe_fc_full\n+\t};\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);\n+\ttc_num = map[pfc_conf->priority];\n+\trx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));\n+\tPMD_INIT_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n+\t/*\n+\t * At least reserve one Ethernet frame for watermark\n+\t * high_water/low_water in kilo bytes for txgbe\n+\t */\n+\tmax_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;\n+\tif ((pfc_conf->fc.high_water > max_high_water) ||\n+\t (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid high/low water setup value in KB\");\n+\t\tPMD_INIT_LOG(ERR, \"High_water must <= 0x%x\", max_high_water);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];\n+\thw->fc.pause_time = pfc_conf->fc.pause_time;\n+\thw->fc.send_xon = pfc_conf->fc.send_xon;\n+\thw->fc.low_water[tc_num] = pfc_conf->fc.low_water;\n+\thw->fc.high_water[tc_num] = pfc_conf->fc.high_water;\n+\n+\terr = txgbe_dcb_pfc_enable(hw, tc_num);\n+\n+\t/* Not negotiated is not an error case */\n+\tif ((err == 0) || (err == TXGBE_ERR_FC_NOT_NEGOTIATED))\n+\t\treturn 0;\n+\n+\tPMD_INIT_LOG(ERR, \"txgbe_dcb_pfc_enable = 0x%x\", err);\n+\treturn -EIO;\n+}\n+\n int\n txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n@@ -3284,6 +3336,7 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.tx_queue_release = txgbe_dev_tx_queue_release,\n \t.flow_ctrl_get = txgbe_flow_ctrl_get,\n \t.flow_ctrl_set = txgbe_flow_ctrl_set,\n+\t.priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,\n \t.mac_addr_add = txgbe_add_rar,\n \t.mac_addr_remove = txgbe_remove_rar,\n \t.mac_addr_set = txgbe_set_default_mac_addr,\ndiff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c\nindex c029df56d..d0e40d18c 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.c\n+++ b/drivers/net/txgbe/txgbe_rxtx.c\n@@ -3146,7 +3146,7 @@ txgbe_dcb_hw_configure(struct rte_eth_dev *dev,\n \t\t\tstruct txgbe_dcb_config *dcb_config)\n {\n \tint ret = 0;\n-\tuint8_t i, nb_tcs;\n+\tuint8_t i, pfc_en, nb_tcs;\n \tuint16_t pbsize, rx_buffer_size;\n \tuint8_t config_dcb_rx = 0;\n \tuint8_t config_dcb_tx = 0;\n@@ -3313,6 +3313,26 @@ txgbe_dcb_hw_configure(struct rte_eth_dev *dev,\n \t/* Configure queue statistics registers */\n \ttxgbe_dcb_config_tc_stats_raptor(hw, dcb_config);\n \n+\t/* Check if the PFC is supported */\n+\tif (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {\n+\t\tpbsize = (uint16_t)(rx_buffer_size / nb_tcs);\n+\t\tfor (i = 0; i < nb_tcs; i++) {\n+\t\t\t/*\n+\t\t\t* If the TC count is 8,and the default high_water is 48,\n+\t\t\t* the low_water is 16 as default.\n+\t\t\t*/\n+\t\t\thw->fc.high_water[i] = (pbsize * 3) / 4;\n+\t\t\thw->fc.low_water[i] = pbsize / 4;\n+\t\t\t/* Enable pfc for this TC */\n+\t\t\ttc = &dcb_config->tc_config[i];\n+\t\t\ttc->pfc = txgbe_dcb_pfc_enabled;\n+\t\t}\n+\t\ttxgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);\n+\t\tif (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)\n+\t\t\tpfc_en &= 0x0F;\n+\t\tret = txgbe_dcb_config_pfc(hw, pfc_en, map);\n+\t}\n+\n \treturn ret;\n }\n \n", "prefixes": [ "v2", "46/56" ] }