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GET /api/patches/79354/?format=api
{ "id": 79354, "url": "http://patches.dpdk.org/api/patches/79354/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-18-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200930130415.11211-18-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200930130415.11211-18-ciara.power@intel.com", "date": "2020-09-30T13:04:13", "name": "[v3,17/18] net: add checks for max SIMD bitwidth", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e2c3085e3856a52064c24e08bb655fb8da65070c", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-18-ciara.power@intel.com/mbox/", "series": [ { "id": 12621, "url": "http://patches.dpdk.org/api/series/12621/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12621", "date": "2020-09-30T13:03:56", "name": "add max SIMD bitwidth to EAL", "version": 3, "mbox": "http://patches.dpdk.org/series/12621/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/79354/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/79354/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5EB48A04B5;\n\tWed, 30 Sep 2020 15:13:57 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B32841DBA0;\n\tWed, 30 Sep 2020 15:08:46 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id DA35C1DB61\n for <dev@dpdk.org>; Wed, 30 Sep 2020 15:08:30 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Sep 2020 06:08:29 -0700", "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:27 -0700" ], "IronPort-SDR": [ "\n 50UPfOZPYLWnL5dyXt1qUB1CfTRiHx0jMSbajXuPBWNStzVLlKEh+kQtw3eCpyP8t5QiFsq3uw\n H4uZhTtJMvsg==", "\n tINi71Xq7teoX9BflM9n5VZTHSGVUbiSKUgi1gPqXC3NaqXZ50LFZI+SgMcFEgY9HwA+eShBQh\n hKya+17l160w==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9759\"; a=\"150223510\"", "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"150223510\"", "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"294603281\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "Ciara Power <ciara.power@intel.com>,\n Jasvinder Singh <jasvinder.singh@intel.com>,\n Olivier Matz <olivier.matz@6wind.com>", "Date": "Wed, 30 Sep 2020 14:04:13 +0100", "Message-Id": "<20200930130415.11211-18-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200930130415.11211-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20200930130415.11211-1-ciara.power@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath.\n\nThe vector path was initially chosen in RTE_INIT, however this is no\nlonger suitable as we cannot check the max SIMD bitwidth at that time.\nThe default chosen in RTE_INIT is now scalar. For best performance\nand to use vector paths, apps must explicitly call the set algorithm\nfunction before using other functions from this library, as this is\nwhere vector handlers are now chosen.\n\nSuggested-by: Jasvinder Singh <jasvinder.singh@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n\n---\nv3:\n - Moved choosing vector paths out of RTE_INIT.\n - Moved checking max_simd_bitwidth into the set_alg function.\n---\n lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++---------\n lib/librte_net/rte_net_crc.h | 3 ++-\n 2 files changed, 19 insertions(+), 10 deletions(-)", "diff": "diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c\nindex 9fd4794a9d..241eb16399 100644\n--- a/lib/librte_net/rte_net_crc.c\n+++ b/lib/librte_net/rte_net_crc.c\n@@ -9,6 +9,7 @@\n #include <rte_cpuflags.h>\n #include <rte_common.h>\n #include <rte_net_crc.h>\n+#include <rte_eal.h>\n \n #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)\n #define X86_64_SSE42_PCLMULQDQ 1\n@@ -60,6 +61,9 @@ static rte_net_crc_handler handlers_neon[] = {\n };\n #endif\n \n+static uint16_t max_simd_bitwidth;\n+#define RTE_LOGTYPE_NET RTE_LOGTYPE_USER1\n+\n /**\n * Reflect the bits about the middle\n *\n@@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)\n void\n rte_net_crc_set_alg(enum rte_net_crc_alg alg)\n {\n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n+\n \tswitch (alg) {\n #ifdef X86_64_SSE42_PCLMULQDQ\n \tcase RTE_NET_CRC_SSE42:\n-\t\thandlers = handlers_sse42;\n-\t\tbreak;\n+\t\tif (max_simd_bitwidth >= RTE_MAX_128_SIMD) {\n+\t\t\thandlers = handlers_sse42;\n+\t\t\treturn;\n+\t\t}\n+\t\tRTE_LOG(INFO, NET, \"Max SIMD Bitwidth too low, using scalar\\n\");\n #elif defined ARM64_NEON_PMULL\n \t\t/* fall-through */\n \tcase RTE_NET_CRC_NEON:\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL) &&\n+\t\t\t\tmax_simd_bitwidth >= RTE_MAX_128_SIMD) {\n \t\t\thandlers = handlers_neon;\n-\t\t\tbreak;\n+\t\t\treturn;\n \t\t}\n+\t\tRTE_LOG(INFO, NET, \"Max SIMD Bitwidth too low or CPU flag not enabled, using scalar\\n\");\n #endif\n \t\t/* fall-through */\n \tcase RTE_NET_CRC_SCALAR:\n@@ -184,19 +196,15 @@ rte_net_crc_calc(const void *data,\n /* Select highest available crc algorithm as default one */\n RTE_INIT(rte_net_crc_init)\n {\n-\tenum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;\n-\n \trte_net_crc_scalar_init();\n \n #ifdef X86_64_SSE42_PCLMULQDQ\n-\talg = RTE_NET_CRC_SSE42;\n \trte_net_crc_sse42_init();\n #elif defined ARM64_NEON_PMULL\n \tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {\n-\t\talg = RTE_NET_CRC_NEON;\n \t\trte_net_crc_neon_init();\n \t}\n #endif\n \n-\trte_net_crc_set_alg(alg);\n+\trte_net_crc_set_alg(RTE_NET_CRC_SCALAR);\n }\ndiff --git a/lib/librte_net/rte_net_crc.h b/lib/librte_net/rte_net_crc.h\nindex 16e85ca970..7a45ebe193 100644\n--- a/lib/librte_net/rte_net_crc.h\n+++ b/lib/librte_net/rte_net_crc.h\n@@ -28,7 +28,8 @@ enum rte_net_crc_alg {\n /**\n * This API set the CRC computation algorithm (i.e. scalar version,\n * x86 64-bit sse4.2 intrinsic version, etc.) and internal data\n- * structure.\n+ * structure. This should be called before any other functions, to\n+ * choose the algorithm for best performance.\n *\n * @param alg\n * This parameter is used to select the CRC implementation version.\n", "prefixes": [ "v3", "17/18" ] }