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GET /api/patches/79231/?format=api
{ "id": 79231, "url": "http://patches.dpdk.org/api/patches/79231/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200929205935.20432-3-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200929205935.20432-3-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200929205935.20432-3-ajit.khaparde@broadcom.com", "date": "2020-09-29T20:59:34", "name": "[2/3] net/bnxt: update HWRM structures", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "819c4d9c32f8537c0541a021d74e6160ae75d732", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200929205935.20432-3-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 12601, "url": "http://patches.dpdk.org/api/series/12601/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12601", "date": "2020-09-29T20:59:32", "name": "patchset for bnxt PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/12601/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/79231/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/79231/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 66465A04B1;\n\tTue, 29 Sep 2020 23:00:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4378E1DABD;\n\tTue, 29 Sep 2020 22:59:54 +0200 (CEST)", "from mail-oo1-f99.google.com (mail-oo1-f99.google.com\n [209.85.161.99]) by dpdk.org (Postfix) with ESMTP id 8E84C1DABB\n for <dev@dpdk.org>; Tue, 29 Sep 2020 22:59:51 +0200 (CEST)", "by mail-oo1-f99.google.com with SMTP id t3so1647082ook.8\n for <dev@dpdk.org>; Tue, 29 Sep 2020 13:59:51 -0700 (PDT)", "from C02VPB22HTD6.wifi.broadcom.net ([192.19.223.252])\n by smtp-relay.gmail.com with ESMTPS id f22sm721666otl.7.2020.09.29.13.59.45\n for <dev@dpdk.org>\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Tue, 29 Sep 2020 13:59:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n s=google;\n h=from:to:subject:date:message-id:in-reply-to:references:mime-version\n :content-transfer-encoding;\n bh=uQZHfIOjtfSdGJOIZp+xhJBzLAu5EDwUuVles44rHxY=;\n b=R1tuVgevHNcmInXbIDFA7GrkJ0zRXjmGRSKH5fETZ4BYbvfLhnUdQYtFtl64A1NTDH\n iK1j7AjBxkiYb2UPAeCgv2gKAt/VJZlLpCUm/O3CiehusVorO2FKV6NZ7lKnDCCv2+Ql\n aGW+Bo0fwSoaFDmCBvaaRs0/fnjdJJTTpIZoo=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=uQZHfIOjtfSdGJOIZp+xhJBzLAu5EDwUuVles44rHxY=;\n b=aaGZKu/a5yj8yJxuE7yQsNaL0x2ApZm+fIS810/qt55vQods6WP9Q4PcX0r9fZMzgh\n iXeVk/WaIc0cVrMI+gyM/IjQhCRS5Gxgew6HSpUwgUcqnQ3MmiFgH6KLL0SeFY5+FjKj\n mkyotqwCKeyDr2FjBrskdp3nUBuSXn0MRHmUqve0pESB0RCglF0dY8xZf/frd8JzBy57\n w9Vrrzno8jXbB95LY8KdrSPEV/Kl9gvEQ3C5hOgh9VybcEkp7fK3jYNtUkqggAuf5/Ps\n GpiOc+e/Ywet+39/OI4UjUTQWNz5MkkeWvO8KVIP8eRjjzfi2zmCr0AAHTx7+nBE/2vh\n XzIg==", "X-Gm-Message-State": "AOAM530BzcHIiNaD4zlpjW+SQNX74PV1E8HefVGEqiDErp6rMZcDbQlG\n ESh9mQgTlt4OIwu+Mn7Sy3ErblVf7TwOzsWnFEMi308onWktpEfgwNXL4hcKJm5MlEDKf1KZ9Ob\n upWS9twOMnK601YGN4tmNSYy7bdNPEgk+6g4kqBf1b2CvYCyfrvZ1T2Y/3YHjBaygnEhHSt2J8p\n T58A==", "X-Google-Smtp-Source": "\n ABdhPJxo1GUT5DJnLDKy8Nsa5BY6OLd+uCC7wC38mCQ5TXe5xE2amoiKKFi9XwjLa2ReL6EJvvXndkYMDN24", "X-Received": "by 2002:a4a:4845:: with SMTP id p66mr5971086ooa.68.1601413189393;\n Tue, 29 Sep 2020 13:59:49 -0700 (PDT)", "X-Relaying-Domain": "broadcom.com", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Date": "Tue, 29 Sep 2020 13:59:34 -0700", "Message-Id": "<20200929205935.20432-3-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20200929205935.20432-1-ajit.khaparde@broadcom.com>", "References": "<20200929205935.20432-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 2/3] net/bnxt: update HWRM structures", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "HWRM API to a newer 1.10.1.70 version.\n\nFew fields have been renamed because of this.\nrx_err_pkt -> rx_discard_pkts\nrx_drop_pkts -> rx_error_pkts\n\ntx_err_pkts -> tx_discard_pkts\ntx_drop_pkts -> tx_error_pkts\n\nlink_signal_mode -> active_fec_signal_mode\n\ntx_bd_long_hi.mss -> tx_bd_long_hi.kid_or_ts_high_mss\ntx_bd_long_hi.hdr_size -> tx_bd_long_hi.kid_or_ts_low_hdr_size\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n doc/guides/rel_notes/release_20_11.rst | 1 +\n drivers/net/bnxt/bnxt_hwrm.c | 7 +-\n drivers/net/bnxt/bnxt_txr.c | 27 +-\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 11011 +++++++++++++++--------\n 4 files changed, 7056 insertions(+), 3990 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex c460271be..7d6d5579c 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -84,6 +84,7 @@ New Features\n \n * Added support for 200G PAM4 link speed.\n * Added support for RSS hash level selection.\n+ * Updated HWRM structures to 1.10.1.70 version.\n \n \n Removed Items\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex fc89cc29a..faeaf4b5d 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -1364,7 +1364,8 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,\n \tlink_info->phy_ver[0] = resp->phy_maj;\n \tlink_info->phy_ver[1] = resp->phy_min;\n \tlink_info->phy_ver[2] = resp->phy_bld;\n-\tlink_info->link_signal_mode = rte_le_to_cpu_16(resp->link_signal_mode);\n+\tlink_info->link_signal_mode =\n+\t\trte_le_to_cpu_16(resp->active_fec_signal_mode);\n \tlink_info->force_pam4_link_speed =\n \t\t\trte_le_to_cpu_16(resp->force_pam4_link_speed);\n \tlink_info->support_pam4_speeds =\n@@ -4011,8 +4012,8 @@ int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,\n \t\tstats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);\n \t\tstats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);\n \t\tstats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);\n-\t\tstats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);\n-\t\tstats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);\n+\t\tstats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);\n+\t\tstats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);\n \t} else {\n \t\tstats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);\n \t\tstats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);\ndiff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c\nindex 20683315e..c55497960 100644\n--- a/drivers/net/bnxt/bnxt_txr.c\n+++ b/drivers/net/bnxt/bnxt_txr.c\n@@ -216,6 +216,10 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \t\t\t\t\t&txr->tx_desc_ring[txr->tx_prod];\n \t\ttxbd1->lflags = 0;\n \t\ttxbd1->cfa_meta = vlan_tag_flags;\n+\t\t/* Legacy tx_bd_long_hi->mss =\n+\t\t * tx_bd_long_hi->kid_or_ts_high_mss\n+\t\t */\n+\t\ttxbd1->kid_or_ts_high_mss = 0;\n \n \t\tif (txq->vfr_tx_cfa_action)\n \t\t\ttxbd1->cfa_action = txq->vfr_tx_cfa_action;\n@@ -235,91 +239,76 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \t\t\t\t tx_pkt->outer_l3_len : 0;\n \t\t\t/* The hdr_size is multiple of 16bit units not 8bit.\n \t\t\t * Hence divide by 2.\n+\t\t\t * Also legacy hdr_size = kid_or_ts_low_hdr_size.\n \t\t\t */\n-\t\t\ttxbd1->hdr_size = hdr_size >> 1;\n-\t\t\ttxbd1->mss = tx_pkt->tso_segsz;\n-\t\t\tRTE_VERIFY(txbd1->mss);\n+\t\t\ttxbd1->kid_or_ts_low_hdr_size = hdr_size >> 1;\n+\t\t\ttxbd1->kid_or_ts_high_mss = tx_pkt->tso_segsz;\n+\t\t\tRTE_VERIFY(txbd1->kid_or_ts_high_mss);\n \n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_TCP_UDP_CKSUM) ==\n \t\t\t PKT_TX_OIP_IIP_TCP_UDP_CKSUM) {\n \t\t\t/* Outer IP, Inner IP, Inner TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_TCP_CKSUM) ==\n \t\t\t PKT_TX_OIP_IIP_TCP_CKSUM) {\n \t\t\t/* Outer IP, Inner IP, Inner TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_UDP_CKSUM) ==\n \t\t\t PKT_TX_OIP_IIP_UDP_CKSUM) {\n \t\t\t/* Outer IP, Inner IP, Inner TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_IIP_TCP_UDP_CKSUM) ==\n \t\t\t PKT_TX_IIP_TCP_UDP_CKSUM) {\n \t\t\t/* (Inner) IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_IIP_UDP_CKSUM) ==\n \t\t\t PKT_TX_IIP_UDP_CKSUM) {\n \t\t\t/* (Inner) IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_IIP_TCP_CKSUM) ==\n \t\t\t PKT_TX_IIP_TCP_CKSUM) {\n \t\t\t/* (Inner) IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_IP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_TCP_UDP_CKSUM) ==\n \t\t\t PKT_TX_OIP_TCP_UDP_CKSUM) {\n \t\t\t/* Outer IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_UDP_CKSUM) ==\n \t\t\t PKT_TX_OIP_UDP_CKSUM) {\n \t\t\t/* Outer IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_TCP_CKSUM) ==\n \t\t\t PKT_TX_OIP_TCP_CKSUM) {\n \t\t\t/* Outer IP, (Inner) TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OIP_IIP_CKSUM) ==\n \t\t\t PKT_TX_OIP_IIP_CKSUM) {\n \t\t\t/* Outer IP, Inner IP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_FLG_TIP_IP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_TCP_UDP_CKSUM) ==\n \t\t\t PKT_TX_TCP_UDP_CKSUM) {\n \t\t\t/* TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_TCP_CKSUM) ==\n \t\t\t PKT_TX_TCP_CKSUM) {\n \t\t\t/* TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_UDP_CKSUM) ==\n \t\t\t PKT_TX_UDP_CKSUM) {\n \t\t\t/* TCP/UDP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_IP_CKSUM) ==\n \t\t\t PKT_TX_IP_CKSUM) {\n \t\t\t/* IP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_IP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_OUTER_IP_CKSUM) ==\n \t\t\t PKT_TX_OUTER_IP_CKSUM) {\n \t\t\t/* IP CSO */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_T_IP_CHKSUM;\n-\t\t\ttxbd1->mss = 0;\n \t\t} else if ((tx_pkt->ol_flags & PKT_TX_IEEE1588_TMST) ==\n \t\t\t PKT_TX_IEEE1588_TMST) {\n \t\t\t/* PTP */\n \t\t\ttxbd1->lflags |= TX_BD_LONG_LFLAGS_STAMP;\n-\t\t\ttxbd1->mss = 0;\n \t\t}\n \t} else {\n \t\ttxbd->flags_type |= TX_BD_SHORT_TYPE_TX_BD_SHORT;\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 8dfc14b1e..72100919d 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -392,7 +392,11 @@ struct cmd_nums {\n \t#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)\n \t#define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)\n \t#define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)\n-\t#define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)\n+\t/* Reserved. */\n+\t#define HWRM_RESERVED7 UINT32_C(0xba)\n+\t#define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)\n+\t#define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)\n+\t#define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)\n \t#define HWRM_FW_RESET UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS UINT32_C(0xc1)\n \t#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)\n@@ -619,7 +623,7 @@ struct cmd_nums {\n \t#define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)\n \t/* Queries extended stats per function */\n \t#define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)\n-\t/* Queries extended statistics context */\n+\t/* Queries extended statitics context */\n \t#define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST UINT32_C(0x200)\n@@ -677,6 +681,12 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)\n \t/* Experimental */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)\n+\t/* Experimental */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)\n+\t/* Experimental */\n+\t#define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)\n+\t/* Experimental */\n \t#define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)\n \t/* Experimental */\n \t#define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)\n@@ -860,6 +870,11 @@ struct ret_codes {\n \t * may try again later.\n \t */\n \t#define HWRM_ERR_CODE_BUSY UINT32_C(0x10)\n+\t/*\n+\t * This error code is reported by Firmware when an operation requested\n+\t * by the host is not allowed due to a secure lock violation.\n+\t */\n+\t#define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)\n \t/*\n \t * This value indicates that the HWRM response is in TLV format and\n \t * should be interpreted as one or more TLVs starting with the\n@@ -947,8 +962,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 56\n-#define HWRM_VERSION_STR \"1.10.1.56\"\n+#define HWRM_VERSION_RSVD 70\n+#define HWRM_VERSION_STR \"1.10.1.70\"\n \n /****************\n * hwrm_ver_get *\n@@ -1499,6 +1514,645 @@ struct hwrm_ver_get_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/* cfa_bds_read_cmd_data_msg (size:128b/16B) */\n+struct cfa_bds_read_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/*\n+\t * This is read command. From 32 to 128B can be read from a table\n+\t * using this command.\n+\t */\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ\n+\t/* This value selects the table type to be acted upon. */\n+\tuint8_t\ttable_type;\n+\t/* This value selects the table type to be acted upon. */\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0\n+\t/* This command acts on the action table of the specified scope. */\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)\n+\t/* This command acts on the exact match table of the specified scope. */\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \\\n+\t\tCFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed. A\n+\t * value of zero is invalid. Maximum value is 4.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0\n+\t/* This is the 32B index into the selected table to access. */\n+\tuint32_t\ttable_index;\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)\n+\t#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+\t/*\n+\t * This is the 64b host address where you want the data returned to. The\n+\t * data will be written to the same function as the one that owns the SQ\n+\t * this command is read from. The bottom two bits of this value must be\n+\t * zero. The size of the write is controlled by the data_size field.\n+\t */\n+\tuint64_t\thost_address;\n+} __rte_packed;\n+\n+/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */\n+struct cfa_bds_write_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/*\n+\t * This is write command. From 32 to 128B can be written to a table\n+\t * using this command.\n+\t */\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE\n+\t/* This value selects the table type to be acted upon. */\n+\tuint8_t\twrite_thru_table_type;\n+\t/* This value selects the table type to be acted upon. */\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0\n+\t/* This command acts on the action table of the specified scope. */\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)\n+\t/* This command acts on the exact match table of the specified scope. */\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \\\n+\t\tCFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM\n+\t/*\n+\t * Indicates write-through control. Indicates write-through when set,\n+\t * or write back when cleared.\n+\t */\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed. A\n+\t * value of zero is invalid. Maximum value is 4.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0\n+\t/* This is the 32B index into the selected table to access. */\n+\tuint32_t\ttable_index;\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)\n+\t#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+\tuint32_t\tunused0;\n+\tuint32_t\tunused1;\n+\t/*\n+\t * This is the data to be written. Data length is determined by the\n+\t * data_size field. The bd_cnt in the encapsulating BD must also be set\n+\t * correctly to ensure that the BD is processed correctly and the full\n+\t * WRITE_CMD message is extracted from the BD.\n+\t */\n+\tuint32_t\tdta[32];\n+} __rte_packed;\n+\n+/* cfa_bds_read_clr_cmd_data_msg (size:192b/24B) */\n+struct cfa_bds_read_clr_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/*\n+\t * This is read-clear command. 32B can be read from a table and\n+\t * a 16b mask can be used to clear specific 16b units after the\n+\t * read as an atomic operation.\n+\t */\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR\n+\t/* This value selects the table type to be acted upon. */\n+\tuint8_t\ttable_type;\n+\t/* This value selects the table type to be acted upon. */\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0\n+\t/* This command acts on the action table of the specified scope. */\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)\n+\t/* This command acts on the exact match table of the specified scope. */\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \\\n+\t\tCFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\tuint8_t\tunused0;\n+\t/* This is the 32B index into the selected table to access. */\n+\tuint32_t\ttable_index;\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \\\n+\t\tUINT32_C(0x3ffffff)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+\t/*\n+\t * This is the 64b host address where you want the data returned to. The\n+\t * data will be written to the same function as the one that owns the SQ\n+\t * this command is read from. The bottom two bits of this value must be\n+\t * zero. The size of the write is controlled by the data_size field.\n+\t */\n+\tuint64_t\thost_address;\n+\t/*\n+\t * This is active high clear mask for the 32B of data that this command\n+\t * can read. Bit 0 of the field will clear bits 15:0 of the first word\n+\t * of data read when set to '1'.\n+\t */\n+\tuint16_t\tclear_mask;\n+\tuint16_t\tunused1[3];\n+} __rte_packed;\n+\n+/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */\n+struct cfa_bds_em_insert_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/*\n+\t * An exact match table insert will be attempted into the table.\n+\t * If there is a free location in the bucket, the payload will\n+\t * be written to the bucket.\n+\t */\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT\n+\t/*\n+\t * Indicates write-through control. Indicates write-through when set,\n+\t * or write back when cleared.\n+\t */\n+\tuint8_t\twrite_thru;\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0\n+\t/*\n+\t * Indicates write-through control. Indicates write-through when set,\n+\t * or write back when cleared.\n+\t */\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed. A\n+\t * value of zero is invalid. Maximum value is 4.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0\n+\t/* This is the 32B index into the selected table to access. */\n+\tuint32_t\ttable_index;\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \\\n+\t\tUINT32_C(0x3ffffff)\n+\t#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+\t/*\n+\t * This is the 64b host address where you want the data returned to. The\n+\t * data will be written to the same function as the one that owns the SQ\n+\t */\n+\tuint64_t\thost_address;\n+\t/*\n+\t * This is the Exact Match Lookup Record. Data length is determined by\n+\t * the data_size field. The bd_cnt in the encapsulating BD must also be\n+\t */\n+\tuint32_t\tdta[32];\n+} __rte_packed;\n+\n+/* cfa_bds_em_delete_cmd_data_msg (size:192b/24B) */\n+struct cfa_bds_em_delete_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/* An exact match table delete will be attempted. */\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE\n+\t/*\n+\t * Indicates write-through control. Indicates write-through when set,\n+\t * or write back when cleared.\n+\t */\n+\tuint8_t\twrite_thru;\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0\n+\t/*\n+\t * Indicates write-through control. Indicates write-through when set,\n+\t * or write back when cleared.\n+\t */\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed. A\n+\t * value of zero is invalid. Maximum value is 4.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0\n+\tuint32_t\tunused0;\n+\t/*\n+\t * This is the 64b host address where you want the data returned to. The\n+\t * data will be written to the same function as the one that owns the SQ\n+\t */\n+\tuint64_t\thost_address;\n+\t/*\n+\t * This is the Exact Match Lookup Record. Data length is determined by\n+\t * the data_size field. The bd_cnt in the encapsulating BD must also be\n+\t */\n+\tuint64_t\tdta;\n+} __rte_packed;\n+\n+/* cfa_bds_invalidate_cmd_data_msg (size:64b/8B) */\n+struct cfa_bds_invalidate_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/*\n+\t * The specified table area will be invalidated. If it is needed.\n+\t * again, it will be read from the backing store.\n+\t */\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE\n+\t/* This value selects the table type to be acted upon. */\n+\tuint8_t\ttable_type;\n+\t/* This value selects the table type to be acted upon. */\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0\n+\t/* This command acts on the action table of the specified scope. */\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \\\n+\t\tUINT32_C(0x0)\n+\t/* This command acts on the exact match table of the specified scope. */\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \\\n+\t\tUINT32_C(0x1)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \\\n+\t\tCFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\tuint8_t\tunused0;\n+\t/* This is the 32B index into the selected table to access. */\n+\tuint32_t\ttable_index;\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \\\n+\t\tUINT32_C(0x3ffffff)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+} __rte_packed;\n+\n+/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */\n+struct cfa_bds_event_collect_cmd_data_msg {\n+\t/* This value selects the format for the mid-path command for the CFA. */\n+\tuint8_t\topcode;\n+\t/* Reads notification messages from the Host Notification Queue. */\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \\\n+\t\tUINT32_C(0x6)\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT\n+\tuint8_t\tunused0;\n+\t/* This value selects which table scope will be accessed. */\n+\tuint8_t\ttable_scope;\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \\\n+\t\tUINT32_C(0x1f)\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed. A\n+\t * value of zero is invalid. Maximum value is 4.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0\n+\tuint32_t\tunused1;\n+\t/*\n+\t * This is the 64b host address where you want the data returned to. The\n+\t * data will be written to the same function as the one that owns the SQ\n+\t */\n+\tuint64_t\thost_address;\n+} __rte_packed;\n+\n+/* ce_bds_add_data_msg (size:512b/64B) */\n+struct ce_bds_add_data_msg {\n+\tuint32_t\tversion_algorithm_kid_opcode;\n+\t/*\n+\t * This value selects the operation for the mid-path command for the\n+\t * crypto blocks.\n+\t */\n+\t#define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)\n+\t#define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0\n+\t/*\n+\t * This is the add command. Using this opcode, Host Driver can add\n+\t * information required for kTLS processing. The information is\n+\t * updated in the CFCK context.\n+\t */\n+\t#define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)\n+\t#define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \\\n+\t\tCE_BDS_ADD_DATA_MSG_OPCODE_ADD\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated kTLS offloaded connection.\n+\t */\n+\t#define CE_BDS_ADD_DATA_MSG_KID_MASK \\\n+\t\tUINT32_C(0xfffff0)\n+\t#define CE_BDS_ADD_DATA_MSG_KID_SFT 4\n+\t/*\n+\t * Currently only two algorithms are supported, AES_GCM_128 and\n+\t * AES_GCM_256. Additional bits for future growth.\n+\t */\n+\t#define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \\\n+\t\tUINT32_C(0xf000000)\n+\t#define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24\n+\t/* AES_GCM_128 Algorithm */\n+\t#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \\\n+\t\tUINT32_C(0x1000000)\n+\t/* AES_GCM_256 Algorithm */\n+\t#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \\\n+\t\tUINT32_C(0x2000000)\n+\t/*\n+\t * Version number of TLS connection. HW will provide registers that\n+\t * converts the 4b encoded version number to 16b of actual version\n+\t * number in the TLS Header. * Initialized --> By mid-path command *\n+\t * Updated --> Never though another mid-path command will result in an\n+\t * update.\n+\t */\n+\t#define CE_BDS_ADD_DATA_MSG_VERSION_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t#define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28\n+\t/* TLS1.2 Version */\n+\t#define CE_BDS_ADD_DATA_MSG__TLS1_2 \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* TLS1.3 Version */\n+\t#define CE_BDS_ADD_DATA_MSG__TLS1_3 \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define CE_BDS_ADD_DATA_MSG__LAST \\\n+\t\tCE_BDS_ADD_DATA_MSG__TLS1_3\n+\t/*\n+\t * Command Type in the TLS header. HW will provide registers that\n+\t * converts the 3b encoded command type to 8b of actual command type in\n+\t * the TLS Header. * Initialized --> By mid-path command * Updated -->\n+\t * Never though another mid-path command will result in an update\n+\t */\n+\tuint8_t\tcmd_type;\n+\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)\n+\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0\n+\t/* Application */\n+\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)\n+\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \\\n+\t\tCE_BDS_ADD_DATA_MSG_CMD_TYPE_APP\n+\tuint8_t\tunused0[3];\n+\t/*\n+\t * Salt is part of the nonce that is used as the Initial Vector (IV) in\n+\t * AES-GCM cipher suites. These are exchanged as part of the handshake\n+\t * process and is either the client_write_iv (when the client is\n+\t * sending) or server_write_iv (when the server is sending). In\n+\t * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to\n+\t * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number\n+\t * is zero padded to 12B and then xor'ed with the 4B of salt to generate\n+\t * the 12B of IV. This value is initialized by this mid-path command.\n+\t */\n+\tuint32_t\tsalt;\n+\tuint32_t\tunused1;\n+\t/*\n+\t * This field keeps track of the TCP sequence number that is expected as\n+\t * the first byte in the next TCP packet. This field is calculated by HW\n+\t * using the output of the parser. The field is initialized as part of\n+\t * the Mid-path BD download/update of a kTLS connection. For every TCP\n+\t * packet processed, TCE HW will update the value to Current packet TCP\n+\t * sequence number + Current packet TCP Payload Length.\n+\t */\n+\tuint32_t\tpkt_tcp_seq_num;\n+\t/*\n+\t * This field maintains the TCP sequence number of the first byte in the\n+\t * header of the active TLS record. This field is initialized as part of\n+\t * the Mid-path BD download/update of a kTLS connection. For every\n+\t * record that is processed, TCE HW copies the value from the\n+\t * next_tls_header_tcp_seq_num field.\n+\t */\n+\tuint32_t\ttls_header_tcp_seq_num;\n+\t/*\n+\t * This is sequence number for the TLS record in a particular session.\n+\t * In TLS1.2, record sequence number is part of the Associated Data (AD)\n+\t * in the AEAD algorithm. In TLS1.3, record sequence number is part of\n+\t * the Initial Vector (IV). The field is initialized as part of the\n+\t * mid-path BD download/update of a kTLS connection. TCE HW increments\n+\t * the field after that for every record processed as it parses the TCP\n+\t * packet.\n+\t */\n+\tuint32_t\trecord_seq_num[2];\n+\t/*\n+\t * Key used for encrypting or decrypting TLS records. The Key is\n+\t * exchanged during the hand-shake protocol by the client-server and\n+\t * provided to HW through this mid-path BD.\n+\t */\n+\tuint32_t\tsession_key[8];\n+} __rte_packed;\n+\n+/* ce_bds_delete_data_msg (size:64b/8B) */\n+struct ce_bds_delete_data_msg {\n+\tuint32_t\tkid_opcode;\n+\t/*\n+\t * This value selects the operation for the mid-path command for the\n+\t * crypto blocks.\n+\t */\n+\t#define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)\n+\t#define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0\n+\t/*\n+\t * This is the delete command. Using this opcode, the host Driver\n+\t * can remove a key context from the CFCK. If context is deleted\n+\t * and packets with the same KID come through the pipeline, the\n+\t * following actions are taken. For transmit packets, no crypto\n+\t * operation will be performed, payload will be zero'ed out. For\n+\t * receive packets, no crypto operation will be performed,\n+\t * payload will be unmodified.\n+\t */\n+\t#define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)\n+\t#define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \\\n+\t\tCE_BDS_DELETE_DATA_MSG_OPCODE_DELETE\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated kTLS offloaded connection.\n+\t */\n+\t#define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)\n+\t#define CE_BDS_DELETE_DATA_MSG_KID_SFT 4\n+\tuint32_t\tunused0;\n+} __rte_packed;\n+\n+/* ce_bds_resync_resp_ack_msg (size:128b/16B) */\n+struct ce_bds_resync_resp_ack_msg {\n+\tuint32_t\tresync_status_kid_opcode;\n+\t/*\n+\t * This value selects the operation for the mid-path command for the\n+\t * crypto blocks.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0\n+\t/*\n+\t * This command is used by the driver as a response to the resync\n+\t * request sent by the crypto engine.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \\\n+\t\tCE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated kTLS offloaded connection.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4\n+\t/*\n+\t * This field indicates if the resync request resulted in a success or\n+\t * a failure.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \\\n+\t\tUINT32_C(0x1000000)\n+\t/*\n+\t * An ACK indicates that the driver was able to find the TLS record\n+\t * associated with TCP sequence number provided by the HW\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \\\n+\t\t(UINT32_C(0x0) << 24)\n+\t#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \\\n+\t\tCE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK\n+\t/*\n+\t * This field is the echo of the TCP sequence number provided in the\n+\t * resync request by the HW. If HW sent multiple resync requests, it\n+\t * only tracks the latest TCP sequence number. When the response from\n+\t * the Driver doesn't match the latest request, HW will drop the resync\n+\t * response.\n+\t */\n+\tuint32_t\tresync_record_tcp_seq_num;\n+\t/*\n+\t * This field indicates the TLS record sequence number associated with\n+\t * the resync request. HW will take this number and add the delta records\n+\t * it has found since sending the resync request, update the context and\n+\t * resume decrypting records.\n+\t */\n+\tuint32_t\tresync_record_seq_num[2];\n+} __rte_packed;\n+\n+/* ce_bds_resync_resp_nack_msg (size:64b/8B) */\n+struct ce_bds_resync_resp_nack_msg {\n+\tuint32_t\tresync_status_kid_opcode;\n+\t/*\n+\t * This value selects the operation for the mid-path command for the\n+\t * crypto blocks.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0\n+\t/*\n+\t * This command is used by the driver as a response to the resync\n+\t * request sent by the crypto engine.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \\\n+\t\tCE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated kTLS offloaded connection.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \\\n+\t\tUINT32_C(0xfffff0)\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4\n+\t/*\n+\t * This field indicates if the resync request resulted in a success or\n+\t * a failure.\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \\\n+\t\tUINT32_C(0x1000000)\n+\t/*\n+\t * An NAK indicates that the driver wasn't able to find the TLS\n+\t * record associated with TCP sequence number provided by the HW\n+\t */\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \\\n+\t\t(UINT32_C(0x1) << 24)\n+\t#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \\\n+\t\tCE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK\n+\t/*\n+\t * This field is the echo of the TCP sequence number provided in the\n+\t * resync request by the HW. If HW sent multiple resync requests, it\n+\t * only tracks the latest TCP sequence number. When the response from\n+\t * the Driver doesn't match the latest request, HW will drop the resync\n+\t * response.\n+\t */\n+\tuint32_t\tresync_record_tcp_seq_num;\n+} __rte_packed;\n+\n+/* crypto_presync_bd_cmd (size:256b/32B) */\n+struct crypto_presync_bd_cmd {\n+\tuint8_t\tflags;\n+\t/*\n+\t * Typically, presync BDs are used for packet retransmissions. Source\n+\t * port sends all the packets in order over the network to destination\n+\t * port and packets get dropped in the network. The destination port\n+\t * will request retranmission of dropped packets and source port driver\n+\t * will send presync BD to setup the transmitter appropriately. It will\n+\t * provide the start and end TCP sequence number of the data to be\n+\t * transmitted. HW keeps two sets of context variable, one for in order\n+\t * traffic and one for retransmission traffic. HW is designed to\n+\t * transmit everything posted in the presync BD and return to in order\n+\t * mode after that. No inorder context variables are updated in the\n+\t * process. There is a special case where packets can be dropped\n+\t * between the TCP stack and Device Driver (Berkley Packet Filter for\n+\t * ex) and HW still needs to transmit rest of the traffic. In this\n+\t * mode, driver will send a presync BD as if it is a retransmission but\n+\t * at the end of the transmission, the in order variables need to be\n+\t * updated. This flag is used by driver to indicate that in order\n+\t * variables needs to be updated at the end of completing the task\n+\t * associated with the presync BD.\n+\t */\n+\t#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused0;\n+\tuint16_t\tunused1;\n+\t/*\n+\t * This field maintains the TCP sequence number of the first byte in the\n+\t * Header of the active TLS record. This field is set to 0 during\n+\t * mid-path BD updates, but is set to correct value when a presync BD is\n+\t * detected. For every record that is processed, the value from the\n+\t * next_tls_header_tcp_seq_num field is copied.\n+\t */\n+\tuint32_t\theader_tcp_seq_num;\n+\t/*\n+\t * When a retransmitted packet has a TLS authentication TAG present and\n+\t * the data spans multiple TCP Packets, HW is required to read the entire\n+\t * record to recalculate the TAG but only transmit what is required. This\n+\t * field is the start TCP sequence number of the packet(s) that need to\n+\t * be re-transmitted. This field is initialized to 0 during Mid-path BD\n+\t * add command and initialized to value provided by the driver when\n+\t * Pre-sync BD is detected. This field is never updated unless another\n+\t * Pre-sync BD signaling a new retransmission is scheduled.\n+\t */\n+\tuint32_t\tstart_tcp_seq_num;\n+\t/*\n+\t * When a retransmitted packet has a TLS authentication TAG present and\n+\t * the data spans multiple TCP Packets, HW is required to read the\n+\t * entire record to recalculate the TAG but only transmit what is\n+\t * required. This field is the end TCP sequence number of the packet(s)\n+\t * that need to be re-transmitted. This field is initialized to 0 during\n+\t * Mid-path BD add command and initialized to value provided by the\n+\t * driver when Pre-sync BD is detected. This field is never updated\n+\t * unless another Pre-sync BD signaling a new retransmission is\n+\t * scheduled.\n+\t */\n+\tuint32_t\tend_tcp_seq_num;\n+\t/*\n+\t * For TLS1.2, an explicit nonce is used as part of the IV (concatenated\n+\t * with the SALT). For retans packets, this field is extracted from the\n+\t * TLS record, field right after the TLS Header and stored in the\n+\t * context. This field needs to be stored in context as TCP segmentation\n+\t * could have split the field into multiple TCP packets. This value is\n+\t * initialized to 0 when presync BD is detected by taking the value from\n+\t * the first TLS header. When subsequent TLS Headers are detected, the\n+\t * value is extracted from packet.\n+\t */\n+\tuint32_t\texplicit_nonce[2];\n+\t/*\n+\t * This is sequence number for the TLS record in a particular session. In\n+\t * TLS1.2, record sequence number is part of the Associated Data (AD) in\n+\t * the AEAD algorithm. In TLS1.3, record sequence number is part of the\n+\t * Initial Vector (IV). The field is initialized to 0 during Mid-path BD\n+\t * download. Is initialized to correct value when a pre-sync BD is\n+\t * detected. TCE HW increments the field after that for every record\n+\t * processed as it parses the TCP packet. Subsequent pre-sync BDs\n+\t * delivering more retransmission instruction will also update this\n+\t * field.\n+\t */\n+\tuint32_t\trecord_seq_num[2];\n+} __rte_packed;\n+\n /* bd_base (size:64b/8B) */\n struct bd_base {\n \tuint8_t\ttype;\n@@ -1530,6 +2184,16 @@ struct bd_base {\n \t * RX Producer Assembly Buffer Descriptor.\n \t */\n \t#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)\n+\t/*\n+\t * Indicates that this BD is used to issue a command to one of\n+\t * the mid-path destinations.\n+\t */\n+\t#define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)\n+\t/*\n+\t * Indicates that this BD is used to issue a cryptographic pre-\n+\t * sync command through the fast path and destined for TCE.\n+\t */\n+\t#define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)\n \t/*\n \t * Indicates that this BD is 32B long and is used for\n \t * normal L2 packet transmission.\n@@ -1642,7 +2306,12 @@ struct tx_bd_short {\n \t * used for any data that the driver wants to associate with the\n \t * transmit BD.\n \t *\n-\t * This field must be valid on the first BD of a packet.\n+\t * This field must be valid on the first BD of a packet. If completion\n+\t * coalescing is enabled on the TX ring, it is suggested that the driver\n+\t * populate the opaque field to indicate the specific TX ring with which\n+\t * the completion is associated, then utilize the opaque and sq_cons_idx\n+\t * fields in the coalesced completion record to determine the specific\n+\t * packets that are to be completed on that ring.\n \t */\n \tuint32_t\topaque;\n \t/*\n@@ -1745,11 +2414,16 @@ struct tx_bd_long {\n \t */\n \tuint16_t\tlen;\n \t/*\n-\t * The opaque data field is pass through to the completion and can be\n+\t * The opaque data field is passed through to the completion and can be\n \t * used for any data that the driver wants to associate with the\n \t * transmit BD.\n \t *\n-\t * This field must be valid on the first BD of a packet.\n+\t * This field must be valid on the first BD of a packet. If completion\n+\t * coalescing is enabled on the TX ring, it is suggested that the driver\n+\t * populate the opaque field to indicate the specific TX ring with which\n+\t * the completion is associated, then utilize the opaque and sq_cons_idx\n+\t * fields in the coalesced completion record to determine the specific\n+\t * packets that are to be completed on that ring.\n \t */\n \tuint32_t\topaque;\n \t/*\n@@ -1802,7 +2476,7 @@ struct tx_bd_long_hi {\n \t#define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)\n \t/*\n \t * If set to 1, the device will record the time at which the packet\n-\t * was actually transmitted at the TX MAC.\n+\t * was actually transmitted at the TX MAC for 2-step time sync.\n \t *\n \t * This bit must be valid on the first BD of a packet.\n \t */\n@@ -1829,9 +2503,9 @@ struct tx_bd_long_hi {\n \t * Send Offload) processing for both normal or encapsulated\n \t * packets, which is a form of TCP segmentation. When this bit\n \t * is 1, the hdr_size and mss fields must be valid. The driver\n-\t * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum\n-\t * flags since the controller will replace the appropriate\n-\t * checksum fields for segmented packets.\n+\t * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and\n+\t * tcp_udp_chksum flags since the controller will replace the\n+\t * appropriate checksum fields for segmented packets.\n \t *\n \t * When this bit is 1, the hdr_size and mss fields must be valid.\n \t */\n@@ -1868,7 +2542,47 @@ struct tx_bd_long_hi {\n \t * packet. Packet must be a valid FCoE format packet.\n \t */\n \t#define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)\n-\tuint16_t\thdr_size;\n+\t/*\n+\t * If set to '1', then the timestamp from the BD is used. If cleared\n+\t * to 0, then TWE provides the timestamp.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)\n+\t/*\n+\t * If set to '1', this operation will cause a trace capture in each\n+\t * block it passes through.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)\n+\t/*\n+\t * If set to '1', the device will record the time at which the packet\n+\t * was actually transmitted at the TX MAC for 1-step time sync. This\n+\t * bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)\n+\t/*\n+\t * If set to '1', the controller replaces the Outer-tunnel IP checksum\n+\t * field with hardware calculated IP checksum for the IP header of the\n+\t * packet associated with this descriptor. For outer UDP checksum, it\n+\t * will be the following behavior for all cases independent of settings\n+\t * of inner LSO and checksum offload BD flags. If outer UDP checksum\n+\t * is 0, then do not update it. If outer UDP checksum is non zero, then\n+\t * the hardware should compute and update it.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)\n+\t/*\n+\t * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP\n+\t * header will not be modified during LSO operations. If set to one\n+\t * when LSO is '1', then the IPID of the Outer-tunnel IP header will be\n+\t * incremented for each subsequent segment of an LSO operation. The\n+\t * flag is ignored if the LSO packet is a normal (non-tunneled) TCP\n+\t * packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)\n+\t/*\n+\t * If set to '1', When set to 1, KTLS encryption will be enabled for\n+\t * the packet.\n+\t */\n+\t#define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)\n+\tuint16_t\tkid_or_ts_low_hdr_size;\n \t/*\n \t * When LSO is '1', this field must contain the offset of the\n \t * TCP payload from the beginning of the packet in as\n@@ -1878,9 +2592,16 @@ struct tx_bd_long_hi {\n \t *\n \t * This value must be valid on the first BD of a packet.\n \t */\n-\t#define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)\n-\t#define TX_BD_LONG_HDR_SIZE_SFT 0\n-\tuint32_t\tmss;\n+\t#define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)\n+\t#define TX_BD_LONG_HDR_SIZE_SFT 0\n+\t/*\n+\t * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit\n+\t * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the\n+\t * 20-bit KID.\n+\t */\n+\t#define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)\n+\t#define TX_BD_LONG_KID_OR_TS_LOW_SFT 9\n+\tuint32_t\tkid_or_ts_high_mss;\n \t/*\n \t * This is the MSS value that will be used to do the LSO processing.\n \t * The value is the length in bytes of the TCP payload for each\n@@ -1888,9 +2609,22 @@ struct tx_bd_long_hi {\n \t *\n \t * This value must be valid on the first BD of a packet.\n \t */\n-\t#define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)\n-\t#define TX_BD_LONG_MSS_SFT 0\n-\tuint16_t\tunused2;\n+\t#define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)\n+\t#define TX_BD_LONG_MSS_SFT 0\n+\t/*\n+\t * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit\n+\t * timestamp. If lflags.crypto_en is 1, the least significant 13 bits\n+\t * of this field contain the upper 13 bits of the 20-bit KID.\n+\t */\n+\t#define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)\n+\t#define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15\n+\t/*\n+\t * This value selects bits 25:16 of the CFA action to perform on the\n+\t * packet. See the cfa_action field for more information.\n+\t */\n+\tuint16_t\tcfa_action_high;\n+\t#define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)\n+\t#define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0\n \t/*\n \t * This value selects a CFA action to perform on the packet.\n \t * Set this value to zero if no CFA action is desired.\n@@ -2025,7 +2759,12 @@ struct tx_bd_long_inline {\n \t/*\n \t * The opaque data field is passed through to the completion and can be\n \t * used for any data that the driver wants to associate with the transmit\n-\t * BD.\n+\t * BD. This field must be valid on the first BD of a packet. If\n+\t * completion coalescing is enabled on the TX ring, it is suggested that\n+\t * the driver populate the opaque field to indicate the specific TX ring\n+\t * with which the completion is associated, then utilize the opaque and\n+\t * sq_cons_idx fields in the coalesced completion record to determine\n+\t * the specific packets that are to be completed on that ring.\n \t *\n \t * This field must be valid on the first BD of a packet.\n \t */\n@@ -2063,7 +2802,8 @@ struct tx_bd_long_inline {\n \t#define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)\n \t/*\n \t * If set to 1, the device will record the time at which the packet\n-\t * was actually transmitted at the TX MAC.\n+\t * was actually transmitted at the TX MAC for 2-step time sync. This\n+\t * bit must be valid on the first BD of a packet.\n \t */\n \t#define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)\n \t/*\n@@ -2092,9 +2832,73 @@ struct tx_bd_long_inline {\n \t * packet. Packet must be a valid FCoE format packet.\n \t */\n \t#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)\n-\tuint16_t\tunused2;\n-\tuint32_t\tunused3;\n-\tuint16_t\tunused4;\n+\t/*\n+\t * If set to '1', then the timestamp from the BD is used. If cleared\n+\t * to 0, then TWE provides the timestamp.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)\n+\t/*\n+\t * If set to '1', this operation will cause a trace capture in each\n+\t * block it passes through.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)\n+\t/*\n+\t * If set to '1', the device will record the time at which the packet\n+\t * was actually transmitted at the TX MAC for 1-step time sync. This\n+\t * bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)\n+\t/*\n+\t * If set to '1', the controller replaces the Outer-tunnel IP checksum\n+\t * field with hardware calculated IP checksum for the IP header of the\n+\t * packet associated with this descriptor. For outer UDP checksum, it\n+\t * will be the following behavior for all cases independent of settings\n+\t * of inner LSO and checksum offload BD flags. If outer UDP checksum\n+\t * is 0, then do not update it. If outer UDP checksum is non zero, then\n+\t * the hardware should compute and update it.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)\n+\t/*\n+\t * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP\n+\t * header will not be modified during LSO operations. If set to one\n+\t * when LSO is '1', then the IPID of the Outer-tunnel IP header will be\n+\t * incremented for each subsequent segment of an LSO operation. The\n+\t * flag is ignored if the LSO packet is a normal (non-tunneled) TCP\n+\t * packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)\n+\t/*\n+\t * If set to '1', When set to 1, KTLS encryption will be enabled for\n+\t * the packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)\n+\tuint8_t\tunused2;\n+\tuint8_t\tkid_or_ts_low;\n+\t#define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)\n+\t/*\n+\t * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit\n+\t * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of\n+\t * the 20-bit KID.\n+\t */\n+\t#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)\n+\t#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1\n+\tuint32_t\tkid_or_ts_high;\n+\t#define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)\n+\t#define TX_BD_LONG_INLINE_UNUSED_SFT 0\n+\t/*\n+\t * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit\n+\t * timestamp. If lflags.crypto_en is 1, the least significant 13 bits\n+\t * of this field contain the upper 13 bits of the 20-bit KID.\n+\t */\n+\t#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)\n+\t#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15\n+\t/*\n+\t * This value selects bits 25:16 of the CFA action to perform on the\n+\t * packet. See the cfa_action field for more information.\n+\t */\n+\tuint16_t\tcfa_action_high;\n+\t#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)\n+\t#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0\n \t/*\n \t * This value selects a CFA action to perform on the packet.\n \t * Set this value to zero if no CFA action is desired.\n@@ -2182,6 +2986,97 @@ struct tx_bd_empty {\n \tuint8_t\tunused_4[8];\n } __rte_packed;\n \n+/* tx_bd_mp_cmd (size:128b/16B) */\n+struct tx_bd_mp_cmd {\n+\t/* Unless otherwise stated, sub-fields of this field are always valid. */\n+\tuint16_t\tflags_type;\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_BD_MP_CMD_TYPE_SFT 0\n+\t/*\n+\t * Indicates that this BD is used to issue a command to one of\n+\t * the mid-path destinations.\n+\t */\n+\t#define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)\n+\t#define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD\n+\t#define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define TX_BD_MP_CMD_FLAGS_SFT 6\n+\t/* */\n+\t#define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)\n+\t#define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6\n+\t/*\n+\t * This value indicates the number of 16B BD locations (slots)\n+\t * consumed in the ring by this mid-path command BD, including the\n+\t * BD header and the command field.\n+\t */\n+\t#define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)\n+\t#define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8\n+\t/*\n+\t * This value defines the length of command field in bytes. The maximum\n+\t * value shall be 496.\n+\t */\n+\tuint16_t\tlen;\n+\t/*\n+\t * The opaque data field is pass through to the completion and can be\n+\t * used for any data that the driver wants to associate with this\n+\t * Tx mid-path command.\n+\t */\n+\tuint32_t\topaque;\n+\tuint64_t\tunused1;\n+} __rte_packed;\n+\n+/* tx_bd_presync_cmd (size:128b/16B) */\n+struct tx_bd_presync_cmd {\n+\t/* Unless otherwise stated, sub-fields of this field are always valid. */\n+\tuint16_t\tflags_type;\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_BD_PRESYNC_CMD_TYPE_SFT 0\n+\t/*\n+\t * Indicates that this BD is used to issue a cryptographic pre-\n+\t * sync command through the fast path and destined for TCE.\n+\t */\n+\t#define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)\n+\t#define TX_BD_PRESYNC_CMD_TYPE_LAST \\\n+\t\tTX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_SFT 6\n+\t/* */\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6\n+\t/*\n+\t * This value indicates the number of 16B BD locations (slots)\n+\t * consumed in the ring by this pre-sync command BD, including the\n+\t * BD header and the command field.\n+\t */\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)\n+\t#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8\n+\t/*\n+\t * This value defines the length of command field in bytes. The maximum\n+\t * value shall be 496.\n+\t */\n+\tuint16_t\tlen;\n+\t/*\n+\t * The opaque data field is pass through to TCE and can be used for\n+\t * debug.\n+\t */\n+\tuint32_t\topaque;\n+\t/*\n+\t * This field is the Crypto Context ID to which the retransmit packet is\n+\t * applied. The KID references the context fields used by the\n+\t * associated kTLS offloaded connection.\n+\t */\n+\tuint32_t\tkid;\n+\t/*\n+\t * The KID value of all-ones is reserved for non-KTLS packets, which\n+\t * only implies that this value must not be used when filling this\n+\t * field for crypto packets.\n+\t */\n+\t#define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)\n+\t#define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0\n+\tuint32_t\tunused_1;\n+} __rte_packed;\n+\n /* rx_prod_pkt_bd (size:128b/16B) */\n struct rx_prod_pkt_bd {\n \t/* This value identifies the type of buffer descriptor. */\n@@ -2310,6 +3205,297 @@ struct rx_prod_agg_bd {\n \tuint64_t\taddress;\n } __rte_packed;\n \n+/* cfa_cmpls_cmp_data_msg (size:128b/16B) */\n+struct cfa_cmpls_cmp_data_msg {\n+\tuint32_t\tmp_client_dma_length_opcode_status_type;\n+\t/*\n+\t * This field represents the Mid-Path client that generated the\n+\t * completion.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0\n+\t/* Mid Path Short Completion with length = 16B. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \\\n+\t\tUINT32_C(0x1e)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \\\n+\t\tCFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT\n+\t/* This value indicates the status for the command. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6\n+\t/* Completed without error. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \\\n+\t\t(UINT32_C(0x0) << 6)\n+\t/* Indicates an unsupported CFA opcode in the command. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \\\n+\t\t(UINT32_C(0x1) << 6)\n+\t/*\n+\t * Indicates a CFA command formatting error. This error can occur on\n+\t * any of the supported CFA commands.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \\\n+\t\t(UINT32_C(0x2) << 6)\n+\t/*\n+\t * Indicates an SVIF-Table scope error. This error can occur on any\n+\t * of the supported CFA commands.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \\\n+\t\t(UINT32_C(0x3) << 6)\n+\t/*\n+\t * Indicates that the table_index is either outside of the\n+\t * table_scope range set by its EM_SIZE or, for EM Insert, it is in\n+\t * the static bucket range. This error can occur on EM Insert\n+\t * commands. It can also occur on Read, Read Clear, Write, and\n+\t * Invalidate commands if the table_type is EM.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \\\n+\t\t(UINT32_C(0x4) << 6)\n+\t/*\n+\t * Cache operation responded with an error. This error can occur on\n+\t * Read, Read Clear, Write, EM Insert, and EM Delete commands.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \\\n+\t\t(UINT32_C(0x5) << 6)\n+\t/*\n+\t * Indicates failure on EM Insert or EM Delete Command. Hash index\n+\t * and hash msb are returned in table_index and hash_msb fields.\n+\t * Dma_length is set to 1 if the bucket is also returned (as dma\n+\t * data).\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \\\n+\t\t(UINT32_C(0x6) << 6)\n+\t/*\n+\t * Indicates no notifications were available on an Event Collection\n+\t * command.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \\\n+\t\t(UINT32_C(0x7) << 6)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \\\n+\t\tCFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10\n+\t/* This is the opcode from the command. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \\\n+\t\tUINT32_C(0xff000)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12\n+\t/*\n+\t * This is read command. From 32 to 128B can be read from a table\n+\t * using this command.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/*\n+\t * This is write command. From 32 to 128B can be written to a table\n+\t * using this command.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/*\n+\t * This is read-clear command. 32B can be read from a table and a 16b\n+\t * mask can be used to clear specific 16b units after the read as an\n+\t * atomic operation.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/*\n+\t * An exact match table insert will be attempted into the table. If\n+\t * there is a free location in the bucket, the payload will be\n+\t * written to the bucket.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/* An exact match table delete will be attempted. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/*\n+\t * The specified table area will be invalidated. If it is needed\n+\t * again, it will be read from the backing store.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t/* Reads notification messages from the Host Notification Queue. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \\\n+\t\t(UINT32_C(0x6) << 12)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \\\n+\t\tCFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT\n+\t/*\n+\t * This field indicates the length of the DMA that accompanies the\n+\t * completion. Specified in units of DWords (32b). Valid values are\n+\t * between 0 and 128. A value of zero indicates that there is no DMA\n+\t * that accompanies the completion.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \\\n+\t\tUINT32_C(0xff00000)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20\n+\t/*\n+\t * This field represents the Mid-Path client that generated the\n+\t * completion.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28\n+\t/* TX configrable flow processing block. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \\\n+\t\t(UINT32_C(0x2) << 28)\n+\t/* RX configrable flow processing block. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \\\n+\t\t(UINT32_C(0x3) << 28)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \\\n+\t\tCFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA\n+\t/*\n+\t * This is a copy of the opaque field from the mid path BD of this\n+\t * command.\n+\t */\n+\tuint32_t\topaque;\n+\tuint16_t\thash_msb_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue. The even passes will\n+\t * write 1. The odd passes will write 0.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1\n+\t/*\n+\t * This is the upper 12b of the hash, returned on Exact Match\n+\t * Insertion/Deletion Commands.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4\n+\t/* This is the table type from the command. */\n+\tuint8_t\ttable_type;\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4\n+\t/* This command acts on the action table of the specified scope. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)\n+\t/* This command acts on the exact match table of the specified scope. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \\\n+\t\tCFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM\n+\tuint8_t\ttable_scope;\n+\t/* This is the table scope from the command. */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0\n+\tuint32_t\ttable_index;\n+\t/*\n+\t * This is the table index from the command (if it exists). However, if\n+\t * an Exact Match Insertion/Deletion command failed, then this is the\n+\t * table index of the calculated static hash bucket.\n+\t */\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)\n+\t#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0\n+} __rte_packed;\n+\n+/* CFA Mid-Path 32B DMA Message */\n+/* cfa_dma32b_data_msg (size:256b/32B) */\n+struct cfa_dma32b_data_msg {\n+\t/* DMA data value. */\n+\tuint32_t\tdta[8];\n+} __rte_packed;\n+\n+/* CFA Mid-Path 64B DMA Message */\n+/* cfa_dma64b_data_msg (size:512b/64B) */\n+struct cfa_dma64b_data_msg {\n+\t/* DMA data value. */\n+\tuint32_t\tdta[16];\n+} __rte_packed;\n+\n+/* CFA Mid-Path 96B DMA Message */\n+/* cfa_dma96b_data_msg (size:768b/96B) */\n+struct cfa_dma96b_data_msg {\n+\t/* DMA data value. */\n+\tuint32_t\tdta[24];\n+} __rte_packed;\n+\n+/* CFA Mid-Path 128B DMA Message */\n+/* cfa_dma128b_data_msg (size:1024b/128B) */\n+struct cfa_dma128b_data_msg {\n+\t/* DMA data value. */\n+\tuint32_t\tdta[32];\n+} __rte_packed;\n+\n+/* ce_cmpls_cmp_data_msg (size:128b/16B) */\n+struct ce_cmpls_cmp_data_msg {\n+\tuint16_t\tstatus_subtype_type;\n+\t/*\n+\t * This field indicates the exact type of the completion. By\n+\t * convention, the LSB identifies the length of the record in 16B\n+\t * units. Even values indicate 16B records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)\n+\t#define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0\n+\t/* Completion of a Mid Path Command. Length = 16B */\n+\t#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)\n+\t#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \\\n+\t\tCE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT\n+\t/*\n+\t * This value indicates the CE sub-type operation that is being\n+\t * completed.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6\n+\t/* Completion Response for a Solicited Command. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)\n+\t/* Error Completion (Unsolicited). */\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)\n+\t/* Re-Sync Completion (Unsolicited) */\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \\\n+\t\tCE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC\n+\t/* This value indicates the status for the command. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10\n+\t/* Completed without error. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \\\n+\t\t(UINT32_C(0x0) << 10)\n+\t/* CFCK load error. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \\\n+\t\t(UINT32_C(0x1) << 10)\n+\t/* FID check error. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \\\n+\t\t(UINT32_C(0x2) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \\\n+\t\tCE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR\n+\tuint8_t\tunused0;\n+\tuint8_t\tmp_clients;\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0\n+\t/*\n+\t * This field represents the Mid-Path client that generated the\n+\t * completion.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4\n+\t/* TX crypto engine block. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)\n+\t/* RX crypto engine block. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \\\n+\t\tCE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE\n+\t/*\n+\t * This is a copy of the opaque field from the mid path BD of this\n+\t * command.\n+\t */\n+\tuint32_t\topaque;\n+\t/* */\n+\tuint32_t\tkid_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes will\n+\t * write 1. The odd passes will write 0.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated kTLS offloaded connection.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)\n+\t#define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1\n+\tuint32_t\tunused2;\n+} __rte_packed;\n+\n /* cmpl_base (size:128b/16B) */\n struct cmpl_base {\n \tuint16_t\ttype;\n@@ -5423,27 +6609,32 @@ struct rx_tpa_v2_end_cmpl {\n \t * records. Odd values indicate 32B\n \t * records.\n \t */\n-\t#define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)\n-\t#define RX_TPA_V2_END_CMPL_TYPE_SFT 0\n+\t#define RX_TPA_V2_END_CMPL_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define RX_TPA_V2_END_CMPL_TYPE_SFT 0\n \t/*\n \t * RX L2 TPA End Completion:\n \t * Completion at the end of a TPA operation.\n \t * Length = 32B\n \t */\n-\t#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)\n+\t#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \\\n+\t\tUINT32_C(0x15)\n \t#define RX_TPA_V2_END_CMPL_TYPE_LAST \\\n \t\tRX_TPA_V2_END_CMPL_TYPE_RX_TPA_END\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_SFT 6\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_MASK \\\n+\t\tUINT32_C(0xffc0)\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_SFT 6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n \t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_ERROR \\\n+\t\tUINT32_C(0x40)\n \t/* This field indicates how the packet was placed in the buffer. */\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \\\n+\t\tUINT32_C(0x380)\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7\n \t/*\n \t * Jumbo:\n \t * TPA Packet was placed using jumbo algorithm. This means\n@@ -5482,11 +6673,30 @@ struct rx_tpa_v2_end_cmpl {\n \t */\n \t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \\\n \t\t(UINT32_C(0x6) << 7)\n+\t/*\n+\t * IOC/Header-Data Separation:\n+\t * Packet will be placed using In-Order Completion/HDS where\n+\t * the header is in the first packet buffer. Payload of each\n+\t * packet will be placed such that each packet starts at the\n+\t * beginning of an aggregation buffer.\n+\t */\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \\\n+\t\t(UINT32_C(0x7) << 7)\n \t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \\\n-\t\tRX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS\n-\t/* unused is 2 b */\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10\n+\t\tRX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS\n+\t/* unused is 1 b */\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit is '1' if metadata has been added to the end of the\n+\t * packet in host memory. Metadata starts at the first 32B boundary\n+\t * after the end of the packet for regular and jumbo placement.\n+\t * It starts at the first 32B boundary after the end of the header\n+\t * for HDS placement. The length of the metadata is indicated in the\n+\t * metadata itself.\n+\t */\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \\\n+\t\tUINT32_C(0x800)\n \t/*\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n@@ -5496,8 +6706,9 @@ struct rx_tpa_v2_end_cmpl {\n \t * field is valid and contains the TCP checksum.\n \t * This also indicates that the payload_offset field is valid.\n \t */\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)\n-\t#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \\\n+\t\tUINT32_C(0xf000)\n+\t#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12\n \t/*\n \t * This value is zero for TPA End completions.\n \t * There is no data in the buffer that corresponds to the opaque\n@@ -6047,6 +7258,12 @@ struct hwrm_async_event_cmpl {\n \t/* Master function selection event */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \\\n \t\tUINT32_C(0x9)\n+\t/*\n+\t * An event signifying that a ring has been disabled by\n+\t * hw due to error.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \\\n+\t\tUINT32_C(0xa)\n \t/* Function driver unloaded */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \\\n \t\tUINT32_C(0x10)\n@@ -6156,6 +7373,9 @@ struct hwrm_async_event_cmpl {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \\\n \t\tUINT32_C(0x41)\n+\t/* Maximum Registrable event id. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \\\n+\t\tUINT32_C(0x42)\n \t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n@@ -6792,7 +8012,7 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t\tUINT32_C(0x8)\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \\\n \t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY\n-\t/* Event specific data */\n+\t/* Event specific data. The data is for internal debug use only. */\n \tuint32_t\tevent_data2;\n \tuint8_t\topaque_v;\n \t/*\n@@ -6936,6 +8156,71 @@ struct hwrm_async_event_cmpl_error_recovery {\n \t\tUINT32_C(0x2)\n } __rte_packed;\n \n+/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */\n+struct hwrm_async_event_cmpl_ring_monitor_msg {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Ring Monitor Message. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \\\n+\t\tUINT32_C(0xa)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\t/* Type of Ring disabled. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \\\n+\t\t0\n+\t/* tx ring disabled. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx ring disabled. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \\\n+\t\tUINT32_C(0x1)\n+\t/* cmpl ring disabled. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/*\n+\t * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl\n+\t * then this field will indicate the ring id.\n+\t */\n+\tuint32_t\tevent_data1;\n+} __rte_packed;\n+\n /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */\n struct hwrm_async_event_cmpl_func_drvr_unload {\n \tuint16_t\ttype;\n@@ -8396,6 +9681,388 @@ struct hwrm_async_event_cmpl_hwrm_error {\n \t\tUINT32_C(0x1)\n } __rte_packed;\n \n+/* metadata_base_msg (size:64b/8B) */\n+struct metadata_base_msg {\n+\tuint16_t\tmd_type_link;\n+\t/* This field classifies the data present in the meta-data. */\n+\t#define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)\n+\t#define METADATA_BASE_MSG_MD_TYPE_SFT 0\n+\t/* Meta data fiels are not valid */\n+\t#define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)\n+\t/*\n+\t * This setting is used when packets are coming in-order. Depending on\n+\t * the state of the receive context, the meta-data will carry different\n+\t * information.\n+\t */\n+\t#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)\n+\t/*\n+\t * With this setting HW passes the TCP sequence number of the TLS\n+\t * record that it is requesting a resync on in the meta data.\n+\t */\n+\t#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)\n+\t#define METADATA_BASE_MSG_MD_TYPE_LAST \\\n+\t\tMETADATA_BASE_MSG_MD_TYPE_TLS_RESYNC\n+\t/*\n+\t * This field indicates where the next metadata block starts. It is\n+\t * counted in 16B units. A value of zero indicates that there is no\n+\t * metadata.\n+\t */\n+\t#define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)\n+\t#define METADATA_BASE_MSG_LINK_SFT 5\n+\tuint16_t\tunused0;\n+\tuint32_t\tunused1;\n+} __rte_packed;\n+\n+/* tls_metadata_base_msg (size:64b/8B) */\n+struct tls_metadata_base_msg {\n+\tuint32_t\tmd_type_link_flags_kid_lo;\n+\t/* This field classifies the data present in the meta-data. */\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \\\n+\t\tUINT32_C(0x1f)\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0\n+\t/*\n+\t * This setting is used when packets are coming in-order. Depending on\n+\t * the state of the receive context, the meta-data will carry different\n+\t * information.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * With this setting HW passes the TCP sequence number of the TLS\n+\t * record that it is requesting a resync on in the meta data.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \\\n+\t\tUINT32_C(0x2)\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \\\n+\t\tTLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC\n+\t/*\n+\t * This field indicates where the next metadata block starts. It is\n+\t * counted in 16B units. A value of zero indicates that there is no\n+\t * metadata.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_LINK_MASK \\\n+\t\tUINT32_C(0x1e0)\n+\t#define TLS_METADATA_BASE_MSG_LINK_SFT 5\n+\t/* These are flags present in the metadata. */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_MASK \\\n+\t\tUINT32_C(0x1fffe00)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_SFT 9\n+\t/*\n+\t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n+\t * the packet is passed on as it came in on the wire.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This field indicates the state of the ghash field passed in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \\\n+\t\tUINT32_C(0xc00)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10\n+\t/*\n+\t * This enumeration states that the ghash is not valid in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \\\n+\t\t(UINT32_C(0x0) << 10)\n+\t/*\n+\t * This enumeration indicates that this pkt contains the record's\n+\t * tag and this pkt was received ooo, the partial_ghash field\n+\t * contains the ghash.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \\\n+\t\t(UINT32_C(0x1) << 10)\n+\t/*\n+\t * This enumeration indicates that the current record's tag wasn't\n+\t * seen and the chip is moving on to the next record, the\n+\t * partial_ghash field contains the ghash.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \\\n+\t\t(UINT32_C(0x2) << 10)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \\\n+\t\tTLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC\n+\t/* This field indicates the status of tag authentication. */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n+\t\tUINT32_C(0x3000)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t/*\n+\t * This enumeration is set when there is no tags present in the\n+\t * packet.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/*\n+\t * This enumeration states that there is at least one tag in the\n+\t * packet and every tag is valid.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/*\n+\t * This enumeration states that there is atleast one tag in the\n+\t * packet and atleast one of the tag is invalid. The entire packet\n+\t * is sent decrypted to the host.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \\\n+\t\tTLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE\n+\t/*\n+\t * A value of 1 indicates that this packet contains a record that\n+\t * starts in the packet and extends beyond the packet.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This value indicates the lower 7-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_KID_LO_MASK \\\n+\t\tUINT32_C(0xfe000000)\n+\t#define TLS_METADATA_BASE_MSG_KID_LO_SFT 25\n+\tuint16_t\tkid_hi;\n+\t/*\n+\t * This value indicates the upper 13-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)\n+\t#define TLS_METADATA_BASE_MSG_KID_HI_SFT 0\n+\tuint16_t\tunused0;\n+} __rte_packed;\n+\n+/* tls_metadata_insync_msg (size:192b/24B) */\n+struct tls_metadata_insync_msg {\n+\tuint32_t\tmd_type_link_flags_kid_lo;\n+\t/* This field classifies the data present in the meta-data. */\n+\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \\\n+\t\tUINT32_C(0x1f)\n+\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0\n+\t/*\n+\t * This setting is used when packets are coming in-order. Depending on\n+\t * the state of the receive context, the meta-data will carry different\n+\t * information.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \\\n+\t\tUINT32_C(0x1)\n+\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \\\n+\t\tTLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC\n+\t/*\n+\t * This field indicates where the next metadata block starts. It is\n+\t * counted in 16B units. A value of zero indicates that there is no\n+\t * metadata.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_LINK_MASK \\\n+\t\tUINT32_C(0x1e0)\n+\t#define TLS_METADATA_INSYNC_MSG_LINK_SFT 5\n+\t/* These are flags present in the metadata. */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \\\n+\t\tUINT32_C(0x1fffe00)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9\n+\t/*\n+\t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n+\t * the packet is passed on as it came in on the wire.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This field indicates the state of the ghash field passed in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \\\n+\t\tUINT32_C(0xc00)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10\n+\t/*\n+\t * This enumeration states that the ghash is not valid in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \\\n+\t\t(UINT32_C(0x0) << 10)\n+\t/*\n+\t * This enumeration indicates that this pkt contains the record's\n+\t * tag and this pkt was received ooo, the partial_ghash field\n+\t * contains the ghash.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \\\n+\t\t(UINT32_C(0x1) << 10)\n+\t/*\n+\t * This enumeration indicates that the current record's tag wasn't\n+\t * seen and the chip is moving on to the next record, the\n+\t * partial_ghash field contains the ghash.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \\\n+\t\t(UINT32_C(0x2) << 10)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \\\n+\t\tTLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC\n+\t/* This field indicates the status of tag authentication. */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n+\t\tUINT32_C(0x3000)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t/*\n+\t * This enumeration is set when there is no tags present in the\n+\t * packet.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/*\n+\t * This enumeration states that there is at least one tag in the\n+\t * packet and every tag is valid.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/*\n+\t * This enumeration states that there is atleast one tag in the\n+\t * packet and atleast one of the tag is invalid. The entire packet\n+\t * is sent decrypted to the host.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \\\n+\t\tTLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE\n+\t/*\n+\t * A value of 1 indicates that this packet contains a record that\n+\t * starts in the packet and extends beyond the packet.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This value indicates the lower 7-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \\\n+\t\tUINT32_C(0xfe000000)\n+\t#define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25\n+\tuint16_t\tkid_hi;\n+\t/*\n+\t * This value indicates the upper 13-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)\n+\t#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0\n+\t/*\n+\t * This field is only valid when md_type is set to tls_insync. This field\n+\t * indicates the offset within the current TCP packet where the TLS header\n+\t * starts. If there are multiple TLS headers in the packet, this provides\n+\t * the offset of the last TLS header.\n+\t *\n+\t * The field is calculated by subtracting TCP sequence number of the first\n+\t * byte of the TCP payload of the packet from the TCP sequence number of\n+\t * the last TLS header in the packet.\n+\t */\n+\tuint16_t\ttls_header_offset;\n+\t/*\n+\t * This is the sequence Number of the record that was processed by the HW.\n+\t * If there are multiple records in a packet, this would be the sequence\n+\t * number of the last record.\n+\t */\n+\tuint64_t\trecord_seq_num;\n+\t/*\n+\t * This field contains cumulative partial GHASH value of all the packets\n+\t * decrypted by the HW associated with a TLS record. This field is valid\n+\t * on when packets belonging to have arrived out-of-order and HW could\n+\t * not decrypt every packet and authenticate the record. Partial GHASH is\n+\t * only sent out with packet having the TAG field.\n+\t */\n+\tuint64_t\tpartial_ghash;\n+} __rte_packed;\n+\n+/* tls_metadata_resync_msg (size:256b/32B) */\n+struct tls_metadata_resync_msg {\n+\tuint32_t\tmd_type_link_flags_kid_lo;\n+\t/* This field classifies the data present in the meta-data. */\n+\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \\\n+\t\tUINT32_C(0x1f)\n+\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0\n+\t/*\n+\t * With this setting HW passes the TCP sequence number of the TLS\n+\t * record that it is requesting a resync on in the meta data.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \\\n+\t\tUINT32_C(0x2)\n+\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \\\n+\t\tTLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC\n+\t/*\n+\t * This field indicates where the next metadata block starts. It is\n+\t * counted in 16B units. A value of zero indicates that there is no\n+\t * metadata.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_LINK_MASK \\\n+\t\tUINT32_C(0x1e0)\n+\t#define TLS_METADATA_RESYNC_MSG_LINK_SFT 5\n+\t/* These are flags present in the metadata. */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \\\n+\t\tUINT32_C(0x1fffe00)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9\n+\t/*\n+\t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n+\t * the packet is passed on as it came in on the wire.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This field indicates the state of the ghash field passed in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \\\n+\t\tUINT32_C(0xc00)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10\n+\t/*\n+\t * This enumeration states that the ghash is not valid in the\n+\t * meta-data.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \\\n+\t\t(UINT32_C(0x0) << 10)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \\\n+\t\tTLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID\n+\t/* This field indicates the status of tag authentication. */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n+\t\tUINT32_C(0x3000)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t/*\n+\t * This enumeration is set when there is no tags present in the\n+\t * packet.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \\\n+\t\tTLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE\n+\t/*\n+\t * A value of 1 indicates that this packet contains a record that\n+\t * starts in the packet and extends beyond the packet.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This value indicates the lower 7-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \\\n+\t\tUINT32_C(0xfe000000)\n+\t#define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25\n+\tuint16_t\tkid_hi;\n+\t/*\n+\t * This value indicates the upper 13-bit of the Crypto Key ID\n+\t * associated with this operation.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)\n+\t#define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0\n+\t/* This field is unused in this context. */\n+\tuint16_t\tmetadata_0;\n+\t/*\n+\t * This field indicates the TCP sequence number of the TLS record that HW\n+\t * is requesting a resync on from the Driver. HW will keep a count of the\n+\t * TLS records it found after this record (delta_records). Driver will\n+\t * provide the TLS Record Sequence Number associated with the record. HW\n+\t * will add the delta_records to the Record Sequence Number provided by\n+\t * the driver and get back on sync.\n+\t */\n+\tuint32_t\tresync_record_tcp_seq_num;\n+\tuint32_t\tunused0;\n+\t/* This field is unused in this context. */\n+\tuint64_t\tmetadata_2;\n+\t/* This field is unused in this context. */\n+\tuint64_t\tmetadata_3;\n+} __rte_packed;\n+\n /*******************\n * hwrm_func_reset *\n *******************/\n@@ -9466,7 +11133,38 @@ struct hwrm_func_qcaps_output {\n \t\tUINT32_C(0x80)\n \t/* The maximum number of SCHQs supported by this device. */\n \tuint8_t\tmax_schqs;\n-\tuint8_t\tunused_1[2];\n+\tuint8_t\tmpc_chnls_cap;\n+\t/*\n+\t * When this bit is '1', it indicates that HW and firmware\n+\t * supports the use of a MPC channel with destination set\n+\t * to the TX crypto engine block.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that HW and firmware\n+\t * supports the use of a MPC channel with destination set\n+\t * to the RX crypto engine block.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that HW and firmware\n+\t * supports the use of a MPC channel with destination set\n+\t * to the TX configurable flow processing block.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates that HW and firmware\n+\t * supports the use of a MPC channel with destination set\n+\t * to the RX configurable flow processing block.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates that HW and firmware\n+\t * supports the use of a MPC channel with destination set\n+\t * to the primate processor block.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)\n+\tuint8_t\tunused_1;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -9643,6 +11341,12 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \\\n \t\tUINT32_C(0x400)\n+\t/*\n+\t * If set to 1, then the firmware will notify driver using async\n+\t * event when a ring is disabled due to a Hardware error.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \\\n+\t\tUINT32_C(0x800)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -9959,7 +11663,40 @@ struct hwrm_func_qcfg_output {\n \t#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0\n \t/* This field specifies whether svif is valid or not */\n \t#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)\n-\tuint8_t\tunused_2[7];\n+\tuint8_t\tmpc_chnls;\n+\t/*\n+\t * When this bit is '1', it indicates that a MPC channel with\n+\t * destination set to the TX crypto engine block is enabled.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that a MPC channel with\n+\t * destination set to the RX crypto engine block is enabled.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that a MPC channel with\n+\t * destination set to the TX configurable flow processing block is\n+\t * enabled.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates that a MPC channel with\n+\t * destination set to the RX configurable flow processing block is\n+\t * enabled.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates that a MPC channel with\n+\t * destination set to the primate processor block is enabled.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \\\n+\t\tUINT32_C(0x10)\n+\tuint8_t\tunused_2[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -10376,6 +12113,12 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \\\n \t\tUINT32_C(0x1000000)\n+\t/*\n+\t * This bit must be '1' for the mpc_chnls field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \\\n+\t\tUINT32_C(0x2000000)\n \t/*\n \t * The maximum transmission unit of the function.\n \t * The HWRM should make sure that the mtu of\n@@ -10642,7 +12385,74 @@ struct hwrm_func_cfg_input {\n \tuint16_t\tnum_mcast_filters;\n \t/* Used by a PF driver to associate a SCHQ with a VF. */\n \tuint16_t\tschq_id;\n-\tuint8_t\tunused_0[6];\n+\tuint16_t\tmpc_chnls;\n+\t/*\n+\t * When this bit is '1', the caller requests to enable a MPC\n+\t * channel with destination to the TX crypto engine block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the caller requests to disable a MPC\n+\t * channel with destination to the TX crypto engine block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the caller requests to enable a MPC\n+\t * channel with destination to the RX crypto engine block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the caller requests to disable a MPC\n+\t * channel with destination to the RX crypto engine block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the caller requests to enable a MPC\n+\t * channel with destination to the TX configurable flow processing\n+\t * block. When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the caller requests to disable a MPC\n+\t * channel with destination to the TX configurable flow processing\n+\t * block block. When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', the caller requests to enable a MPC\n+\t * channel with destination to the RX configurable flow processing\n+\t * block. When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', the caller requests to disable a MPC\n+\t * channel with destination to the RX configurable flow processing\n+\t * block block. When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', the caller requests to enable a MPC\n+\t * channel with destination to the primate processor block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', the caller requests to disable a MPC\n+\t * channel with destination to the primate processor block.\n+\t * When this bit is ‘0’, this flag has no effect.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \\\n+\t\tUINT32_C(0x200)\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_func_cfg_output (size:128b/16B) */\n@@ -10889,7 +12699,7 @@ struct hwrm_func_qstats_ext_input {\n \tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_func_qstats_ext_output (size:1472b/184B) */\n+/* hwrm_func_qstats_ext_output (size:1536b/192B) */\n struct hwrm_func_qstats_ext_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -10941,6 +12751,8 @@ struct hwrm_func_qstats_ext_output {\n \tuint64_t\trx_tpa_bytes;\n \t/* Number of TPA errors */\n \tuint64_t\trx_tpa_errors;\n+\t/* Number of TPA errors */\n+\tuint64_t\trx_tpa_events;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -11842,6 +13654,125 @@ struct hwrm_func_resource_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/*****************************\n+ * hwrm_func_vf_resource_cfg *\n+ *****************************/\n+\n+\n+/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */\n+struct hwrm_func_vf_resource_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* VF ID that is being configured by PF */\n+\tuint16_t\tvf_id;\n+\t/* Maximum guaranteed number of MSI-X vectors for the function */\n+\tuint16_t\tmax_msix;\n+\t/* Minimum guaranteed number of RSS/COS contexts */\n+\tuint16_t\tmin_rsscos_ctx;\n+\t/* Maximum non-guaranteed number of RSS/COS contexts */\n+\tuint16_t\tmax_rsscos_ctx;\n+\t/* Minimum guaranteed number of completion rings */\n+\tuint16_t\tmin_cmpl_rings;\n+\t/* Maximum non-guaranteed number of completion rings */\n+\tuint16_t\tmax_cmpl_rings;\n+\t/* Minimum guaranteed number of transmit rings */\n+\tuint16_t\tmin_tx_rings;\n+\t/* Maximum non-guaranteed number of transmit rings */\n+\tuint16_t\tmax_tx_rings;\n+\t/* Minimum guaranteed number of receive rings */\n+\tuint16_t\tmin_rx_rings;\n+\t/* Maximum non-guaranteed number of receive rings */\n+\tuint16_t\tmax_rx_rings;\n+\t/* Minimum guaranteed number of L2 contexts */\n+\tuint16_t\tmin_l2_ctxs;\n+\t/* Maximum non-guaranteed number of L2 contexts */\n+\tuint16_t\tmax_l2_ctxs;\n+\t/* Minimum guaranteed number of VNICs */\n+\tuint16_t\tmin_vnics;\n+\t/* Maximum non-guaranteed number of VNICs */\n+\tuint16_t\tmax_vnics;\n+\t/* Minimum guaranteed number of statistic contexts */\n+\tuint16_t\tmin_stat_ctx;\n+\t/* Maximum non-guaranteed number of statistic contexts */\n+\tuint16_t\tmax_stat_ctx;\n+\t/* Minimum guaranteed number of ring groups */\n+\tuint16_t\tmin_hw_ring_grps;\n+\t/* Maximum non-guaranteed number of ring groups */\n+\tuint16_t\tmax_hw_ring_grps;\n+\tuint16_t\tflags;\n+\t/*\n+\t * If this bit is set, all minimum resources requested should be\n+\t * reserved if minimum >= 1, otherwise return error. In case of\n+\t * error, keep all existing reservations before the call.\n+\t */\n+\t#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[2];\n+} __rte_packed;\n+\n+/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */\n+struct hwrm_func_vf_resource_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Reserved number of RSS/COS contexts */\n+\tuint16_t\treserved_rsscos_ctx;\n+\t/* Reserved number of completion rings */\n+\tuint16_t\treserved_cmpl_rings;\n+\t/* Reserved number of transmit rings */\n+\tuint16_t\treserved_tx_rings;\n+\t/* Reserved number of receive rings */\n+\tuint16_t\treserved_rx_rings;\n+\t/* Reserved number of L2 contexts */\n+\tuint16_t\treserved_l2_ctxs;\n+\t/* Reserved number of VNICs */\n+\tuint16_t\treserved_vnics;\n+\t/* Reserved number of statistic contexts */\n+\tuint16_t\treserved_stat_ctx;\n+\t/* Reserved number of ring groups */\n+\tuint16_t\treserved_hw_ring_grps;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /*********************************\n * hwrm_func_backing_store_qcaps *\n *********************************/\n@@ -15343,10 +17274,11 @@ struct hwrm_port_phy_cfg_input {\n \t * When set to 1, then the HWRM shall enable FEC autonegotitation\n \t * on this port if supported. When enabled, at least one of the\n \t * FEC modes must be advertised by enabling the fec_clause_74_enable,\n-\t * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable\n-\t * flag. If none of the FEC mode is currently enabled, the HWRM\n-\t * shall choose a default advertisement setting.\n-\t * The default advertisement setting can be queried by calling\n+\t * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,\n+\t * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none\n+\t * of the FEC mode is currently enabled, the HWRM shall choose\n+\t * a default advertisement setting.\n+\t * The default advertisment setting can be queried by calling\n \t * hwrm_port_phy_qcfg. Note that the link speed must be\n \t * in autonegotiation mode for FEC autonegotiation to take effect.\n \t * When set to 0, then this flag shall be ignored.\n@@ -15357,7 +17289,8 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x100)\n \t/*\n \t * When set to 1, then the HWRM shall disable FEC autonegotiation\n-\t * on this port if supported.\n+\t * on this port and use forced FEC mode. In forced FEC mode, one\n+\t * or more FEC forced settings under the same clause can be set.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15385,22 +17318,26 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \\\n \t\tUINT32_C(0x800)\n \t/*\n-\t * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported, by advertising FEC CLAUSE 91 if\n-\t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * When set to 1, then the HWRM shall enable FEC CLAUSE 91\n+\t * (Reed Solomon RS(528,514) for NRZ) on this port if supported,\n+\t * by advertising FEC RS(528,514) if FEC autonegotiation is enabled\n+\t * or force enabled otherwise. In forced FEC mode, this flag\n+\t * will only take effect if the speed is NRZ. Additional\n+\t * RS544 or RS272 flags (also under clause 91) may be set for PAM4\n+\t * in forced FEC mode.\n \t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * If FEC RS(528,514) is not supported, then the HWRM shall ignore\n+\t * this flag.\n \t */\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \\\n \t\tUINT32_C(0x1000)\n \t/*\n-\t * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported, by not advertising FEC CLAUSE 91 if\n-\t * FEC autonegotiation is enabled or force disabled otherwise.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * When set to 1, then the HWRM shall disable FEC CLAUSE 91\n+\t * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by\n+\t * not advertising RS(528,514) if FEC autonegotiation is enabled or\n+\t * force disabled otherwise. When set to 0, then this flag shall be\n+\t * ignored. If FEC RS(528,514) is not supported, then the HWRM\n+\t * shall ignore this flag.\n \t */\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \\\n \t\tUINT32_C(0x2000)\n@@ -15428,6 +17365,9 @@ struct hwrm_port_phy_cfg_input {\n \t * When set to 1, then the HWRM shall enable FEC RS544_1XN\n \t * on this port if supported, by advertising FEC RS544_1XN if\n \t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * In forced mode, this flag will only take effect if the speed is\n+\t * PAM4. If this flag and fec_rs544_ieee_enable are set, the\n+\t * HWRM shall choose one of the RS544 modes.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC RS544_1XN is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15445,25 +17385,76 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \\\n \t\tUINT32_C(0x10000)\n \t/*\n-\t * When set to 1, then the HWRM shall enable FEC RS544_2XN\n-\t * on this port if supported, by advertising FEC RS544_2XN if\n+\t * When set to 1, then the HWRM shall enable FEC RS(544,514)\n+\t * on this port if supported, by advertising FEC RS(544,514) if\n \t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * In forced mode, this flag will only take effect if the speed is\n+\t * PAM4. If this flag and fec_rs544_1xn_enable are set, the\n+\t * HWRM shall choose one of the RS544 modes.\n \t * When set to 0, then this flag shall be ignored.\n-\t * If FEC RS544_2XN is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * If FEC RS(544,514) is not supported, then the HWRM shall ignore\n+\t * this flag.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \\\n \t\tUINT32_C(0x20000)\n \t/*\n-\t * When set to 1, then the HWRM shall disable FEC RS544_2XN\n-\t * on this port if supported, by not advertising FEC RS544_2XN if\n+\t * When set to 1, then the HWRM shall disable FEC RS(544,514)\n+\t * on this port if supported, by not advertising FEC RS(544,514) if\n \t * FEC autonegotiation is enabled or force disabled otherwise.\n \t * When set to 0, then this flag shall be ignored.\n-\t * If FEC RS544_2XN is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * If FEC RS(544,514) is not supported, then the HWRM shall ignore\n+\t * this flag.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \\\n \t\tUINT32_C(0x40000)\n+\t/*\n+\t * When set to 1, then the HWRM shall enable FEC RS272_1XN\n+\t * on this port if supported, by advertising FEC RS272_1XN if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * In forced mode, this flag will only take effect if the speed is\n+\t * PAM4. If this flag and fec_rs272_ieee_enable are set, the\n+\t * HWRM shall choose one of the RS272 modes. Note that RS272\n+\t * and RS544 modes cannot be set at the same time in forced FEC mode.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS272_1XN is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \\\n+\t\tUINT32_C(0x80000)\n+\t/*\n+\t * When set to 1, then the HWRM shall disable FEC RS272_1XN\n+\t * on this port if supported, by not advertising FEC RS272_1XN if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS272_1XN is not supported, then the HWRM shall ignore\n+\t * this flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \\\n+\t\tUINT32_C(0x100000)\n+\t/*\n+\t * When set to 1, then the HWRM shall enable FEC RS(272,257)\n+\t * on this port if supported, by advertising FEC RS(272,257) if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * In forced mode, this flag will only take effect if the speed is\n+\t * PAM4. If this flag and fec_rs272_1xn_enable are set, the\n+\t * HWRM shall choose one of the RS272 modes. Note that RS272\n+\t * and RS544 modes cannot be set at the same time in forced FEC mode.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS(272,257) is not supported, then the HWRM shall ignore\n+\t * this flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \\\n+\t\tUINT32_C(0x200000)\n+\t/*\n+\t * When set to 1, then the HWRM shall disable FEC RS(272,257)\n+\t * on this port if supported, by not advertising FEC RS(272,257) if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS(272,257) is not supported, then the HWRM shall ignore\n+\t * this flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \\\n+\t\tUINT32_C(0x400000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the auto_mode field to be\n@@ -15939,7 +17930,7 @@ struct hwrm_port_phy_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_port_phy_qcfg_output (size:832b/104B) */\n+/* hwrm_port_phy_qcfg_output (size:768b/96B) */\n struct hwrm_port_phy_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -15959,20 +17950,52 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \\\n \t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK\n+\tuint8_t\tactive_fec_signal_mode;\n \t/*\n \t * This value indicates the current link signaling mode of the\n \t * connection.\n \t */\n-\tuint8_t\tlink_signal_mode;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0\n \t/* NRZ signaling */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_NRZ UINT32_C(0x0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \\\n+\t\tUINT32_C(0x0)\n \t/* PAM4 signaling */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4 UINT32_C(0x1)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL_MODE_PAM4\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4\n+\t/* This value indicates the current active FEC mode. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4\n+\t/* No active FEC */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* FEC RS544_1XN active, autonegoatiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* FEC RS(544,528) active, autonegoatiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* FEC RS272_1XN active, autonegotiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t/* FEC RS(272,257) active, autonegoatiated or forced. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \\\n+\t\t(UINT32_C(0x6) << 4)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE\n \t/*\n \t * This value indicates the current link speed of the connection.\n-\t * The link_signal_mode field indicates if the link is using\n+\t * The signal_mode field indicates if the link is using\n \t * NRZ or PAM4 signaling.\n \t */\n \tuint16_t\tlink_speed;\n@@ -16739,16 +18762,18 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.\n-\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for\n+\t * NRZ) is supported on this port.\n+\t * When set to 0, then FEC RS(528,418) is not supported on this port.\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this\n-\t * port. This means that FEC CLAUSE 91 is either advertised if\n-\t * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.\n-\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for\n+\t * NRZ) is enabled on this port. This means that FEC RS(528,514) is\n+\t * either advertised if FEC autonegotiation is enabled or FEC\n+\t * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)\n+\t * is disabled if supported.\n \t * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \\\n@@ -16769,59 +18794,49 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * When set to 1, then FEC RS544_2XN is supported on this port.\n-\t * When set to 0, then FEC RS544_2XN is not supported on this port.\n+\t * When set to 1, then FEC RS(544,514) is supported on this port.\n+\t * When set to 0, then FEC RS(544,514) is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \\\n \t\tUINT32_C(0x200)\n \t/*\n-\t * When set to 1, then RS544_2XN is enabled on this\n-\t * port. This means that FEC RS544_2XN is either advertised if\n-\t * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.\n-\t * When set to 0, then FEC RS544_2XN is disabled if supported.\n-\t * This flag should be ignored if FEC RS544_2XN is not supported on this port.\n+\t * When set to 1, then RS(544,514) is enabled on this\n+\t * port. This means that FEC RS(544,514) is either advertised if\n+\t * FEC autonegotiation is enabled or FEC RS(544,514) is force\n+\t * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.\n+\t * This flag should be ignored if FEC RS(544,514) is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \\\n \t\tUINT32_C(0x400)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this\n-\t * port, either successfully autonegoatiated or forced.\n-\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.\n-\t * This flag is only valid when link is up on this port.\n-\t * At most only one active FEC flags (fec_clause74_active,\n-\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t * When set to 1, then FEC RS272_1XN is supported on this port.\n+\t * When set to 0, then FEC RS272_1XN is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \\\n \t\tUINT32_C(0x800)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this\n-\t * port, either successfully autonegoatiated or forced.\n-\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.\n-\t * This flag is only valid when link is up on this port.\n-\t * At most only one active FEC flags (fec_clause74_active,\n-\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t * When set to 1, then RS272_1XN is enabled on this\n+\t * port. This means that FEC RS272_1XN is either advertised if\n+\t * FEC autonegotiation is enabled or FEC RS272_1XN is force\n+\t * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.\n+\t * This flag should be ignored if FEC RS272_1XN is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \\\n \t\tUINT32_C(0x1000)\n \t/*\n-\t * When set to 1, then FEC RS544_1XN is active on this\n-\t * port, either successfully autonegoatiated or forced.\n-\t * When set to 0, then FEC RS544_1XN is not active.\n-\t * This flag is only valid when link is up on this port.\n-\t * At most only one active FEC flags (fec_clause74_active,\n-\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t * When set to 1, then FEC RS(272,514) is supported on this port.\n+\t * When set to 0, then FEC RS(272,514) is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \\\n \t\tUINT32_C(0x2000)\n \t/*\n-\t * When set to 1, then FEC RS544_2XN is active on this\n-\t * port, either successfully autonegoatiated or forced.\n-\t * When set to 0, then FEC RS544_2XN is not active.\n-\t * This flag is only valid when link is up on this port.\n-\t * At most only one active FEC flags (fec_clause74_active,\n-\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t * When set to 1, then RS(272,257) is enabled on this\n+\t * port. This means that FEC RS(272,257) is either advertised if\n+\t * FEC autonegotiation is enabled or FEC RS(272,257) is force\n+\t * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.\n+\t * This flag should be ignored if FEC RS(272,257) is not supported on this port.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \\\n \t\tUINT32_C(0x4000)\n \t/*\n \t * This value is indicates the duplex of the current\n@@ -16900,7 +18915,7 @@ struct hwrm_port_phy_qcfg_output {\n \t * The advertised PAM4 speeds for the port by the link partner.\n \t * Each advertised speed will be set to '1'.\n \t */\n-\tuint16_t\tlink_partner_pam4_adv_speeds;\n+\tuint8_t\tlink_partner_pam4_adv_speeds;\n \t/* 50Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \\\n \t\tUINT32_C(0x1)\n@@ -16910,7 +18925,6 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 200Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \\\n \t\tUINT32_C(0x4)\n-\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19110,7 +21124,7 @@ struct hwrm_port_lpbk_qstats_output {\n ************************/\n \n \n-/* hwrm_port_ecn_qstats_input (size:192b/24B) */\n+/* hwrm_port_ecn_qstats_input (size:256b/32B) */\n struct hwrm_port_ecn_qstats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -19145,10 +21159,31 @@ struct hwrm_port_ecn_qstats_input {\n \t * multi-host mode.\n \t */\n \tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n+\t/*\n+\t * Size of the DMA buffer the caller has allocated for the firmware to\n+\t * write into.\n+\t */\n+\tuint16_t\tecn_stat_buf_size;\n+\tuint8_t\tflags;\n+\t/* This value is not used to avoid backward compatibility issues. */\n+\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n+\t/*\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n+\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \\\n+\t\tHWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This is the host address where\n+\t * ECN port statistics will be stored\n+\t */\n+\tuint64_t\tecn_stat_host_addr;\n } __rte_packed;\n \n-/* hwrm_port_ecn_qstats_output (size:384b/48B) */\n+/* hwrm_port_ecn_qstats_output (size:128b/16B) */\n struct hwrm_port_ecn_qstats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -19158,28 +21193,14 @@ struct hwrm_port_ecn_qstats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of packets marked in CoS queue 0. */\n-\tuint32_t\tmark_cnt_cos0;\n-\t/* Number of packets marked in CoS queue 1. */\n-\tuint32_t\tmark_cnt_cos1;\n-\t/* Number of packets marked in CoS queue 2. */\n-\tuint32_t\tmark_cnt_cos2;\n-\t/* Number of packets marked in CoS queue 3. */\n-\tuint32_t\tmark_cnt_cos3;\n-\t/* Number of packets marked in CoS queue 4. */\n-\tuint32_t\tmark_cnt_cos4;\n-\t/* Number of packets marked in CoS queue 5. */\n-\tuint32_t\tmark_cnt_cos5;\n-\t/* Number of packets marked in CoS queue 6. */\n-\tuint32_t\tmark_cnt_cos6;\n-\t/* Number of packets marked in CoS queue 7. */\n-\tuint32_t\tmark_cnt_cos7;\n+\t/* Number of bytes of stats the firmware wrote to the DMA buffer. */\n+\tuint16_t\tecn_stat_buf_size;\n \t/*\n \t * Bitmask that indicates which CoS queues have ECN marking enabled.\n \t * Bit i corresponds to CoS queue i.\n \t */\n \tuint8_t\tmark_en;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tunused_0[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19190,6 +21211,59 @@ struct hwrm_port_ecn_qstats_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/* ECN mark statistics format */\n+/* port_stats_ecn (size:512b/64B) */\n+struct port_stats_ecn {\n+\t/*\n+\t * Number of packets marked in CoS queue 0.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos0;\n+\t/*\n+\t * Number of packets marked in CoS queue 1.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos1;\n+\t/*\n+\t * Number of packets marked in CoS queue 2.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos2;\n+\t/*\n+\t * Number of packets marked in CoS queue 3.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos3;\n+\t/*\n+\t * Number of packets marked in CoS queue 4.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos4;\n+\t/*\n+\t * Number of packets marked in CoS queue 5.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos5;\n+\t/*\n+\t * Number of packets marked in CoS queue 6.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos6;\n+\t/*\n+\t * Number of packets marked in CoS queue 7.\n+\t * Or, if the driver requested counter masks, a mask to indicate the size\n+\t * of the counter.\n+\t */\n+\tuint64_t\tmark_cnt_cos7;\n+} __rte_packed;\n+\n /***********************\n * hwrm_port_clr_stats *\n ***********************/\n@@ -19351,14 +21425,20 @@ struct hwrm_port_phy_qcaps_output {\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \\\n \t\tUINT32_C(0x10)\n+\t/*\n+\t * If set to 1, then this field indicates that the\n+\t * local loopback is not supported on this controller.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n \t/*\n \t * Reserved field. The HWRM shall set this field to 0.\n \t * An HWRM client shall ignore this field.\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n-\t\tUINT32_C(0xe0)\n+\t\tUINT32_C(0xc0)\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \\\n-\t\t5\n+\t\t6\n \t/* Number of front panel ports for this device. */\n \tuint8_t\tport_cnt;\n \t/* Not supported or unknown */\n@@ -21479,6 +23559,161 @@ struct hwrm_port_phy_mdio_bus_release_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/************************\n+ * hwrm_port_tx_fir_cfg *\n+ ************************/\n+\n+\n+/* hwrm_port_tx_fir_cfg_input (size:320b/40B) */\n+struct hwrm_port_tx_fir_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Modulation types of TX FIR: NRZ, PAM4. */\n+\tuint8_t\tmod_type;\n+\t/* For NRZ */\n+\t#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)\n+\t/* For PAM4 */\n+\t#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)\n+\t#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \\\n+\t\tHWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4\n+\t/* The lane mask of the lane TX FIR will be configured. */\n+\tuint8_t\tlane_mask;\n+\tuint8_t\tunused_0[2];\n+\t/* Value1 of TX FIR, required for NRZ or PAM4. */\n+\tuint32_t\ttxfir_val_1;\n+\t/* Value2 of TX FIR, required for NRZ or PAM4. */\n+\tuint32_t\ttxfir_val_2;\n+\t/* Value3 of TX FIR, required for PAM4. */\n+\tuint32_t\ttxfir_val_3;\n+\t/* Value4 of TX FIR, required for PAM4. */\n+\tuint32_t\ttxfir_val_4;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_port_tx_fir_cfg_output (size:128b/16B) */\n+struct hwrm_port_tx_fir_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*************************\n+ * hwrm_port_tx_fir_qcfg *\n+ *************************/\n+\n+\n+/* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */\n+struct hwrm_port_tx_fir_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Modulation types of TX FIR: NRZ, PAM4. */\n+\tuint8_t\tmod_type;\n+\t/* For NRZ */\n+\t#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)\n+\t/* For PAM4 */\n+\t#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)\n+\t#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \\\n+\t\tHWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4\n+\t/* The ID of the lane TX FIR will be queried. */\n+\tuint8_t\tlane_id;\n+\tuint8_t\tunused[6];\n+} __rte_packed;\n+\n+/* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */\n+struct hwrm_port_tx_fir_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Value1 of TX FIR, required for NRZ or PAM4. */\n+\tuint32_t\ttxfir_val_1;\n+\t/* Value2 of TX FIR, required for NRZ or PAM4. */\n+\tuint32_t\ttxfir_val_2;\n+\t/* Value3 of TX FIR, required for PAM4. */\n+\tuint32_t\ttxfir_val_3;\n+\t/* Value4 of TX FIR, required for PAM4. */\n+\tuint32_t\ttxfir_val_4;\n+\tuint8_t\tunused[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***********************\n * hwrm_queue_qportcfg *\n ***********************/\n@@ -21642,8 +23877,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21678,8 +23915,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21714,8 +23953,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21750,8 +23991,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21786,8 +24029,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21822,8 +24067,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21858,8 +24105,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -21894,8 +24143,10 @@ struct hwrm_queue_qportcfg_output {\n \t * that takes a queue id.\n \t * # IDs must always be queried by this command before any use\n \t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n+\t * # The CoS queue index is obtained by applying modulo 10 to the\n+\t * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.\n+\t * The CoS queue index is used to reference port statistics for the\n+\t * CoS queue.\n \t * # A value of 0xff indicates that the queue is not available.\n \t * # Available queues may not be in sequential order.\n \t */\n@@ -27251,6 +29502,12 @@ struct hwrm_ring_alloc_input {\n \t */\n \t#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \\\n \t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the mpc_chnls_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \\\n+\t\tUINT32_C(0x400)\n \t/* Ring Type. */\n \tuint8_t\tring_type;\n \t/* L2 Completion Ring (CR) */\n@@ -27483,7 +29740,36 @@ struct hwrm_ring_alloc_input {\n \t#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)\n \t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \\\n \t\tHWRM_RING_ALLOC_INPUT_INT_MODE_POLL\n-\tuint8_t\tunused_4[3];\n+\t/* Midpath channel type */\n+\tuint8_t\tmpc_chnls_type;\n+\t/*\n+\t * Indicate the TX ring alloc MPC channel type is a MPC channel\n+\t * with destination to the TX crypto engine block.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)\n+\t/*\n+\t * Indicate the RX ring alloc MPC channel type is a MPC channel\n+\t * with destination to the RX crypto engine block.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)\n+\t/*\n+\t * Indicate the RX ring alloc MPC channel type is a MPC channel\n+\t * with destination to the TX configurable flow processing block.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)\n+\t/*\n+\t * Indicate the RX ring alloc MPC channel type is a MPC channel\n+\t * with destination to the RX configurable flow processing block.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)\n+\t/*\n+\t * Indicate the RX ring alloc MPC channel type is a MPC channel\n+\t * with destination to the primate processor block.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)\n+\t#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE\n+\tuint8_t\tunused_4[2];\n \t/*\n \t * The cq_handle is specified when allocating a completion ring. For\n \t * devices that support NQs, this cq_handle will be included in the\n@@ -35339,13 +37625,13 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_cfa_pair_info *\n- **********************/\n+/**************************\n+ * hwrm_cfa_vf_pair_alloc *\n+ **************************/\n \n \n-/* hwrm_cfa_pair_info_input (size:448b/56B) */\n-struct hwrm_cfa_pair_info_input {\n+/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */\n+struct hwrm_cfa_vf_pair_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35374,23 +37660,17 @@ struct hwrm_cfa_pair_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* If this flag is set, lookup by name else lookup by index. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n-\t/* If this flag is set, lookup by PF id and VF id. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n-\t/* Pair table index. */\n-\tuint16_t\tpair_index;\n-\t/* Pair pf index. */\n-\tuint8_t\tpair_pfid;\n-\t/* Pair vf index. */\n-\tuint8_t\tpair_vfid;\n-\t/* Pair name (32 byte string). */\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_a_id;\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_b_id;\n+\tuint8_t\tunused_0[4];\n+\t/* VF Pair name (32 byte string). */\n \tchar\tpair_name[32];\n } __rte_packed;\n \n-/* hwrm_cfa_pair_info_output (size:576b/72B) */\n-struct hwrm_cfa_pair_info_output {\n+/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_vf_pair_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35399,56 +37679,6 @@ struct hwrm_cfa_pair_info_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Pair table index. */\n-\tuint16_t\tnext_pair_index;\n-\t/* Pair member a's fid. */\n-\tuint16_t\ta_fid;\n-\t/* Logical host number. */\n-\tuint8_t\thost_a_index;\n-\t/* Logical PF number. */\n-\tuint8_t\tpf_a_index;\n-\t/* Pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_a_index;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code_a;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action_a;\n-\t/* Pair member b's fid. */\n-\tuint16_t\tb_fid;\n-\t/* Logical host number. */\n-\tuint8_t\thost_b_index;\n-\t/* Logical PF number. */\n-\tuint8_t\tpf_b_index;\n-\t/* Pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_b_index;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code_b;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action_b;\n-\t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */\n-\tuint8_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \\\n-\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR\n-\t/* Pair state. */\n-\tuint8_t\tpair_state;\n-\t/* Pair has been allocated */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n-\t/* Both pair members are active */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n-\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n-\t/* Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -35460,85 +37690,13 @@ struct hwrm_cfa_pair_info_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_cfa_vfr_alloc *\n- **********************/\n-\n-\n-/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */\n-struct hwrm_cfa_vfr_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_id;\n-\t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n-\t */\n-\tuint16_t\treserved;\n-\tuint8_t\tunused_0[4];\n-\t/* VF Representor name (32 byte string). */\n-\tchar\tvfr_name[32];\n-} __rte_packed;\n-\n-/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_vfr_alloc_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action;\n-\tuint8_t\tunused_0[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/*********************\n- * hwrm_cfa_vfr_free *\n- *********************/\n+/*************************\n+ * hwrm_cfa_vf_pair_free *\n+ *************************/\n \n \n-/* hwrm_cfa_vfr_free_input (size:448b/56B) */\n-struct hwrm_cfa_vfr_free_input {\n+/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */\n+struct hwrm_cfa_vf_pair_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35567,16 +37725,12 @@ struct hwrm_cfa_vfr_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VF Representor name (32 byte string). */\n-\tchar\t\tvfr_name[32];\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_id;\n-\tuint16_t\treserved;\n-\tuint8_t\t\tunused_0[4];\n+\t/* VF Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n } __rte_packed;\n \n-/* hwrm_cfa_vfr_free_output (size:128b/16B) */\n-struct hwrm_cfa_vfr_free_output {\n+/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */\n+struct hwrm_cfa_vf_pair_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35588,7 +37742,7 @@ struct hwrm_cfa_vfr_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -35596,15 +37750,13 @@ struct hwrm_cfa_vfr_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/*************************\n+ * hwrm_cfa_vf_pair_info *\n+ *************************/\n \n \n-/***************************************\n- * hwrm_cfa_redirect_query_tunnel_type *\n- ***************************************/\n-\n-\n-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */\n-struct hwrm_cfa_redirect_query_tunnel_type_input {\n+/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */\n+struct hwrm_cfa_vf_pair_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35633,13 +37785,18 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The source function id. */\n-\tuint16_t\tsrc_fid;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tflags;\n+\t/* If this flag is set, lookup by name else lookup by index. */\n+\t#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n+\t/* vf pair table index. */\n+\tuint16_t\tvf_pair_index;\n+\tuint8_t\tunused_0[2];\n+\t/* VF Pair name (32 byte string). */\n+\tchar\tvf_pair_name[32];\n } __rte_packed;\n \n-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */\n-struct hwrm_cfa_redirect_query_tunnel_type_output {\n+/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */\n+struct hwrm_cfa_vf_pair_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35648,51 +37805,28 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Tunnel Mask. */\n-\tuint32_t\ttunnel_mask;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \\\n-\t\tUINT32_C(0x1)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \\\n-\t\tUINT32_C(0x2)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \\\n-\t\tUINT32_C(0x10)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n-\t\tUINT32_C(0x20)\n-\t/* Multi-Protocol Label Switching (MPLS) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n-\t\tUINT32_C(0x40)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \\\n-\t\tUINT32_C(0x80)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \\\n-\t\tUINT32_C(0x100)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n-\t\tUINT32_C(0x200)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n-\t\tUINT32_C(0x400)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n-\t\tUINT32_C(0x800)\n-\t/* Use fixed layer 2 ether type of 0xFFFF */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n-\t\tUINT32_C(0x1000)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n-\t\tUINT32_C(0x2000)\n-\tuint8_t\tunused_0[3];\n+\t/* vf pair table index. */\n+\tuint16_t\tnext_vf_pair_index;\n+\t/* vf pair member a's vf_fid. */\n+\tuint16_t\tvf_a_fid;\n+\t/* vf pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_a_index;\n+\t/* vf pair member b's vf_fid. */\n+\tuint16_t\tvf_b_fid;\n+\t/* vf pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_b_index;\n+\t/* vf pair state. */\n+\tuint8_t\tpair_state;\n+\t/* Pair has been allocated */\n+\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n+\t/* Both pair members are active */\n+\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n+\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n+\t\tHWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n+\tuint8_t\tunused_0[5];\n+\t/* VF Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -35703,13 +37837,13 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_cfa_ctx_mem_rgtr *\n- *************************/\n+/***********************\n+ * hwrm_cfa_pair_alloc *\n+ ***********************/\n \n \n-/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */\n-struct hwrm_cfa_ctx_mem_rgtr_input {\n+/* hwrm_cfa_pair_alloc_input (size:576b/72B) */\n+struct hwrm_cfa_pair_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35738,44 +37872,104 @@ struct hwrm_cfa_ctx_mem_rgtr_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint16_t\tflags;\n-\t/* Counter PBL indirect levels. */\n-\tuint8_t\tpage_level;\n-\t/* PBL pointer is physical start address. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n-\t/* PBL pointer points to PTE table. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n-\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n-\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n-\t/* Page size. */\n-\tuint8_t\tpage_size;\n-\t/* 4KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n-\t/* 8KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n-\t/* 64KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n-\t/* 256KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n-\t/* 1MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n-\t/* 2MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n-\t/* 4MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n-\t/* 1GB page size. */\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n-\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n-\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G\n-\tuint32_t\tunused_0;\n-\t/* Pointer to the PBL, or PDL depending on number of levels */\n-\tuint64_t\tpage_dir;\n+\t/*\n+\t * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,\n+\t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n+\t */\n+\tuint16_t\tpair_mode;\n+\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \\\n+\t\tUINT32_C(0x0)\n+\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \\\n+\t\tUINT32_C(0x1)\n+\t/* Pair between REP on local host with REP on specified host. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \\\n+\t\tUINT32_C(0x2)\n+\t/* Pair for the proxy interface. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \\\n+\t\tUINT32_C(0x3)\n+\t/* Pair for the PF interface. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \\\n+\t\tUINT32_C(0x4)\n+\t/* Modify existing rep2fn pair and move pair to new PF. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \\\n+\t\tUINT32_C(0x5)\n+\t/* Modify exsiting rep2fn pairs paired with same PF and move pairs to new PF. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \\\n+\t\tUINT32_C(0x6)\n+\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \\\n+\t\tUINT32_C(0x7)\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \\\n+\t\tHWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_a_id;\n+\t/* Logical Host (0xff-local host). */\n+\tuint8_t\thost_b_id;\n+\t/* Logical PF (0xff-PF for command channel). */\n+\tuint8_t\tpf_b_id;\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_b_id;\n+\t/* Loopback port (0xff-internal loopback), valid for mode-3. */\n+\tuint8_t\tport_id;\n+\t/* Priority used for encap of loopback packets valid for mode-3. */\n+\tuint8_t\tpri;\n+\t/* New PF for rep2fn modify, valid for mode 5. */\n+\tuint16_t\tnew_pf_fid;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the q_ab field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the q_ba field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the fc_ab field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the fc_ba field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)\n+\t/* VF Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+\t/*\n+\t * The q_ab value specifies the logical index of the TX/RX CoS\n+\t * queue to be assigned for traffic in the A to B direction of\n+\t * the interface pair. The default value is 0.\n+\t */\n+\tuint8_t\tq_ab;\n+\t/*\n+\t * The q_ba value specifies the logical index of the TX/RX CoS\n+\t * queue to be assigned for traffic in the B to A direction of\n+\t * the interface pair. The default value is 1.\n+\t */\n+\tuint8_t\tq_ba;\n+\t/*\n+\t * Specifies whether RX ring flow control is disabled (0) or enabled\n+\t * (1) in the A to B direction. The default value is 0, meaning that\n+\t * packets will be dropped when the B-side RX rings are full.\n+\t */\n+\tuint8_t\tfc_ab;\n+\t/*\n+\t * Specifies whether RX ring flow control is disabled (0) or enabled\n+\t * (1) in the B to A direction. The default value is 1, meaning that\n+\t * the RX CoS queue will be flow controlled when the A-side RX rings\n+\t * are full.\n+\t */\n+\tuint8_t\tfc_ba;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */\n-struct hwrm_cfa_ctx_mem_rgtr_output {\n+/* hwrm_cfa_pair_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_pair_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35784,12 +37978,15 @@ struct hwrm_cfa_ctx_mem_rgtr_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n-\t */\n-\tuint16_t\tctx_id;\n-\tuint8_t\tunused_0[5];\n+\t/* Only valid for modes 1 and 2. */\n+\tuint16_t\trx_cfa_code_a;\n+\t/* Only valid for modes 1 and 2. */\n+\tuint16_t\ttx_cfa_action_a;\n+\t/* Only valid for mode 2. */\n+\tuint16_t\trx_cfa_code_b;\n+\t/* Only valid for mode 2. */\n+\tuint16_t\ttx_cfa_action_b;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -35800,13 +37997,13 @@ struct hwrm_cfa_ctx_mem_rgtr_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_cfa_ctx_mem_unrgtr *\n- ***************************/\n+/**********************\n+ * hwrm_cfa_pair_free *\n+ **********************/\n \n \n-/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */\n-struct hwrm_cfa_ctx_mem_unrgtr_input {\n+/* hwrm_cfa_pair_free_input (size:448b/56B) */\n+struct hwrm_cfa_pair_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35835,16 +38032,40 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* VF Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+\t/* Logical PF (0xff-PF for command channel). */\n+\tuint8_t\tpf_b_id;\n+\tuint8_t\tunused_0[3];\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_id;\n \t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n+\t * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,\n+\t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n \t */\n-\tuint16_t\tctx_id;\n-\tuint8_t\tunused_0[6];\n+\tuint16_t\tpair_mode;\n+\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n+\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n+\t/* Pair between REP on local host with REP on specified host. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n+\t/* Pair for the proxy interface. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n+\t/* Pair for the PF interface. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n+\t/* Modify existing rep2fn pair and move pair to new PF. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)\n+\t/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)\n+\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)\n+\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \\\n+\t\tHWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW\n } __rte_packed;\n \n-/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */\n-struct hwrm_cfa_ctx_mem_unrgtr_output {\n+/* hwrm_cfa_pair_free_output (size:128b/16B) */\n+struct hwrm_cfa_pair_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35864,13 +38085,13 @@ struct hwrm_cfa_ctx_mem_unrgtr_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_cfa_ctx_mem_qctx *\n- *************************/\n+/**********************\n+ * hwrm_cfa_pair_info *\n+ **********************/\n \n \n-/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */\n-struct hwrm_cfa_ctx_mem_qctx_input {\n+/* hwrm_cfa_pair_info_input (size:448b/56B) */\n+struct hwrm_cfa_pair_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35899,16 +38120,23 @@ struct hwrm_cfa_ctx_mem_qctx_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n-\t */\n-\tuint16_t\tctx_id;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tflags;\n+\t/* If this flag is set, lookup by name else lookup by index. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n+\t/* If this flag is set, lookup by PF id and VF id. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n+\t/* Pair table index. */\n+\tuint16_t\tpair_index;\n+\t/* Pair pf index. */\n+\tuint8_t\tpair_pfid;\n+\t/* Pair vf index. */\n+\tuint8_t\tpair_vfid;\n+\t/* Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n } __rte_packed;\n \n-/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */\n-struct hwrm_cfa_ctx_mem_qctx_output {\n+/* hwrm_cfa_pair_info_output (size:576b/72B) */\n+struct hwrm_cfa_pair_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -35917,41 +38145,57 @@ struct hwrm_cfa_ctx_mem_qctx_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint16_t\tflags;\n-\t/* Counter PBL indirect levels. */\n-\tuint8_t\tpage_level;\n-\t/* PBL pointer is physical start address. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n-\t/* PBL pointer points to PTE table. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n-\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \\\n-\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2\n-\t/* Page size. */\n-\tuint8_t\tpage_size;\n-\t/* 4KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)\n-\t/* 8KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)\n-\t/* 64KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)\n-\t/* 256KB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)\n-\t/* 1MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)\n-\t/* 2MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)\n-\t/* 4MB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)\n-\t/* 1GB page size. */\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)\n-\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \\\n-\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G\n-\tuint8_t\tunused_0[4];\n-\t/* Pointer to the PBL, or PDL depending on number of levels */\n-\tuint64_t\tpage_dir;\n-\tuint8_t\tunused_1[7];\n+\t/* Pair table index. */\n+\tuint16_t\tnext_pair_index;\n+\t/* Pair member a's fid. */\n+\tuint16_t\ta_fid;\n+\t/* Logical host number. */\n+\tuint8_t\thost_a_index;\n+\t/* Logical PF number. */\n+\tuint8_t\tpf_a_index;\n+\t/* Pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_a_index;\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code_a;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action_a;\n+\t/* Pair member b's fid. */\n+\tuint16_t\tb_fid;\n+\t/* Logical host number. */\n+\tuint8_t\thost_b_index;\n+\t/* Logical PF number. */\n+\tuint8_t\tpf_b_index;\n+\t/* Pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_b_index;\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code_b;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action_b;\n+\t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */\n+\tuint8_t\tpair_mode;\n+\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n+\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n+\t/* Pair between REP on local host with REP on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n+\t/* Pair for the proxy interface. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n+\t/* Pair for the PF interface. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \\\n+\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR\n+\t/* Pair state. */\n+\tuint8_t\tpair_state;\n+\t/* Pair has been allocated */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n+\t/* Both pair members are active */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n+\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n+\t/* Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -35962,13 +38206,13 @@ struct hwrm_cfa_ctx_mem_qctx_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_cfa_ctx_mem_qcaps *\n- **************************/\n+/**********************\n+ * hwrm_cfa_vfr_alloc *\n+ **********************/\n \n \n-/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */\n-struct hwrm_cfa_ctx_mem_qcaps_input {\n+/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */\n+struct hwrm_cfa_vfr_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -35997,10 +38241,20 @@ struct hwrm_cfa_ctx_mem_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_id;\n+\t/*\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n+\t */\n+\tuint16_t\treserved;\n+\tuint8_t\tunused_0[4];\n+\t/* VF Representor name (32 byte string). */\n+\tchar\tvfr_name[32];\n } __rte_packed;\n \n-/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */\n-struct hwrm_cfa_ctx_mem_qcaps_output {\n+/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_vfr_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36009,9 +38263,11 @@ struct hwrm_cfa_ctx_mem_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Indicates the maximum number of context memory which can be registered. */\n-\tuint16_t\tmax_entries;\n-\tuint8_t\tunused_0[5];\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36022,13 +38278,13 @@ struct hwrm_cfa_ctx_mem_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_cfa_eem_qcaps *\n- **********************/\n+/*********************\n+ * hwrm_cfa_vfr_free *\n+ *********************/\n \n \n-/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */\n-struct hwrm_cfa_eem_qcaps_input {\n+/* hwrm_cfa_vfr_free_input (size:448b/56B) */\n+struct hwrm_cfa_vfr_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36057,29 +38313,20 @@ struct hwrm_cfa_eem_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When set to 1, indicates the configuration will apply to TX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_rx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x1)\n+\t/* VF Representor name (32 byte string). */\n+\tchar\tvfr_name[32];\n+\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n+\tuint16_t\tvf_id;\n \t/*\n-\t * When set to 1, indicates the configuration will apply to RX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_tx bit can't be set.\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n \t */\n-\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x2)\n-\t/* When set to 1, all offloaded flows will be sent to EEM. */\n-\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x4)\n-\tuint32_t\tunused_0;\n+\tuint16_t\treserved;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */\n-struct hwrm_cfa_eem_qcaps_output {\n+/* hwrm_cfa_vfr_free_output (size:128b/16B) */\n+struct hwrm_cfa_vfr_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36088,87 +38335,7 @@ struct hwrm_cfa_eem_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When set to 1, indicates the configuration will apply to TX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_rx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * When set to 1, indicates the configuration will apply to RX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_tx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * When set to 1, indicates the the FW supports the Centralized\n-\t * Memory Model. The concept designates one entity for the\n-\t * memory allocation while all others ‘subscribe’ to it.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When set to 1, indicates the the FW supports the Detached\n-\t * Centralized Memory Model. The memory is allocated and managed\n-\t * as a separate entity. All PFs and VFs will be granted direct\n-\t * or semi-direct access to the allocated memory while none of\n-\t * which can interfere with the management of the memory.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n-\tuint32_t\tunused_0;\n-\tuint32_t\tsupported;\n-\t/*\n-\t * If set to 1, then EEM KEY0 table is supported using crc32 hash.\n-\t * If set to 0, EEM KEY0 table is not supported.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * If set to 1, then EEM KEY1 table is supported using lookup3 hash.\n-\t * If set to 0, EEM KEY1 table is not supported.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * If set to 1, then EEM External Record table is supported.\n-\t * If set to 0, EEM External Record table is not supported.\n-\t * (This table includes action record, EFC pointers, encap pointers)\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * If set to 1, then EEM External Flow Counters table is supported.\n-\t * If set to 0, EEM External Flow Counters table is not supported.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * If set to 1, then FID table used for implicit flow flush is supported.\n-\t * If set to 0, then FID table used for implicit flow flush is not supported.\n-\t */\n-\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * The maximum number of entries supported by EEM. When configuring the host memory\n-\t * the number of numbers of entries that can supported are -\n-\t * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.\n-\t * Any value that are not these values, the FW will round down to the closest support\n-\t * number of entries.\n-\t */\n-\tuint32_t\tmax_entries_supported;\n-\t/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */\n-\tuint16_t\tkey_entry_size;\n-\t/* The entry size in bytes of each entry in the EEM RECORD tables. */\n-\tuint16_t\trecord_entry_size;\n-\t/* The entry size in bytes of each entry in the EEM EFC tables. */\n-\tuint16_t\tefc_entry_size;\n-\t/* The FID size in bytes of each entry in the EEM FID tables. */\n-\tuint16_t\tfid_entry_size;\n-\tuint8_t\tunused_1[7];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36179,13 +38346,13 @@ struct hwrm_cfa_eem_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/********************\n- * hwrm_cfa_eem_cfg *\n- ********************/\n+/***************************************\n+ * hwrm_cfa_redirect_query_tunnel_type *\n+ ***************************************/\n \n \n-/* hwrm_cfa_eem_cfg_input (size:384b/48B) */\n-struct hwrm_cfa_eem_cfg_input {\n+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36214,65 +38381,66 @@ struct hwrm_cfa_eem_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When set to 1, indicates the configuration will apply to TX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_rx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \\\n+\t/* The source function id. */\n+\tuint16_t\tsrc_fid;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Tunnel Mask. */\n+\tuint32_t\ttunnel_mask;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * When set to 1, indicates the configuration will apply to RX flows\n-\t * which are to be offloaded.\n-\t * Note if this bit is set then the path_tx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \\\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \\\n \t\tUINT32_C(0x2)\n-\t/* When set to 1, all offloaded flows will be sent to EEM. */\n-\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \\\n \t\tUINT32_C(0x4)\n-\t/* When set to 1, secondary, 0 means primary. */\n-\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \\\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \\\n \t\tUINT32_C(0x8)\n-\t/*\n-\t * Group_id which used by Firmware to identify memory pools belonging\n-\t * to certain group.\n-\t */\n-\tuint16_t\tgroup_id;\n-\tuint16_t\tunused_0;\n-\t/*\n-\t * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,\n-\t * RECORD, EFC all have the same number of entries and all tables will be configured\n-\t * using this value. Current minimum value is 32k. Current maximum value is 128M.\n-\t */\n-\tuint32_t\tnum_entries;\n-\tuint32_t\tunused_1;\n-\t/* Configured EEM with the given context if for KEY0 table. */\n-\tuint16_t\tkey0_ctx_id;\n-\t/* Configured EEM with the given context if for KEY1 table. */\n-\tuint16_t\tkey1_ctx_id;\n-\t/* Configured EEM with the given context if for RECORD table. */\n-\tuint16_t\trecord_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tefc_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tfid_ctx_id;\n-\tuint16_t\tunused_2;\n-\tuint32_t\tunused_3;\n-} __rte_packed;\n-\n-/* hwrm_cfa_eem_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_eem_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \\\n+\t\tUINT32_C(0x10)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n+\t\tUINT32_C(0x20)\n+\t/* Multi-Protocol Label Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n+\t\tUINT32_C(0x40)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \\\n+\t\tUINT32_C(0x80)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \\\n+\t\tUINT32_C(0x100)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n+\t\tUINT32_C(0x200)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n+\t\tUINT32_C(0x400)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n+\t\tUINT32_C(0x800)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n+\t\tUINT32_C(0x1000)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0x2000)\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36283,13 +38451,13 @@ struct hwrm_cfa_eem_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_cfa_eem_qcfg *\n- *********************/\n+/*************************\n+ * hwrm_cfa_ctx_mem_rgtr *\n+ *************************/\n \n \n-/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */\n-struct hwrm_cfa_eem_qcfg_input {\n+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */\n+struct hwrm_cfa_ctx_mem_rgtr_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36318,16 +38486,44 @@ struct hwrm_cfa_eem_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* When set to 1, indicates the configuration is the TX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n-\t/* When set to 1, indicates the configuration is the RX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 256KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 1MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 1GB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G\n \tuint32_t\tunused_0;\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n } __rte_packed;\n \n-/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */\n-struct hwrm_cfa_eem_qcfg_output {\n+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_rgtr_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36336,29 +38532,12 @@ struct hwrm_cfa_eem_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/* When set to 1, indicates the configuration is the TX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x1)\n-\t/* When set to 1, indicates the configuration is the RX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x2)\n-\t/* When set to 1, all offloaded flows will be sent to EEM. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x4)\n-\t/* The number of entries the FW has configured for EEM. */\n-\tuint32_t\tnum_entries;\n-\t/* Configured EEM with the given context if for KEY0 table. */\n-\tuint16_t\tkey0_ctx_id;\n-\t/* Configured EEM with the given context if for KEY1 table. */\n-\tuint16_t\tkey1_ctx_id;\n-\t/* Configured EEM with the given context if for RECORD table. */\n-\tuint16_t\trecord_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tefc_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tfid_ctx_id;\n-\tuint8_t\tunused_2[5];\n+\t/*\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n+\t */\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36369,13 +38548,13 @@ struct hwrm_cfa_eem_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*******************\n- * hwrm_cfa_eem_op *\n- *******************/\n+/***************************\n+ * hwrm_cfa_ctx_mem_unrgtr *\n+ ***************************/\n \n \n-/* hwrm_cfa_eem_op_input (size:192b/24B) */\n-struct hwrm_cfa_eem_op_input {\n+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */\n+struct hwrm_cfa_ctx_mem_unrgtr_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36404,49 +38583,16 @@ struct hwrm_cfa_eem_op_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When set to 1, indicates the host memory which is passed will be\n-\t * used for the TX flow offload function specified in fid.\n-\t * Note if this bit is set then the path_rx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n-\t/*\n-\t * When set to 1, indicates the host memory which is passed will be\n-\t * used for the RX flow offload function specified in fid.\n-\t * Note if this bit is set then the path_tx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n-\tuint16_t\tunused_0;\n-\t/* The number of EEM key table entries to be configured. */\n-\tuint16_t\top;\n-\t/* This value is reserved and should not be used. */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)\n-\t/*\n-\t * To properly stop EEM and ensure there are no DMA's, the caller\n-\t * must disable EEM for the given PF, using this call. This will\n-\t * safely disable EEM and ensure that all DMA'ed to the\n-\t * keys/records/efc have been completed.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)\n-\t/*\n-\t * Once the EEM host memory has been configured, EEM options have\n-\t * been configured. Then the caller should enable EEM for the given\n-\t * PF. Note once this call has been made, then the EEM mechanism\n-\t * will be active and DMA's will occur as packets are processed.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)\n \t/*\n-\t * Clear EEM settings for the given PF so that the register values\n-\t * are reset back to there initial state.\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n \t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \\\n-\t\tHWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_cfa_eem_op_output (size:128b/16B) */\n-struct hwrm_cfa_eem_op_output {\n+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_unrgtr_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36466,13 +38612,13 @@ struct hwrm_cfa_eem_op_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/********************************\n- * hwrm_cfa_adv_flow_mgnt_qcaps *\n- ********************************/\n+/*************************\n+ * hwrm_cfa_ctx_mem_qctx *\n+ *************************/\n \n \n-/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */\n-struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */\n+struct hwrm_cfa_ctx_mem_qctx_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36501,11 +38647,16 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tunused_0[4];\n+\t/*\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n+\t */\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */\n-struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */\n+struct hwrm_cfa_ctx_mem_qctx_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36514,114 +38665,41 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/*\n-\t * Value of 1 to indicate firmware support 16-bit flow handle.\n-\t * Value of 0 to indicate firmware not support 16-bit flow handle.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * Value of 1 to indicate firmware support 64-bit flow handle.\n-\t * Value of 0 to indicate firmware not support 64-bit flow handle.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Value of 1 to indicate firmware support flow batch delete operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 to indicate that the firmware does not support flow batch delete\n-\t * operation.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * Value of 1 to indicate that the firmware support flow reset all operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 indicates firmware does not support flow reset all operation.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n-\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n-\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports TX EEM flows.\n-\t * Value of 0 indicates firmware does not support TX EEM flows.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports RX EEM flows.\n-\t * Value of 0 indicates firmware does not support RX EEM flows.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports the dynamic allocation of an\n-\t * on-chip flow counter which can be used for EEM flows.\n-\t * Value of 0 indicates firmware does not support the dynamic allocation of an\n-\t * on-chip flow counter.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports setting of\n-\t * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.\n-\t * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports untagged matching\n-\t * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0\n-\t * indicates firmware does not support untagged matching.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports XDP filter. Value\n-\t * of 0 indicates firmware does not support XDP filter.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * Value of 1 to indicate that the firmware support L2 header source\n-\t * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.\n-\t * Value of 0 indicates firmware does not support L2 header source\n-\t * fields matching.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \\\n-\t\tUINT32_C(0x800)\n-\t/*\n-\t * If set to 1, firmware is capable of supporting ARP ethertype as\n-\t * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the\n-\t * RX direction. By default, this flag should be 0 for older version\n-\t * of firmware.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \\\n-\t\tUINT32_C(0x1000)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports setting of\n-\t * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC\n-\t * command. Value of 0 indicates firmware does not support\n-\t * rfs_ring_tbl_idx in dst_id field.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \\\n-\t\tUINT32_C(0x2000)\n-\t/*\n-\t * If set to 1, firmware is capable of supporting IPv4/IPv6 as\n-\t * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX\n-\t * direction. By default, this flag should be 0 for older version\n-\t * of firmware.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n-\t\tUINT32_C(0x4000)\n-\tuint8_t\tunused_0[3];\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 256KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 1MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 1GB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G\n+\tuint8_t\tunused_0[4];\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36632,13 +38710,13 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************\n- * hwrm_cfa_tflib *\n- ******************/\n+/**************************\n+ * hwrm_cfa_ctx_mem_qcaps *\n+ **************************/\n \n \n-/* hwrm_cfa_tflib_input (size:1024b/128B) */\n-struct hwrm_cfa_tflib_input {\n+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36667,18 +38745,10 @@ struct hwrm_cfa_tflib_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* TFLIB message type. */\n-\tuint16_t\ttf_type;\n-\t/* TFLIB message subtype. */\n-\tuint16_t\ttf_subtype;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n-\t/* TFLIB request data. */\n-\tuint32_t\ttf_req[26];\n } __rte_packed;\n \n-/* hwrm_cfa_tflib_output (size:5632b/704B) */\n-struct hwrm_cfa_tflib_output {\n+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36687,16 +38757,9 @@ struct hwrm_cfa_tflib_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* TFLIB message type. */\n-\tuint16_t\ttf_type;\n-\t/* TFLIB message subtype. */\n-\tuint16_t\ttf_subtype;\n-\t/* TFLIB response code */\n-\tuint32_t\ttf_resp_code;\n-\t/* TFLIB response data. */\n-\tuint32_t\ttf_resp[170];\n-\t/* unused. */\n-\tuint8_t\tunused1[7];\n+\t/* Indicates the maximum number of context memory which can be registered. */\n+\tuint16_t\tmax_entries;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36707,13 +38770,13 @@ struct hwrm_cfa_tflib_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********\n- * hwrm_tf *\n- ***********/\n+/**************************\n+ * hwrm_cfa_counter_qcaps *\n+ **************************/\n \n \n-/* hwrm_tf_input (size:1024b/128B) */\n-struct hwrm_tf_input {\n+/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */\n+struct hwrm_cfa_counter_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36742,18 +38805,10 @@ struct hwrm_tf_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* TF message type. */\n-\tuint16_t\ttype;\n-\t/* TF message subtype. */\n-\tuint16_t\tsubtype;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n-\t/* TF request data. */\n-\tuint32_t\treq[26];\n } __rte_packed;\n \n-/* hwrm_tf_output (size:5632b/704B) */\n-struct hwrm_tf_output {\n+/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */\n+struct hwrm_cfa_counter_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36762,34 +38817,63 @@ struct hwrm_tf_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* TF message type. */\n-\tuint16_t\ttype;\n-\t/* TF message subtype. */\n-\tuint16_t\tsubtype;\n-\t/* TF response code */\n-\tuint32_t\tresp_code;\n-\t/* TF response data. */\n-\tuint32_t\tresp[170];\n-\t/* unused. */\n-\tuint8_t\tunused1[7];\n+\tuint32_t\tflags;\n+\t/* Enumeration denoting the supported CFA counter format. */\n+\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \\\n+\t\tUINT32_C(0x1)\n+\t/* CFA counter types are not supported. */\n+\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* 64-bit packet counters followed by 64-bit byte counters format. */\n+\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \\\n+\t\tHWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT\n+\tuint32_t\tunused_0;\n+\t/* Minimum guaranteed number of flow counters supported for this function, in RX direction. */\n+\tuint32_t\tmin_rx_fc;\n+\t/* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */\n+\tuint32_t\tmax_rx_fc;\n+\t/* Minimum guaranteed number of flow counters supported for this function, in TX direction. */\n+\tuint32_t\tmin_tx_fc;\n+\t/* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */\n+\tuint32_t\tmax_tx_fc;\n+\t/* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */\n+\tuint32_t\tmin_rx_efc;\n+\t/* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */\n+\tuint32_t\tmax_rx_efc;\n+\t/* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */\n+\tuint32_t\tmin_tx_efc;\n+\t/* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */\n+\tuint32_t\tmax_tx_efc;\n+\t/* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */\n+\tuint32_t\tmin_rx_mdc;\n+\t/* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */\n+\tuint32_t\tmax_rx_mdc;\n+\t/* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */\n+\tuint32_t\tmin_tx_mdc;\n+\t/* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */\n+\tuint32_t\tmax_tx_mdc;\n+\t/* Maximum guaranteed number of flow counters which can be used during flow alloc. */\n+\tuint32_t\tmax_flow_alloc_fc;\n+\tuint8_t\tunused_1[3];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_tf_version_get *\n- ***********************/\n+/************************\n+ * hwrm_cfa_counter_cfg *\n+ ************************/\n \n \n-/* hwrm_tf_version_get_input (size:128b/16B) */\n-struct hwrm_tf_version_get_input {\n+/* hwrm_cfa_counter_cfg_input (size:256b/32B) */\n+struct hwrm_cfa_counter_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36818,44 +38902,90 @@ struct hwrm_tf_version_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-} __rte_packed;\n-\n-/* hwrm_tf_version_get_output (size:128b/16B) */\n-struct hwrm_tf_version_get_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tflags;\n+\t/* Enumeration denoting the configuration mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \\\n+\t\tUINT32_C(0x1)\n+\t/* Disable the configuration mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \\\n+\t\tUINT32_C(0x0)\n+\t/* Enable the configuration mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \\\n+\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE\n+\t/* Enumeration denoting the RX, TX type of the resource. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \\\n+\t\tUINT32_C(0x2)\n+\t/* Tx path. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* Rx path. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX\n+\t/* Enumeration denoting the data transfer mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2\n+\t/* Push mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \\\n+\t\t(UINT32_C(0x0) << 2)\n+\t/* Pull mode. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \\\n+\t\t(UINT32_C(0x1) << 2)\n+\t/* Pull on async update. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \\\n+\t\t(UINT32_C(0x2) << 2)\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \\\n+\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC\n+\tuint16_t\tcounter_type;\n+\t/* Flow counters. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)\n+\t/* Extended flow counters. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)\n+\t/* Meter drop counters. */\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)\n+\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \\\n+\t\tHWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC\n+\t/* Ctx memory handle to be used for the counter. */\n+\tuint16_t\tctx_id;\n+\t/* Counter update cadence hint (only in Push mode). */\n+\tuint16_t\tupdate_tmr_ms;\n+\t/* Total number of entries. */\n+\tuint32_t\tnum_entries;\n+\tuint32_t\tunused_0;\n+} __rte_packed;\n+\n+/* hwrm_cfa_counter_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_counter_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Version Major number. */\n-\tuint8_t\tmajor;\n-\t/* Version Minor number. */\n-\tuint8_t\tminor;\n-\t/* Version Update number. */\n-\tuint8_t\tupdate;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/************************\n- * hwrm_tf_session_open *\n- ************************/\n+/***************************\n+ * hwrm_cfa_counter_qstats *\n+ ***************************/\n \n \n-/* hwrm_tf_session_open_input (size:640b/80B) */\n-struct hwrm_tf_session_open_input {\n+/* hwrm_cfa_counter_qstats_input (size:320b/40B) */\n+struct hwrm_cfa_counter_qstats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36884,12 +39014,27 @@ struct hwrm_tf_session_open_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Name of the session. */\n-\tuint8_t\tsession_name[64];\n+\tuint16_t\tflags;\n+\t/* Enumeration denoting the RX, TX type of the resource. */\n+\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t/* Tx path. */\n+\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* Rx path. */\n+\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX\n+\tuint16_t\tcounter_type;\n+\tuint16_t\tinput_flow_ctx_id;\n+\tuint16_t\tnum_entries;\n+\tuint16_t\tdelta_time_ms;\n+\tuint16_t\tmeter_instance_id;\n+\tuint16_t\tmdc_ctx_id;\n+\tuint8_t\tunused_0[2];\n+\tuint64_t\texpected_count;\n } __rte_packed;\n \n-/* hwrm_tf_session_open_output (size:192b/24B) */\n-struct hwrm_tf_session_open_output {\n+/* hwrm_cfa_counter_qstats_output (size:128b/16B) */\n+struct hwrm_cfa_counter_qstats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36898,38 +39043,24 @@ struct hwrm_tf_session_open_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Unique session identifier for the session created by the\n-\t * firmware.\n-\t */\n-\tuint32_t\tfw_session_id;\n-\t/*\n-\t * Unique session client identifier for the first client on\n-\t * the newly created session.\n-\t */\n-\tuint32_t\tfw_session_client_id;\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* unused. */\n-\tuint8_t\tunused1[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_tf_session_attach *\n- **************************/\n+/**********************\n+ * hwrm_cfa_eem_qcaps *\n+ **********************/\n \n \n-/* hwrm_tf_session_attach_input (size:704b/88B) */\n-struct hwrm_tf_session_attach_input {\n+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */\n+struct hwrm_cfa_eem_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -36958,25 +39089,29 @@ struct hwrm_tf_session_attach_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n \t/*\n-\t * Unique session identifier for the session that the attach\n-\t * request want to attach to. This value originates from the\n-\t * shared session memory that the attach request opened by\n-\t * way of the 'attach name' that was passed in to the core\n-\t * attach API.\n-\t * The fw_session_id of the attach session includes PCIe bus\n-\t * info to distinguish the PF and session info to identify\n-\t * the associated TruFlow session.\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n \t */\n-\tuint32_t\tattach_fw_session_id;\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* Name of the session it self. */\n-\tuint8_t\tsession_name[64];\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\tuint32_t\tunused_0;\n } __rte_packed;\n \n-/* hwrm_tf_session_attach_output (size:128b/16B) */\n-struct hwrm_tf_session_attach_output {\n+/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */\n+struct hwrm_cfa_eem_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -36985,34 +39120,104 @@ struct hwrm_tf_session_attach_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n \t/*\n-\t * Unique session identifier for the session created by the\n-\t * firmware. It includes PCIe bus info to distinguish the PF\n-\t * and session info to identify the associated TruFlow\n-\t * session. This fw_session_id is unique to the attach\n-\t * request.\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n \t */\n-\tuint32_t\tfw_session_id;\n-\t/* unused. */\n-\tuint8_t\tunused0[3];\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Centralized\n+\t * Memory Model. The concept designates one entity for the\n+\t * memory allocation while all others ‘subscribe’ to it.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Detached\n+\t * Centralized Memory Model. The memory is allocated and managed\n+\t * as a separate entity. All PFs and VFs will be granted direct\n+\t * or semi-direct access to the allocated memory while none of\n+\t * which can interfere with the management of the memory.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\tuint32_t\tunused_0;\n+\tuint32_t\tsupported;\n+\t/*\n+\t * If set to 1, then EEM KEY0 table is supported using crc32 hash.\n+\t * If set to 0, EEM KEY0 table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, then EEM KEY1 table is supported using lookup3 hash.\n+\t * If set to 0, EEM KEY1 table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, then EEM External Record table is supported.\n+\t * If set to 0, EEM External Record table is not supported.\n+\t * (This table includes action record, EFC pointers, encap pointers)\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then EEM External Flow Counters table is supported.\n+\t * If set to 0, EEM External Flow Counters table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, then FID table used for implicit flow flush is supported.\n+\t * If set to 0, then FID table used for implicit flow flush is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * The maximum number of entries supported by EEM. When configuring the host memory\n+\t * the number of numbers of entries that can supported are -\n+\t * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.\n+\t * Any value that are not these values, the FW will round down to the closest support\n+\t * number of entries.\n+\t */\n+\tuint32_t\tmax_entries_supported;\n+\t/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */\n+\tuint16_t\tkey_entry_size;\n+\t/* The entry size in bytes of each entry in the EEM RECORD tables. */\n+\tuint16_t\trecord_entry_size;\n+\t/* The entry size in bytes of each entry in the EEM EFC tables. */\n+\tuint16_t\tefc_entry_size;\n+\t/* The FID size in bytes of each entry in the EEM FID tables. */\n+\tuint16_t\tfid_entry_size;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/****************************\n- * hwrm_tf_session_register *\n- ****************************/\n+/********************\n+ * hwrm_cfa_eem_cfg *\n+ ********************/\n \n \n-/* hwrm_tf_session_register_input (size:704b/88B) */\n-struct hwrm_tf_session_register_input {\n+/* hwrm_cfa_eem_cfg_input (size:384b/48B) */\n+struct hwrm_cfa_eem_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37041,23 +39246,56 @@ struct hwrm_tf_session_register_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n \t/*\n-\t * Unique session identifier for the session that the\n-\t * register request want to create a new client on. This\n-\t * value originates from the first open request.\n-\t * The fw_session_id of the attach session includes PCIe bus\n-\t * info to distinguish the PF and session info to identify\n-\t * the associated TruFlow session.\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n \t */\n-\tuint32_t\tfw_session_id;\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* Name of the session client. */\n-\tuint8_t\tsession_client_name[64];\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\t/* When set to 1, secondary, 0 means primary. */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * Group_id which used by Firmware to identify memory pools belonging\n+\t * to certain group.\n+\t */\n+\tuint16_t\tgroup_id;\n+\tuint16_t\tunused_0;\n+\t/*\n+\t * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,\n+\t * RECORD, EFC all have the same number of entries and all tables will be configured\n+\t * using this value. Current minimum value is 32k. Current maximum value is 128M.\n+\t */\n+\tuint32_t\tnum_entries;\n+\tuint32_t\tunused_1;\n+\t/* Configured EEM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EEM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EEM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\tuint16_t\tunused_2;\n+\tuint32_t\tunused_3;\n } __rte_packed;\n \n-/* hwrm_tf_session_register_output (size:128b/16B) */\n-struct hwrm_tf_session_register_output {\n+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_eem_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37066,32 +39304,24 @@ struct hwrm_tf_session_register_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Unique session client identifier for the session created\n-\t * by the firmware. It includes the session the client it\n-\t * attached to and session client info.\n-\t */\n-\tuint32_t\tfw_session_client_id;\n-\t/* unused. */\n-\tuint8_t\tunused0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tf_session_unregister *\n- ******************************/\n+/*********************\n+ * hwrm_cfa_eem_qcfg *\n+ *********************/\n \n \n-/* hwrm_tf_session_unregister_input (size:192b/24B) */\n-struct hwrm_tf_session_unregister_input {\n+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */\n+struct hwrm_cfa_eem_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37120,20 +39350,16 @@ struct hwrm_tf_session_unregister_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Unique session identifier for the session that the\n-\t * unregister request want to close a session client on.\n-\t */\n-\tuint32_t\tfw_session_id;\n-\t/*\n-\t * Unique session client identifier for the session that the\n-\t * unregister request want to close.\n-\t */\n-\tuint32_t\tfw_session_client_id;\n+\tuint32_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint32_t\tunused_0;\n } __rte_packed;\n \n-/* hwrm_tf_session_unregister_output (size:128b/16B) */\n-struct hwrm_tf_session_unregister_output {\n+/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */\n+struct hwrm_cfa_eem_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37142,26 +39368,46 @@ struct hwrm_tf_session_unregister_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint32_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\t/* The number of entries the FW has configured for EEM. */\n+\tuint32_t\tnum_entries;\n+\t/* Configured EEM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EEM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EEM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\tuint8_t\tunused_2[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_tf_session_close *\n- *************************/\n+/*******************\n+ * hwrm_cfa_eem_op *\n+ *******************/\n \n \n-/* hwrm_tf_session_close_input (size:192b/24B) */\n-struct hwrm_tf_session_close_input {\n+/* hwrm_cfa_eem_op_input (size:192b/24B) */\n+struct hwrm_cfa_eem_op_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37190,14 +39436,49 @@ struct hwrm_tf_session_close_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the TX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the RX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint16_t\tunused_0;\n+\t/* The number of EEM key table entries to be configured. */\n+\tuint16_t\top;\n+\t/* This value is reserved and should not be used. */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)\n+\t/*\n+\t * To properly stop EEM and ensure there are no DMA's, the caller\n+\t * must disable EEM for the given PF, using this call. This will\n+\t * safely disable EEM and ensure that all DMA'ed to the\n+\t * keys/records/efc have been completed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)\n+\t/*\n+\t * Once the EEM host memory has been configured, EEM options have\n+\t * been configured. Then the caller should enable EEM for the given\n+\t * PF. Note once this call has been made, then the EEM mechanism\n+\t * will be active and DMA's will occur as packets are processed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)\n+\t/*\n+\t * Clear EEM settings for the given PF so that the register values\n+\t * are reset back to there initial state.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \\\n+\t\tHWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP\n } __rte_packed;\n \n-/* hwrm_tf_session_close_output (size:128b/16B) */\n-struct hwrm_tf_session_close_output {\n+/* hwrm_cfa_eem_op_output (size:128b/16B) */\n+struct hwrm_cfa_eem_op_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37206,26 +39487,24 @@ struct hwrm_tf_session_close_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/************************\n- * hwrm_tf_session_qcfg *\n- ************************/\n+/********************************\n+ * hwrm_cfa_adv_flow_mgnt_qcaps *\n+ ********************************/\n \n \n-/* hwrm_tf_session_qcfg_input (size:192b/24B) */\n-struct hwrm_tf_session_qcfg_input {\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37254,14 +39533,11 @@ struct hwrm_tf_session_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n+\tuint32_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_tf_session_qcfg_output (size:128b/16B) */\n-struct hwrm_tf_session_qcfg_output {\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37270,74 +39546,131 @@ struct hwrm_tf_session_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* RX action control settings flags. */\n-\tuint8_t\trx_act_flags;\n+\tuint32_t\tflags;\n \t/*\n-\t * A value of 1 in this field indicates that Global Flow ID\n-\t * reporting into cfa_code and cfa_metadata is enabled.\n+\t * Value of 1 to indicate firmware support 16-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 16-bit flow handle.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \\\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * A value of 1 in this field indicates that both inner and outer\n-\t * are stripped and inner tag is passed.\n-\t * Enabled.\n+\t * Value of 1 to indicate firmware support 64-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 64-bit flow handle.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \\\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * A value of 1 in this field indicates that the re-use of\n-\t * existing tunnel L2 header SMAC is enabled for\n-\t * Non-tunnel L2, L2-L3 and IP-IP tunnel.\n+\t * Value of 1 to indicate firmware support flow batch delete operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 to indicate that the firmware does not support flow batch delete\n+\t * operation.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \\\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n \t\tUINT32_C(0x4)\n-\t/* TX Action control settings flags. */\n-\tuint8_t\ttx_act_flags;\n-\t/* Disabled. */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \\\n-\t\tUINT32_C(0x1)\n \t/*\n-\t * When set to 1 any GRE tunnels will include the\n-\t * optional Key field.\n+\t * Value of 1 to indicate that the firmware support flow reset all operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 indicates firmware does not support flow reset all operation.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)\n-\t * field of the outer header is inherited from the inner header\n-\t * (if present) or the fixed value as taken from the encap\n-\t * record.\n+\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n+\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n+\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)\n-\t * field of the outer header is inherited from the inner header\n-\t * (if present) or the fixed value as taken from the encap record.\n+\t * Value of 1 to indicate that firmware supports TX EEM flows.\n+\t * Value of 0 indicates firmware does not support TX EEM flows.\n \t */\n-\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \\\n-\t\tUINT32_C(0x8)\n-\t/* unused. */\n-\tuint8_t\tunused0[5];\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports RX EEM flows.\n+\t * Value of 0 indicates firmware does not support RX EEM flows.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports the dynamic allocation of an\n+\t * on-chip flow counter which can be used for EEM flows.\n+\t * Value of 0 indicates firmware does not support the dynamic allocation of an\n+\t * on-chip flow counter.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.\n+\t * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports untagged matching\n+\t * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0\n+\t * indicates firmware does not support untagged matching.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports XDP filter. Value\n+\t * of 0 indicates firmware does not support XDP filter.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * Value of 1 to indicate that the firmware support L2 header source\n+\t * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.\n+\t * Value of 0 indicates firmware does not support L2 header source\n+\t * fields matching.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting ARP ethertype as\n+\t * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the\n+\t * RX direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC\n+\t * command. Value of 0 indicates firmware does not support\n+\t * rfs_ring_tbl_idx in dst_id field.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting IPv4/IPv6 as\n+\t * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX\n+\t * direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tf_session_resc_qcaps *\n- ******************************/\n+/******************\n+ * hwrm_cfa_tflib *\n+ ******************/\n \n \n-/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */\n-struct hwrm_tf_session_resc_qcaps_input {\n+/* hwrm_cfa_tflib_input (size:1024b/128B) */\n+struct hwrm_cfa_tflib_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37366,36 +39699,18 @@ struct hwrm_tf_session_resc_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * Defines the size of the provided qcaps_addr array\n-\t * buffer. The size should be set to the Resource Manager\n-\t * provided max number of qcaps entries which is device\n-\t * specific. Resource Manager gets the max size from HCAPI\n-\t * RM.\n-\t */\n-\tuint16_t\tqcaps_size;\n-\t/*\n-\t * This is the DMA address for the qcaps output data array\n-\t * buffer. Array is of tf_rm_resc_req_entry type and is\n-\t * device specific.\n-\t */\n-\tuint64_t\tqcaps_addr;\n+\t/* TFLIB message type. */\n+\tuint16_t\ttf_type;\n+\t/* TFLIB message subtype. */\n+\tuint16_t\ttf_subtype;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/* TFLIB request data. */\n+\tuint32_t\ttf_req[26];\n } __rte_packed;\n \n-/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */\n-struct hwrm_tf_session_resc_qcaps_output {\n+/* hwrm_cfa_tflib_output (size:5632b/704B) */\n+struct hwrm_cfa_tflib_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37404,55 +39719,33 @@ struct hwrm_tf_session_resc_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Session reservation strategy. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \\\n-\t\tUINT32_C(0x3)\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \\\n-\t\t0\n-\t/* Static partitioning. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \\\n-\t\tUINT32_C(0x0)\n-\t/* Strategy 1. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \\\n-\t\tUINT32_C(0x1)\n-\t/* Strategy 2. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \\\n-\t\tUINT32_C(0x2)\n-\t/* Strategy 3. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \\\n-\t\tUINT32_C(0x3)\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3\n-\t/*\n-\t * Size of the returned qcaps_addr data array buffer. The\n-\t * value cannot exceed the size defined by the input msg,\n-\t * qcaps_size.\n-\t */\n-\tuint16_t\tsize;\n-\t/* unused. */\n-\tuint16_t\tunused0;\n+\t/* TFLIB message type. */\n+\tuint16_t\ttf_type;\n+\t/* TFLIB message subtype. */\n+\tuint16_t\ttf_subtype;\n+\t/* TFLIB response code */\n+\tuint32_t\ttf_resp_code;\n+\t/* TFLIB response data. */\n+\tuint32_t\ttf_resp[170];\n \t/* unused. */\n \tuint8_t\tunused1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tf_session_resc_alloc *\n- ******************************/\n+/***********\n+ * hwrm_tf *\n+ ***********/\n \n \n-/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */\n-struct hwrm_tf_session_resc_alloc_input {\n+/* hwrm_tf_input (size:1024b/128B) */\n+struct hwrm_tf_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37481,42 +39774,18 @@ struct hwrm_tf_session_resc_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * Defines the array size of the provided req_addr and\n-\t * resv_addr array buffers. Should be set to the number of\n-\t * request entries.\n-\t */\n-\tuint16_t\treq_size;\n-\t/*\n-\t * This is the DMA address for the request input data array\n-\t * buffer. Array is of tf_rm_resc_req_entry type. Size of the\n-\t * array buffer is provided by the 'req_size' field in this\n-\t * message.\n-\t */\n-\tuint64_t\treq_addr;\n-\t/*\n-\t * This is the DMA address for the resc output data array\n-\t * buffer. Array is of tf_rm_resc_entry type. Size of the array\n-\t * buffer is provided by the 'req_size' field in this\n-\t * message.\n-\t */\n-\tuint64_t\tresc_addr;\n+\t/* TF message type. */\n+\tuint16_t\ttype;\n+\t/* TF message subtype. */\n+\tuint16_t\tsubtype;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/* TF request data. */\n+\tuint32_t\treq[26];\n } __rte_packed;\n \n-/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */\n-struct hwrm_tf_session_resc_alloc_output {\n+/* hwrm_tf_output (size:5632b/704B) */\n+struct hwrm_tf_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37525,33 +39794,34 @@ struct hwrm_tf_session_resc_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Size of the returned tf_rm_resc_entry data array. The value\n-\t * cannot exceed the req_size defined by the input msg. The data\n-\t * array is returned using the resv_addr specified DMA\n-\t * address also provided by the input msg.\n-\t */\n-\tuint16_t\tsize;\n+\t/* TF message type. */\n+\tuint16_t\ttype;\n+\t/* TF message subtype. */\n+\tuint16_t\tsubtype;\n+\t/* TF response code */\n+\tuint32_t\tresp_code;\n+\t/* TF response data. */\n+\tuint32_t\tresp[170];\n \t/* unused. */\n-\tuint8_t\tunused0[5];\n+\tuint8_t\tunused1[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*****************************\n- * hwrm_tf_session_resc_free *\n- *****************************/\n+/***********************\n+ * hwrm_tf_version_get *\n+ ***********************/\n \n \n-/* hwrm_tf_session_resc_free_input (size:256b/32B) */\n-struct hwrm_tf_session_resc_free_input {\n+/* hwrm_tf_version_get_input (size:128b/16B) */\n+struct hwrm_tf_version_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37580,34 +39850,10 @@ struct hwrm_tf_session_resc_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * Defines the size, in bytes, of the provided free_addr\n-\t * buffer.\n-\t */\n-\tuint16_t\tfree_size;\n-\t/*\n-\t * This is the DMA address for the free input data array\n-\t * buffer. Array is of tf_rm_resc_entry type. Size of the\n-\t * buffer is provided by the 'free_size' field of this\n-\t * message.\n-\t */\n-\tuint64_t\tfree_addr;\n } __rte_packed;\n \n-/* hwrm_tf_session_resc_free_output (size:128b/16B) */\n-struct hwrm_tf_session_resc_free_output {\n+/* hwrm_tf_version_get_output (size:128b/16B) */\n+struct hwrm_tf_version_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37616,8 +39862,14 @@ struct hwrm_tf_session_resc_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* Version Major number. */\n+\tuint8_t\tmajor;\n+\t/* Version Minor number. */\n+\tuint8_t\tminor;\n+\t/* Version Update number. */\n+\tuint8_t\tupdate;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused0[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -37629,13 +39881,13 @@ struct hwrm_tf_session_resc_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tf_session_resc_flush *\n- ******************************/\n+/************************\n+ * hwrm_tf_session_open *\n+ ************************/\n \n \n-/* hwrm_tf_session_resc_flush_input (size:256b/32B) */\n-struct hwrm_tf_session_resc_flush_input {\n+/* hwrm_tf_session_open_input (size:640b/80B) */\n+struct hwrm_tf_session_open_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37664,34 +39916,12 @@ struct hwrm_tf_session_resc_flush_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * Defines the size, in bytes, of the provided flush_addr\n-\t * buffer.\n-\t */\n-\tuint16_t\tflush_size;\n-\t/*\n-\t * This is the DMA address for the flush input data array\n-\t * buffer. Array of tf_rm_resc_entry type. Size of the\n-\t * buffer is provided by the 'flush_size' field in this\n-\t * message.\n-\t */\n-\tuint64_t\tflush_addr;\n+\t/* Name of the session. */\n+\tuint8_t\tsession_name[64];\n } __rte_packed;\n \n-/* hwrm_tf_session_resc_flush_output (size:128b/16B) */\n-struct hwrm_tf_session_resc_flush_output {\n+/* hwrm_tf_session_open_output (size:192b/24B) */\n+struct hwrm_tf_session_open_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37700,8 +39930,20 @@ struct hwrm_tf_session_resc_flush_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/*\n+\t * Unique session client identifier for the first client on\n+\t * the newly created session.\n+\t */\n+\tuint32_t\tfw_session_client_id;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint32_t\tunused0;\n+\t/* unused. */\n+\tuint8_t\tunused1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -37713,35 +39955,13 @@ struct hwrm_tf_session_resc_flush_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* TruFlow RM capability of a resource. */\n-/* tf_rm_resc_req_entry (size:64b/8B) */\n-struct tf_rm_resc_req_entry {\n-\t/* Type of the resource, defined globally in HCAPI RM. */\n-\tuint32_t\ttype;\n-\t/* Minimum value. */\n-\tuint16_t\tmin;\n-\t/* Maximum value. */\n-\tuint16_t\tmax;\n-} __rte_packed;\n-\n-/* TruFlow RM reservation information. */\n-/* tf_rm_resc_entry (size:64b/8B) */\n-struct tf_rm_resc_entry {\n-\t/* Type of the resource, defined globally in HCAPI RM. */\n-\tuint32_t\ttype;\n-\t/* Start offset. */\n-\tuint16_t\tstart;\n-\t/* Number of resources. */\n-\tuint16_t\tstride;\n-} __rte_packed;\n-\n-/************************\n- * hwrm_tf_tbl_type_get *\n- ************************/\n+/**************************\n+ * hwrm_tf_session_attach *\n+ **************************/\n \n \n-/* hwrm_tf_tbl_type_get_input (size:256b/32B) */\n-struct hwrm_tf_tbl_type_get_input {\n+/* hwrm_tf_session_attach_input (size:704b/88B) */\n+struct hwrm_tf_session_attach_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37770,31 +39990,25 @@ struct hwrm_tf_tbl_type_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX\n-\t/* unused. */\n-\tuint8_t\tunused0[2];\n \t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n+\t * Unique session identifier for the session that the attach\n+\t * request want to attach to. This value originates from the\n+\t * shared session memory that the attach request opened by\n+\t * way of the 'attach name' that was passed in to the core\n+\t * attach API.\n+\t * The fw_session_id of the attach session includes PCIe bus\n+\t * info to distinguish the PF and session info to identify\n+\t * the associated TruFlow session.\n \t */\n-\tuint32_t\ttype;\n-\t/* Index of the type to retrieve. */\n-\tuint32_t\tindex;\n+\tuint32_t\tattach_fw_session_id;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Name of the session it self. */\n+\tuint8_t\tsession_name[64];\n } __rte_packed;\n \n-/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */\n-struct hwrm_tf_tbl_type_get_output {\n+/* hwrm_tf_session_attach_output (size:128b/16B) */\n+struct hwrm_tf_session_attach_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37803,34 +40017,34 @@ struct hwrm_tf_tbl_type_get_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Response code. */\n-\tuint32_t\tresp_code;\n-\t/* Response size. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint16_t\tunused0;\n-\t/* Response data. */\n-\tuint8_t\tdata[128];\n-\t/* unused */\n-\tuint8_t\tunused1[7];\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. It includes PCIe bus info to distinguish the PF\n+\t * and session info to identify the associated TruFlow\n+\t * session. This fw_session_id is unique to the attach\n+\t * request.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/************************\n- * hwrm_tf_tbl_type_set *\n- ************************/\n+/****************************\n+ * hwrm_tf_session_register *\n+ ****************************/\n \n \n-/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */\n-struct hwrm_tf_tbl_type_set_input {\n+/* hwrm_tf_session_register_input (size:704b/88B) */\n+struct hwrm_tf_session_register_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37859,37 +40073,23 @@ struct hwrm_tf_tbl_type_set_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\t/*\n+\t * Unique session identifier for the session that the\n+\t * register request want to create a new client on. This\n+\t * value originates from the first open request.\n+\t * The fw_session_id of the attach session includes PCIe bus\n+\t * info to distinguish the PF and session info to identify\n+\t * the associated TruFlow session.\n+\t */\n \tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX\n \t/* unused. */\n-\tuint8_t\tunused0[2];\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n-\tuint32_t\ttype;\n-\t/* Index of the type to retrieve. */\n-\tuint32_t\tindex;\n-\t/* Size of the data to set. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint8_t\tunused1[6];\n-\t/* Data to be set. */\n-\tuint8_t\tdata[88];\n+\tuint32_t\tunused0;\n+\t/* Name of the session client. */\n+\tuint8_t\tsession_client_name[64];\n } __rte_packed;\n \n-/* hwrm_tf_tbl_type_set_output (size:128b/16B) */\n-struct hwrm_tf_tbl_type_set_output {\n+/* hwrm_tf_session_register_output (size:128b/16B) */\n+struct hwrm_tf_session_register_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37898,26 +40098,32 @@ struct hwrm_tf_tbl_type_set_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session client identifier for the session created\n+\t * by the firmware. It includes the session the client it\n+\t * attached to and session client info.\n+\t */\n+\tuint32_t\tfw_session_client_id;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_tf_ctxt_mem_rgtr *\n- *************************/\n+/******************************\n+ * hwrm_tf_session_unregister *\n+ ******************************/\n \n \n-/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */\n-struct hwrm_tf_ctxt_mem_rgtr_input {\n+/* hwrm_tf_session_unregister_input (size:192b/24B) */\n+struct hwrm_tf_session_unregister_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -37946,49 +40152,20 @@ struct hwrm_tf_ctxt_mem_rgtr_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Counter PBL indirect levels. */\n-\tuint8_t\tpage_level;\n-\t/* PBL pointer is physical start address. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n-\t/* PBL pointer points to PTE table. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n \t/*\n-\t * PBL pointer points to PDE table with each entry pointing\n-\t * to PTE tables.\n+\t * Unique session identifier for the session that the\n+\t * unregister request want to close a session client on.\n \t */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n-\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n-\t/* Page size. */\n-\tuint8_t\tpage_size;\n-\t/* 4KB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n-\t/* 8KB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n-\t/* 64KB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n-\t/* 256KB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n-\t/* 1MB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n-\t/* 2MB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n-\t/* 4MB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n-\t/* 1GB page size. */\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n-\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n-\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* Pointer to the PBL, or PDL depending on number of levels */\n-\tuint64_t\tpage_dir;\n+\tuint32_t\tfw_session_id;\n+\t/*\n+\t * Unique session client identifier for the session that the\n+\t * unregister request want to close.\n+\t */\n+\tuint32_t\tfw_session_client_id;\n } __rte_packed;\n \n-/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */\n-struct hwrm_tf_ctxt_mem_rgtr_output {\n+/* hwrm_tf_session_unregister_output (size:128b/16B) */\n+struct hwrm_tf_session_unregister_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -37997,31 +40174,26 @@ struct hwrm_tf_ctxt_mem_rgtr_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Id/Handle to the recently register context memory. This\n-\t * handle is passed to the TF session.\n-\t */\n-\tuint16_t\tctx_id;\n \t/* unused. */\n-\tuint8_t\tunused0[5];\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_tf_ctxt_mem_unrgtr *\n- ***************************/\n+/*************************\n+ * hwrm_tf_session_close *\n+ *************************/\n \n \n-/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */\n-struct hwrm_tf_ctxt_mem_unrgtr_input {\n+/* hwrm_tf_session_close_input (size:192b/24B) */\n+struct hwrm_tf_session_close_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38050,17 +40222,14 @@ struct hwrm_tf_ctxt_mem_unrgtr_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Id/Handle to the recently register context memory. This\n-\t * handle is passed to the TF session.\n-\t */\n-\tuint16_t\tctx_id;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* unused. */\n-\tuint8_t\tunused0[6];\n+\tuint8_t\tunused0[4];\n } __rte_packed;\n \n-/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */\n-struct hwrm_tf_ctxt_mem_unrgtr_output {\n+/* hwrm_tf_session_close_output (size:128b/16B) */\n+struct hwrm_tf_session_close_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38072,23 +40241,23 @@ struct hwrm_tf_ctxt_mem_unrgtr_output {\n \t/* unused. */\n \tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n /************************\n- * hwrm_tf_ext_em_qcaps *\n+ * hwrm_tf_session_qcfg *\n ************************/\n \n \n-/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */\n-struct hwrm_tf_ext_em_qcaps_input {\n+/* hwrm_tf_session_qcfg_input (size:192b/24B) */\n+struct hwrm_tf_session_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38117,28 +40286,14 @@ struct hwrm_tf_ext_em_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \\\n-\t\tUINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \\\n-\t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX\n-\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n-\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x2)\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* unused. */\n-\tuint32_t\tunused0;\n+\tuint8_t\tunused0[4];\n } __rte_packed;\n \n-/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */\n-struct hwrm_tf_ext_em_qcaps_output {\n+/* hwrm_tf_session_qcfg_output (size:128b/16B) */\n+struct hwrm_tf_session_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38147,109 +40302,74 @@ struct hwrm_tf_ext_em_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n+\t/* RX action control settings flags. */\n+\tuint8_t\trx_act_flags;\n \t/*\n-\t * When set to 1, indicates the the FW supports the Centralized\n-\t * Memory Model. The concept designates one entity for the\n-\t * memory allocation while all others ‘subscribe’ to it.\n+\t * A value of 1 in this field indicates that Global Flow ID\n+\t * reporting into cfa_code and cfa_metadata is enabled.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When set to 1, indicates the the FW supports the Detached\n-\t * Centralized Memory Model. The memory is allocated and managed\n-\t * as a separate entity. All PFs and VFs will be granted direct\n-\t * or semi-direct access to the allocated memory while none of\n-\t * which can interfere with the management of the memory.\n+\t * A value of 1 in this field indicates that both inner and outer\n+\t * are stripped and inner tag is passed.\n+\t * Enabled.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \\\n \t\tUINT32_C(0x2)\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* Support flags. */\n-\tuint32_t\tsupported;\n \t/*\n-\t * If set to 1, then EXT EM KEY0 table is supported using\n-\t * crc32 hash.\n-\t * If set to 0, EXT EM KEY0 table is not supported.\n+\t * A value of 1 in this field indicates that the re-use of\n+\t * existing tunnel L2 header SMAC is enabled for\n+\t * Non-tunnel L2, L2-L3 and IP-IP tunnel.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \\\n+\t\tUINT32_C(0x4)\n+\t/* TX Action control settings flags. */\n+\tuint8_t\ttx_act_flags;\n+\t/* Disabled. */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, then EXT EM KEY1 table is supported using\n-\t * lookup3 hash.\n-\t * If set to 0, EXT EM KEY1 table is not supported.\n+\t * When set to 1 any GRE tunnels will include the\n+\t * optional Key field.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * If set to 1, then EXT EM External Record table is supported.\n-\t * If set to 0, EXT EM External Record table is not\n-\t * supported. (This table includes action record, EFC\n-\t * pointers, encap pointers)\n+\t * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)\n+\t * field of the outer header is inherited from the inner header\n+\t * (if present) or the fixed value as taken from the encap\n+\t * record.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * If set to 1, then EXT EM External Flow Counters table is\n-\t * supported.\n-\t * If set to 0, EXT EM External Flow Counters table is not\n-\t * supported.\n+\t * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)\n+\t * field of the outer header is inherited from the inner header\n+\t * (if present) or the fixed value as taken from the encap record.\n \t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \\\n \t\tUINT32_C(0x8)\n-\t/*\n-\t * If set to 1, then FID table used for implicit flow flush\n-\t * is supported.\n-\t * If set to 0, then FID table used for implicit flow flush\n-\t * is not supported.\n-\t */\n-\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * The maximum number of entries supported by EXT EM. When\n-\t * configuring the host memory the number of numbers of\n-\t * entries that can supported are -\n-\t * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,\n-\t * 128M entries.\n-\t * Any value that are not these values, the FW will round\n-\t * down to the closest support number of entries.\n-\t */\n-\tuint32_t\tmax_entries_supported;\n-\t/*\n-\t * The entry size in bytes of each entry in the EXT EM\n-\t * KEY0/KEY1 tables.\n-\t */\n-\tuint16_t\tkey_entry_size;\n-\t/*\n-\t * The entry size in bytes of each entry in the EXT EM RECORD\n-\t * tables.\n-\t */\n-\tuint16_t\trecord_entry_size;\n-\t/* The entry size in bytes of each entry in the EXT EM EFC tables. */\n-\tuint16_t\tefc_entry_size;\n-\t/* The FID size in bytes of each entry in the EXT EM FID tables. */\n-\tuint16_t\tfid_entry_size;\n \t/* unused. */\n-\tuint8_t\tunused1[7];\n+\tuint8_t\tunused0[5];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_tf_ext_em_op *\n- *********************/\n+/******************************\n+ * hwrm_tf_session_resc_qcaps *\n+ ******************************/\n \n \n-/* hwrm_tf_ext_em_op_input (size:192b/24B) */\n-struct hwrm_tf_ext_em_op_input {\n+/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38278,51 +40398,36 @@ struct hwrm_tf_ext_em_op_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n \tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX\n-\t/* unused. */\n-\tuint16_t\tunused0;\n-\t/* The number of EXT EM key table entries to be configured. */\n-\tuint16_t\top;\n-\t/* This value is reserved and should not be used. */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)\n-\t/*\n-\t * To properly stop EXT EM and ensure there are no DMA's,\n-\t * the caller must disable EXT EM for the given PF, using\n-\t * this call. This will safely disable EXT EM and ensure\n-\t * that all DMA'ed to the keys/records/efc have been\n-\t * completed.\n-\t */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * Once the EXT EM host memory has been configured, EXT EM\n-\t * options have been configured. Then the caller should\n-\t * enable EXT EM for the given PF. Note once this call has\n-\t * been made, then the EXT EM mechanism will be active and\n-\t * DMA's will occur as packets are processed.\n+\t * Defines the size of the provided qcaps_addr array\n+\t * buffer. The size should be set to the Resource Manager\n+\t * provided max number of qcaps entries which is device\n+\t * specific. Resource Manager gets the max size from HCAPI\n+\t * RM.\n \t */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)\n+\tuint16_t\tqcaps_size;\n \t/*\n-\t * Clear EXT EM settings for the given PF so that the\n-\t * register values are reset back to their initial state.\n+\t * This is the DMA address for the qcaps output data array\n+\t * buffer. Array is of tf_rm_resc_req_entry type and is\n+\t * device specific.\n \t */\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)\n-\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \\\n-\t\tHWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP\n-\t/* unused. */\n-\tuint16_t\tunused1;\n+\tuint64_t\tqcaps_addr;\n } __rte_packed;\n \n-/* hwrm_tf_ext_em_op_output (size:128b/16B) */\n-struct hwrm_tf_ext_em_op_output {\n+/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */\n+struct hwrm_tf_session_resc_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38331,26 +40436,55 @@ struct hwrm_tf_ext_em_op_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Session reservation strategy. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \\\n+\t\t0\n+\t/* Static partitioning. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \\\n+\t\tUINT32_C(0x0)\n+\t/* Strategy 1. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \\\n+\t\tUINT32_C(0x1)\n+\t/* Strategy 2. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \\\n+\t\tUINT32_C(0x2)\n+\t/* Strategy 3. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3\n+\t/*\n+\t * Size of the returned qcaps_addr data array buffer. The\n+\t * value cannot exceed the size defined by the input msg,\n+\t * qcaps_size.\n+\t */\n+\tuint16_t\tsize;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint16_t\tunused0;\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_tf_ext_em_cfg *\n- **********************/\n+/******************************\n+ * hwrm_tf_session_resc_alloc *\n+ ******************************/\n \n \n-/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */\n-struct hwrm_tf_ext_em_cfg_input {\n+/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */\n+struct hwrm_tf_session_resc_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38379,65 +40513,42 @@ struct hwrm_tf_ext_em_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n-\tuint32_t\tflags;\n+\tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \\\n-\t\tUINT32_C(0x0)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX\n-\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x2)\n-\t/* When set to 1, secondary, 0 means primary. */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * Group_id which used by Firmware to identify memory pools belonging\n-\t * to certain group.\n+\t * Defines the array size of the provided req_addr and\n+\t * resv_addr array buffers. Should be set to the number of\n+\t * request entries.\n \t */\n-\tuint16_t\tgroup_id;\n+\tuint16_t\treq_size;\n \t/*\n-\t * Dynamically reconfigure EEM pending cache every 1/10th of second.\n-\t * If set to 0 it will disable the EEM HW flush of the pending cache.\n+\t * This is the DMA address for the request input data array\n+\t * buffer. Array is of tf_rm_resc_req_entry type. Size of the\n+\t * array buffer is provided by the 'req_size' field in this\n+\t * message.\n \t */\n-\tuint8_t\tflush_interval;\n-\t/* unused. */\n-\tuint8_t\tunused0;\n+\tuint64_t\treq_addr;\n \t/*\n-\t * Configured EXT EM with the given number of entries. All\n-\t * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the\n-\t * same number of entries and all tables will be configured\n-\t * using this value. Current minimum value is 32k. Current\n-\t * maximum value is 128M.\n+\t * This is the DMA address for the resc output data array\n+\t * buffer. Array is of tf_rm_resc_entry type. Size of the array\n+\t * buffer is provided by the 'req_size' field in this\n+\t * message.\n \t */\n-\tuint32_t\tnum_entries;\n-\t/* unused. */\n-\tuint32_t\tunused1;\n-\t/* Configured EXT EM with the given context if for KEY0 table. */\n-\tuint16_t\tkey0_ctx_id;\n-\t/* Configured EXT EM with the given context if for KEY1 table. */\n-\tuint16_t\tkey1_ctx_id;\n-\t/* Configured EXT EM with the given context if for RECORD table. */\n-\tuint16_t\trecord_ctx_id;\n-\t/* Configured EXT EM with the given context if for EFC table. */\n-\tuint16_t\tefc_ctx_id;\n-\t/* Configured EXT EM with the given context if for EFC table. */\n-\tuint16_t\tfid_ctx_id;\n-\t/* unused. */\n-\tuint16_t\tunused2;\n-\t/* unused. */\n-\tuint32_t\tunused3;\n+\tuint64_t\tresc_addr;\n } __rte_packed;\n \n-/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */\n-struct hwrm_tf_ext_em_cfg_output {\n+/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38446,26 +40557,33 @@ struct hwrm_tf_ext_em_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Size of the returned tf_rm_resc_entry data array. The value\n+\t * cannot exceed the req_size defined by the input msg. The data\n+\t * array is returned using the resv_addr specified DMA\n+\t * address also provided by the input msg.\n+\t */\n+\tuint16_t\tsize;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused0[5];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_tf_ext_em_qcfg *\n- ***********************/\n+/*****************************\n+ * hwrm_tf_session_resc_free *\n+ *****************************/\n \n \n-/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */\n-struct hwrm_tf_ext_em_qcfg_input {\n+/* hwrm_tf_session_resc_free_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38494,22 +40612,34 @@ struct hwrm_tf_ext_em_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n-\tuint32_t\tflags;\n+\tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-} __rte_packed;\n-\n-/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */\n-struct hwrm_tf_ext_em_qcfg_output {\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided free_addr\n+\t * buffer.\n+\t */\n+\tuint16_t\tfree_size;\n+\t/*\n+\t * This is the DMA address for the free input data array\n+\t * buffer. Array is of tf_rm_resc_entry type. Size of the\n+\t * buffer is provided by the 'free_size' field of this\n+\t * message.\n+\t */\n+\tuint64_t\tfree_addr;\n+} __rte_packed;\n+\n+/* hwrm_tf_session_resc_free_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38518,54 +40648,26 @@ struct hwrm_tf_ext_em_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \\\n-\t\tUINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \\\n-\t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX\n-\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x2)\n-\t/* The number of entries the FW has configured for EXT EM. */\n-\tuint32_t\tnum_entries;\n-\t/* Configured EXT EM with the given context if for KEY0 table. */\n-\tuint16_t\tkey0_ctx_id;\n-\t/* Configured EXT EM with the given context if for KEY1 table. */\n-\tuint16_t\tkey1_ctx_id;\n-\t/* Configured EXT EM with the given context if for RECORD table. */\n-\tuint16_t\trecord_ctx_id;\n-\t/* Configured EXT EM with the given context if for EFC table. */\n-\tuint16_t\tefc_ctx_id;\n-\t/* Configured EXT EM with the given context if for EFC table. */\n-\tuint16_t\tfid_ctx_id;\n \t/* unused. */\n-\tuint8_t\tunused0[5];\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_tf_em_insert *\n- *********************/\n+/******************************\n+ * hwrm_tf_session_resc_flush *\n+ ******************************/\n \n \n-/* hwrm_tf_em_insert_input (size:832b/104B) */\n-struct hwrm_tf_em_insert_input {\n+/* hwrm_tf_session_resc_flush_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_flush_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38594,34 +40696,34 @@ struct hwrm_tf_em_insert_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware Session Id. */\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n \tuint32_t\tfw_session_id;\n-\t/* Control Flags. */\n+\t/* Control flags. */\n \tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX\n-\t/* Reported match strength. */\n-\tuint16_t\tstrength;\n-\t/* Index to action. */\n-\tuint32_t\taction_ptr;\n-\t/* Index of EM record. */\n-\tuint32_t\tem_record_idx;\n-\t/* EM Key value. */\n-\tuint64_t\tem_key[8];\n-\t/* Number of bits in em_key. */\n-\tuint16_t\tem_key_bitlen;\n-\t/* unused. */\n-\tuint16_t\tunused0[3];\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided flush_addr\n+\t * buffer.\n+\t */\n+\tuint16_t\tflush_size;\n+\t/*\n+\t * This is the DMA address for the flush input data array\n+\t * buffer. Array of tf_rm_resc_entry type. Size of the\n+\t * buffer is provided by the 'flush_size' field in this\n+\t * message.\n+\t */\n+\tuint64_t\tflush_addr;\n } __rte_packed;\n \n-/* hwrm_tf_em_insert_output (size:128b/16B) */\n-struct hwrm_tf_em_insert_output {\n+/* hwrm_tf_session_resc_flush_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_flush_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38630,23 +40732,48 @@ struct hwrm_tf_em_insert_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* EM record pointer index. */\n-\tuint16_t\trptr_index;\n-\t/* EM record offset 0~3. */\n-\tuint8_t\trptr_entry;\n-\t/* Number of word entries consumed by the key. */\n-\tuint8_t\tnum_of_entries;\n \t/* unused. */\n-\tuint32_t\tunused0;\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_tf_em_delete *\n- *********************/\n+/* TruFlow RM capability of a resource. */\n+/* tf_rm_resc_req_entry (size:64b/8B) */\n+struct tf_rm_resc_req_entry {\n+\t/* Type of the resource, defined globally in HCAPI RM. */\n+\tuint32_t\ttype;\n+\t/* Minimum value. */\n+\tuint16_t\tmin;\n+\t/* Maximum value. */\n+\tuint16_t\tmax;\n+} __rte_packed;\n \n+/* TruFlow RM reservation information. */\n+/* tf_rm_resc_entry (size:64b/8B) */\n+struct tf_rm_resc_entry {\n+\t/* Type of the resource, defined globally in HCAPI RM. */\n+\tuint32_t\ttype;\n+\t/* Start offset. */\n+\tuint16_t\tstart;\n+\t/* Number of resources. */\n+\tuint16_t\tstride;\n+} __rte_packed;\n \n-/* hwrm_tf_em_delete_input (size:832b/104B) */\n-struct hwrm_tf_em_delete_input {\n+/************************\n+ * hwrm_tf_tbl_type_get *\n+ ************************/\n+\n+\n+/* hwrm_tf_tbl_type_get_input (size:256b/32B) */\n+struct hwrm_tf_tbl_type_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38675,32 +40802,31 @@ struct hwrm_tf_em_delete_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Session Id. */\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n \tuint32_t\tfw_session_id;\n \t/* Control flags. */\n \tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX\n-\t/* Unused0 */\n-\tuint16_t\tunused0;\n-\t/* EM internal flow hanndle. */\n-\tuint64_t\tflow_handle;\n-\t/* EM Key value */\n-\tuint64_t\tem_key[8];\n-\t/* Number of bits in em_key. */\n-\tuint16_t\tem_key_bitlen;\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX\n \t/* unused. */\n-\tuint16_t\tunused1[3];\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n } __rte_packed;\n \n-/* hwrm_tf_em_delete_output (size:128b/16B) */\n-struct hwrm_tf_em_delete_output {\n+/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */\n+struct hwrm_tf_tbl_type_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38709,19 +40835,34 @@ struct hwrm_tf_em_delete_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Original stack allocation index. */\n-\tuint16_t\tem_index;\n-\t/* unused. */\n-\tuint16_t\tunused0[3];\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint16_t\tunused0;\n+\t/* Response data. */\n+\tuint8_t\tdata[128];\n+\t/* unused */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __rte_packed;\n \n-/********************\n- * hwrm_tf_tcam_set *\n- ********************/\n+/************************\n+ * hwrm_tf_tbl_type_set *\n+ ************************/\n \n \n-/* hwrm_tf_tcam_set_input (size:1024b/128B) */\n-struct hwrm_tf_tcam_set_input {\n+/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */\n+struct hwrm_tf_tbl_type_set_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38753,49 +40894,34 @@ struct hwrm_tf_tcam_set_input {\n \t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n \tuint32_t\tfw_session_id;\n \t/* Control flags. */\n-\tuint32_t\tflags;\n+\tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * Indicate device data is being sent via DMA, the device\n-\t * data is packing does not change.\n-\t */\n-\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n \t/*\n-\t * TCAM type of the resource, defined globally in the\n+\t * Type of the resource, defined globally in the\n \t * hwrm_tf_resc_type enum.\n \t */\n \tuint32_t\ttype;\n-\t/* Index of TCAM entry. */\n-\tuint16_t\tidx;\n-\t/* Number of bytes in the TCAM key. */\n-\tuint8_t\tkey_size;\n-\t/* Number of bytes in the TCAM result. */\n-\tuint8_t\tresult_size;\n-\t/*\n-\t * Offset from which the mask bytes start in the device data\n-\t * array, key offset is always 0.\n-\t */\n-\tuint8_t\tmask_offset;\n-\t/* Offset from which the result bytes start in the device data array. */\n-\tuint8_t\tresult_offset;\n-\t/* unused. */\n-\tuint8_t\tunused0[6];\n-\t/*\n-\t * TCAM key located at offset 0, mask located at mask_offsec\n-\t * and result at result_offsec for the device.\n-\t */\n-\tuint8_t\tdev_data[88];\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused1[6];\n+\t/* Data to be set. */\n+\tuint8_t\tdata[88];\n } __rte_packed;\n \n-/* hwrm_tf_tcam_set_output (size:128b/16B) */\n-struct hwrm_tf_tcam_set_output {\n+/* hwrm_tf_tbl_type_set_output (size:128b/16B) */\n+struct hwrm_tf_tbl_type_set_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38807,23 +40933,23 @@ struct hwrm_tf_tcam_set_output {\n \t/* unused. */\n \tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the\n-\t * output is completely written to RAM. This field should be\n-\t * read as '1' to indicate that the output has been\n-\t * completely written. When writing a command completion or\n-\t * response to an internal processor, the order of writes has\n-\t * to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/********************\n- * hwrm_tf_tcam_get *\n- ********************/\n+/**************************\n+ * hwrm_tf_ctxt_mem_alloc *\n+ **************************/\n \n \n-/* hwrm_tf_tcam_get_input (size:256b/32B) */\n-struct hwrm_tf_tcam_get_input {\n+/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */\n+struct hwrm_tf_ctxt_mem_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38852,31 +40978,14 @@ struct hwrm_tf_tcam_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * TCAM type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n-\tuint32_t\ttype;\n-\t/* Index of a TCAM entry. */\n-\tuint16_t\tidx;\n+\t/* Size in KB of memory to be allocated. */\n+\tuint32_t\tmem_size;\n \t/* unused. */\n-\tuint16_t\tunused0;\n+\tuint32_t\tunused0;\n } __rte_packed;\n \n-/* hwrm_tf_tcam_get_output (size:2368b/296B) */\n-struct hwrm_tf_tcam_get_output {\n+/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */\n+struct hwrm_tf_ctxt_mem_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38885,23 +40994,49 @@ struct hwrm_tf_tcam_get_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of bytes in the TCAM key. */\n-\tuint8_t\tkey_size;\n-\t/* Number of bytes in the TCAM entry. */\n-\tuint8_t\tresult_size;\n-\t/* Offset from which the mask bytes start in the device data array. */\n-\tuint8_t\tmask_offset;\n-\t/* Offset from which the result bytes start in the device data array. */\n-\tuint8_t\tresult_offset;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n \t/*\n-\t * TCAM key located at offset 0, mask located at mask_offsec\n-\t * and result at result_offsec for the device.\n+\t * PBL pointer points to PDE table with each entry pointing\n+\t * to PTE tables.\n \t */\n-\tuint8_t\tdev_data[272];\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 128KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)\n+\t/* 256KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 512KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)\n+\t/* 1MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 8MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)\n+\t/* 1GB page size. */\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G\n \t/* unused. */\n-\tuint8_t\tunused1[7];\n+\tuint8_t\tunused0[5];\n \t/*\n \t * This field is used in Output records to indicate that the\n \t * output is completely written to RAM. This field should be\n@@ -38913,13 +41048,13 @@ struct hwrm_tf_tcam_get_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_tf_tcam_move *\n- *********************/\n+/*************************\n+ * hwrm_tf_ctxt_mem_free *\n+ *************************/\n \n \n-/* hwrm_tf_tcam_move_input (size:1024b/128B) */\n-struct hwrm_tf_tcam_move_input {\n+/* hwrm_tf_ctxt_mem_free_input (size:256b/32B) */\n+struct hwrm_tf_ctxt_mem_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -38948,33 +41083,53 @@ struct hwrm_tf_tcam_move_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n \t/*\n-\t * TCAM type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n+\t * PBL pointer points to PDE table with each entry pointing\n+\t * to PTE tables.\n \t */\n-\tuint32_t\ttype;\n-\t/* Number of TCAM index pairs to be swapped for the device. */\n-\tuint16_t\tcount;\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 128KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)\n+\t/* 256KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 512KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)\n+\t/* 1MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 8MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)\n+\t/* 1GB page size. */\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G\n \t/* unused. */\n-\tuint16_t\tunused0;\n-\t/* TCAM index pairs to be swapped for the device. */\n-\tuint16_t\tidx_pairs[48];\n+\tuint8_t\tunused0[6];\n } __rte_packed;\n \n-/* hwrm_tf_tcam_move_output (size:128b/16B) */\n-struct hwrm_tf_tcam_move_output {\n+/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */\n+struct hwrm_tf_ctxt_mem_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38996,13 +41151,13 @@ struct hwrm_tf_tcam_move_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_tf_tcam_free *\n- *********************/\n+/*************************\n+ * hwrm_tf_ctxt_mem_rgtr *\n+ *************************/\n \n \n-/* hwrm_tf_tcam_free_input (size:1024b/128B) */\n-struct hwrm_tf_tcam_free_input {\n+/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */\n+struct hwrm_tf_ctxt_mem_rgtr_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39031,33 +41186,55 @@ struct hwrm_tf_tcam_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n \t/*\n-\t * TCAM type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n+\t * PBL pointer points to PDE table with each entry pointing\n+\t * to PTE tables.\n \t */\n-\tuint32_t\ttype;\n-\t/* Number of TCAM index to be deleted for the device. */\n-\tuint16_t\tcount;\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 128KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)\n+\t/* 256KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 512KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)\n+\t/* 1MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 8MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)\n+\t/* 1GB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G\n \t/* unused. */\n-\tuint16_t\tunused0;\n-\t/* TCAM index list to be deleted for the device. */\n-\tuint16_t\tidx_list[48];\n+\tuint32_t\tunused0;\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n } __rte_packed;\n \n-/* hwrm_tf_tcam_free_output (size:128b/16B) */\n-struct hwrm_tf_tcam_free_output {\n+/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */\n+struct hwrm_tf_ctxt_mem_rgtr_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39066,8 +41243,13 @@ struct hwrm_tf_tcam_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This\n+\t * handle is passed to the TF session.\n+\t */\n+\tuint16_t\tctx_id;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused0[5];\n \t/*\n \t * This field is used in Output records to indicate that the\n \t * output is completely written to RAM. This field should be\n@@ -39079,13 +41261,13 @@ struct hwrm_tf_tcam_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_tf_global_cfg_set *\n- **************************/\n+/***************************\n+ * hwrm_tf_ctxt_mem_unrgtr *\n+ ***************************/\n \n \n-/* hwrm_tf_global_cfg_set_input (size:448b/56B) */\n-struct hwrm_tf_global_cfg_set_input {\n+/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */\n+struct hwrm_tf_ctxt_mem_unrgtr_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39114,34 +41296,17 @@ struct hwrm_tf_global_cfg_set_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint32_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX\n-\t/* Global Cfg type */\n-\tuint32_t\ttype;\n-\t/* Offset of the type */\n-\tuint32_t\toffset;\n-\t/* Size of the data to set in bytes */\n-\tuint16_t\tsize;\n-\t/* unused. */\n-\tuint8_t\tunused0[6];\n-\t/* Data to set */\n-\tuint8_t\tdata[8];\n-\t/* Mask of data to set, 0 indicates no mask */\n-\tuint8_t\tmask[8];\n+\t/*\n+\t * Id/Handle to the recently register context memory. This\n+\t * handle is passed to the TF session.\n+\t */\n+\tuint16_t\tctx_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n } __rte_packed;\n \n-/* hwrm_tf_global_cfg_set_output (size:128b/16B) */\n-struct hwrm_tf_global_cfg_set_output {\n+/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */\n+struct hwrm_tf_ctxt_mem_unrgtr_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39163,13 +41328,13 @@ struct hwrm_tf_global_cfg_set_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_tf_global_cfg_get *\n- **************************/\n+/************************\n+ * hwrm_tf_ext_em_qcaps *\n+ ************************/\n \n \n-/* hwrm_tf_global_cfg_get_input (size:320b/40B) */\n-struct hwrm_tf_global_cfg_get_input {\n+/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39198,30 +41363,28 @@ struct hwrm_tf_global_cfg_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n \tuint32_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX\n-\t/* Global Cfg type */\n-\tuint32_t\ttype;\n-\t/* Offset of the type */\n-\tuint32_t\toffset;\n-\t/* Size of the data to set in bytes */\n-\tuint16_t\tsize;\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n \t/* unused. */\n-\tuint8_t\tunused0[6];\n+\tuint32_t\tunused0;\n } __rte_packed;\n \n-/* hwrm_tf_global_cfg_get_output (size:256b/32B) */\n-struct hwrm_tf_global_cfg_get_output {\n+/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */\n+struct hwrm_tf_ext_em_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39230,21 +41393,133 @@ struct hwrm_tf_global_cfg_get_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Size of the data read in bytes */\n-\tuint16_t\tsize;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Centralized\n+\t * Memory Model. The concept designates one entity for the\n+\t * memory allocation while all others ‘subscribe’ to it.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Detached\n+\t * Centralized Memory Model. The memory is allocated and managed\n+\t * as a separate entity. All PFs and VFs will be granted direct\n+\t * or semi-direct access to the allocated memory while none of\n+\t * which can interfere with the management of the memory.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, indicates FW support for host based EEM memory. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/* When set to 1, indicates FW support for on-chip based EEM memory. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n \t/* unused. */\n-\tuint8_t\tunused0[6];\n-\t/* Data to set */\n-\tuint8_t\tdata[16];\n+\tuint32_t\tunused0;\n+\t/* Support flags. */\n+\tuint32_t\tsupported;\n+\t/*\n+\t * If set to 1, then EXT EM KEY0 table is supported using\n+\t * crc32 hash.\n+\t * If set to 0, EXT EM KEY0 table is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, then EXT EM KEY1 table is supported using\n+\t * lookup3 hash.\n+\t * If set to 0, EXT EM KEY1 table is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, then EXT EM External Record table is supported.\n+\t * If set to 0, EXT EM External Record table is not\n+\t * supported. (This table includes action record, EFC\n+\t * pointers, encap pointers)\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then EXT EM External Flow Counters table is\n+\t * supported.\n+\t * If set to 0, EXT EM External Flow Counters table is not\n+\t * supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, then FID table used for implicit flow flush\n+\t * is supported.\n+\t * If set to 0, then FID table used for implicit flow flush\n+\t * is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * If set to 1, then table scopes are supported.\n+\t * If set to 0, then table scopes are not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * The maximum number of entries supported by EXT EM. When\n+\t * configuring the host memory the number of numbers of\n+\t * entries that can supported are -\n+\t * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,\n+\t * 128M entries.\n+\t * Any value that are not these values, the FW will round\n+\t * down to the closest support number of entries.\n+\t */\n+\tuint32_t\tmax_entries_supported;\n+\t/*\n+\t * The entry size in bytes of each entry in the EXT EM\n+\t * KEY0/KEY1 tables.\n+\t */\n+\tuint16_t\tkey_entry_size;\n+\t/*\n+\t * The entry size in bytes of each entry in the EXT EM RECORD\n+\t * tables.\n+\t */\n+\tuint16_t\trecord_entry_size;\n+\t/* The entry size in bytes of each entry in the EXT EM EFC tables. */\n+\tuint16_t\tefc_entry_size;\n+\t/* The FID size in bytes of each entry in the EXT EM FID tables. */\n+\tuint16_t\tfid_entry_size;\n+\t/* Maximum number of ctxt mem allocations allowed. */\n+\tuint32_t\tmax_ctxt_mem_allocs;\n+\t/*\n+\t * Maximum number of static buckets that can be assigned to lookup\n+\t * table scopes.\n+\t */\n+\tuint32_t\tmax_static_buckets;\n+\t/*\n+\t * Maximum number of all (static and dynamic) buckets that can\n+\t * be assigned to lookup table scopes.\n+\t */\n+\tuint32_t\tmax_total_buckets;\n+\t/* unused. */\n+\tuint8_t\tunused1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_tf_if_tbl_get *\n- **********************/\n+/*********************\n+ * hwrm_tf_ext_em_op *\n+ *********************/\n \n \n-/* hwrm_tf_if_tbl_get_input (size:256b/32B) */\n-struct hwrm_tf_if_tbl_get_input {\n+/* hwrm_tf_ext_em_op_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_op_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39273,31 +41548,51 @@ struct hwrm_tf_if_tbl_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n \tuint16_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX\n-\t/* Size of the data to set. */\n-\tuint16_t\tsize;\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* The number of EXT EM key table entries to be configured. */\n+\tuint16_t\top;\n+\t/* This value is reserved and should not be used. */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)\n \t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n+\t * To properly stop EXT EM and ensure there are no DMA's,\n+\t * the caller must disable EXT EM for the given PF, using\n+\t * this call. This will safely disable EXT EM and ensure\n+\t * that all DMA'ed to the keys/records/efc have been\n+\t * completed.\n \t */\n-\tuint32_t\ttype;\n-\t/* Index of the type to retrieve. */\n-\tuint32_t\tindex;\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)\n+\t/*\n+\t * Once the EXT EM host memory has been configured, EXT EM\n+\t * options have been configured. Then the caller should\n+\t * enable EXT EM for the given PF. Note once this call has\n+\t * been made, then the EXT EM mechanism will be active and\n+\t * DMA's will occur as packets are processed.\n+\t */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)\n+\t/*\n+\t * Clear EXT EM settings for the given PF so that the\n+\t * register values are reset back to their initial state.\n+\t */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \\\n+\t\tHWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP\n+\t/* unused. */\n+\tuint16_t\tunused1;\n } __rte_packed;\n \n-/* hwrm_tf_if_tbl_get_output (size:256b/32B) */\n-struct hwrm_tf_if_tbl_get_output {\n+/* hwrm_tf_ext_em_op_output (size:128b/16B) */\n+struct hwrm_tf_ext_em_op_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39306,34 +41601,26 @@ struct hwrm_tf_if_tbl_get_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Response code. */\n-\tuint32_t\tresp_code;\n-\t/* Response size. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint16_t\tunused0;\n-\t/* Response data. */\n-\tuint8_t\tdata[8];\n-\t/* unused */\n-\tuint8_t\tunused1[7];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_tf_if_tbl_type_set *\n- ***************************/\n+/**********************\n+ * hwrm_tf_ext_em_cfg *\n+ **********************/\n \n \n-/* hwrm_tf_if_tbl_set_input (size:384b/48B) */\n-struct hwrm_tf_if_tbl_set_input {\n+/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */\n+struct hwrm_tf_ext_em_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39362,37 +41649,163 @@ struct hwrm_tf_if_tbl_set_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n \t/* Control flags. */\n-\tuint16_t\tflags;\n+\tuint32_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates that tx flow. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, secondary, 0 means primary. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Group_id which used by Firmware to identify memory pools belonging\n+\t * to certain group.\n+\t */\n+\tuint16_t\tgroup_id;\n+\t/*\n+\t * Dynamically reconfigure EEM pending cache every 1/10th of second.\n+\t * If set to 0 it will disable the EEM HW flush of the pending cache.\n+\t */\n+\tuint8_t\tflush_interval;\n \t/* unused. */\n-\tuint8_t\tunused0[2];\n+\tuint8_t\tunused0;\n \t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n+\t * Configured EXT EM with the given number of entries. All\n+\t * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the\n+\t * same number of entries and all tables will be configured\n+\t * using this value. Current minimum value is 32k. Current\n+\t * maximum value is 128M.\n \t */\n-\tuint32_t\ttype;\n-\t/* Index of the type to set. */\n-\tuint32_t\tindex;\n-\t/* Size of the data to set. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint8_t\tunused1[6];\n-\t/* Data to be set. */\n-\tuint8_t\tdata[8];\n+\tuint32_t\tnum_entries;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the group_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the flush_interval field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the num_entries field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the key0_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the key1_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the record_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the efc_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the fid_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the action_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the action_tbl_scope field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the lkup_ctx_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the lkup_tbl_scope field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the lkup_static_buckets field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the lkup_dynamic_buckets field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_DYNAMIC_BUCKETS \\\n+\t\tUINT32_C(0x2000)\n+\t/* Configured EXT EM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EXT EM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EXT EM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\t/* Context id of action table scope. */\n+\tuint16_t\taction_ctx_id;\n+\t/* Table scope id used for action record entries. */\n+\tuint16_t\taction_tbl_scope;\n+\t/* Context id of lookup table scope. */\n+\tuint16_t\tlkup_ctx_id;\n+\t/* Table scope id used for EM lookup entries. */\n+\tuint16_t\tlkup_tbl_scope;\n+\t/* unused. */\n+\tuint16_t\tunused1;\n+\t/*\n+\t * Number of 32B static buckets to be allocated at the beginning\n+\t * of table scope.\n+\t */\n+\tuint32_t\tlkup_static_buckets;\n+\t/* Number of 32B dynamic buckets to be allocated. */\n+\tuint32_t\tlkup_dynamic_buckets;\n+\t/* unused. */\n+\tuint32_t\tunused2;\n } __rte_packed;\n \n-/* hwrm_tf_if_tbl_set_output (size:128b/16B) */\n-struct hwrm_tf_if_tbl_set_output {\n+/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */\n+struct hwrm_tf_ext_em_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39404,23 +41817,23 @@ struct hwrm_tf_if_tbl_set_output {\n \t/* unused. */\n \tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tunnel_dst_port_query *\n- ******************************/\n+/***********************\n+ * hwrm_tf_ext_em_qcfg *\n+ ***********************/\n \n \n-/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_query_input {\n+/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39449,33 +41862,22 @@ struct hwrm_tunnel_dst_port_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Use fixed layer 2 ether type of 0xFFFF */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n-\t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n-\t\tUINT32_C(0xc)\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n-\tuint8_t\tunused_0[7];\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint32_t\tunused0;\n } __rte_packed;\n \n-/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_query_output {\n+/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */\n+struct hwrm_tf_ext_em_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39484,42 +41886,123 @@ struct hwrm_tunnel_dst_port_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n+\t/* The number of entries the FW has configured for EXT EM. */\n+\tuint32_t\tnum_entries;\n+\t/* Configured EXT EM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EXT EM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EXT EM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\tuint32_t\tsupported;\n+\t/* This bit must be '1' for the group_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \\\n+\t\tUINT32_C(0x1)\n+\t/* This bit must be '1' for the flush_interval field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \\\n+\t\tUINT32_C(0x2)\n+\t/* This bit must be '1' for the num_entries field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \\\n+\t\tUINT32_C(0x4)\n+\t/* This bit must be '1' for the key0_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \\\n+\t\tUINT32_C(0x8)\n+\t/* This bit must be '1' for the key1_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \\\n+\t\tUINT32_C(0x10)\n+\t/* This bit must be '1' for the record_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \\\n+\t\tUINT32_C(0x20)\n+\t/* This bit must be '1' for the efc_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \\\n+\t\tUINT32_C(0x40)\n+\t/* This bit must be '1' for the fid_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \\\n+\t\tUINT32_C(0x80)\n+\t/* This bit must be '1' for the action_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \\\n+\t\tUINT32_C(0x100)\n+\t/* This bit must be '1' for the action_tbl_scope field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \\\n+\t\tUINT32_C(0x200)\n+\t/* This bit must be '1' for the lkup_ctx_id field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \\\n+\t\tUINT32_C(0x400)\n+\t/* This bit must be '1' for the lkup_tbl_scope field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \\\n+\t\tUINT32_C(0x800)\n+\t/* This bit must be '1' for the lkup_static_buckets field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \\\n+\t\tUINT32_C(0x1000)\n+\t/* This bit must be '1' for the lkup_dynamic_buckets field is set. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_DYNAMIC_BUCKETS \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * This field represents the identifier of L4 destination port\n-\t * used for the given tunnel type. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n+\t * Group id is used by firmware to identify memory pools belonging\n+\t * to certain group.\n \t */\n-\tuint16_t\ttunnel_dst_port_id;\n+\tuint16_t\tgroup_id;\n+\t/* EEM pending cache flush interval in 1/10th of second. */\n+\tuint8_t\tflush_interval;\n+\t/* unused. */\n+\tuint8_t\tunused1;\n+\t/* Context id of action table scope. */\n+\tuint16_t\taction_ctx_id;\n+\t/* Table scope id used for action record entries. */\n+\tuint16_t\taction_tbl_scope;\n+\t/* Context id of lookup table scope. */\n+\tuint16_t\tlkup_ctx_id;\n+\t/* Table scope id used for EM lookup entries. */\n+\tuint16_t\tlkup_tbl_scope;\n+\t/*\n+\t * Number of 32B static buckets to be allocated at the beginning\n+\t * of table scope.\n+\t */\n+\tuint32_t\tlkup_static_buckets;\n+\t/* Number of 32B dynamic buckets to be allocated. */\n+\tuint32_t\tlkup_dynamic_buckets;\n+\t/* unused. */\n+\tuint8_t\tunused2[3];\n \t/*\n-\t * This field represents the value of L4 destination port\n-\t * identified by tunnel_dst_port_id. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n-\t * This field is in network byte order.\n-\t *\n-\t * A value of 0 means that the destination port is not\n-\t * configured.\n-\t */\n-\tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_0[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_tunnel_dst_port_alloc *\n- ******************************/\n+/*********************\n+ * hwrm_tf_em_insert *\n+ *********************/\n \n \n-/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_alloc_input {\n+/* hwrm_tf_em_insert_input (size:832b/104B) */\n+struct hwrm_tf_em_insert_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39548,45 +42031,34 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Use fixed layer 2 ether type of 0xFFFF */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n-\t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n-\t\tUINT32_C(0xc)\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * This field represents the value of L4 destination port used\n-\t * for the given tunnel type. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n-\t *\n-\t * This field is in network byte order.\n-\t *\n-\t * A value of 0 shall fail the command.\n-\t */\n-\tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_1[4];\n+\t/* Firmware Session Id. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control Flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX\n+\t/* Reported match strength. */\n+\tuint16_t\tstrength;\n+\t/* Index to action. */\n+\tuint32_t\taction_ptr;\n+\t/* Index of EM record. */\n+\tuint32_t\tem_record_idx;\n+\t/* EM Key value. */\n+\tuint64_t\tem_key[8];\n+\t/* Number of bits in em_key. */\n+\tuint16_t\tem_key_bitlen;\n+\t/* unused. */\n+\tuint16_t\tunused0[3];\n } __rte_packed;\n \n-/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_alloc_output {\n+/* hwrm_tf_em_insert_output (size:128b/16B) */\n+struct hwrm_tf_em_insert_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39595,29 +42067,23 @@ struct hwrm_tunnel_dst_port_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n-\t * types that has l4 destination port parameters.\n-\t */\n-\tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_0[5];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n+\t/* EM record pointer index. */\n+\tuint16_t\trptr_index;\n+\t/* EM record offset 0~3. */\n+\tuint8_t\trptr_entry;\n+\t/* Number of word entries consumed by the key. */\n+\tuint8_t\tnum_of_entries;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n } __rte_packed;\n \n-/*****************************\n- * hwrm_tunnel_dst_port_free *\n- *****************************/\n+/*********************\n+ * hwrm_tf_em_delete *\n+ *********************/\n \n \n-/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_free_input {\n+/* hwrm_tf_em_delete_input (size:832b/104B) */\n+struct hwrm_tf_em_delete_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39646,39 +42112,32 @@ struct hwrm_tunnel_dst_port_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Use fixed layer 2 ether type of 0xFFFF */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n-\t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n-\t\tUINT32_C(0xc)\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n-\t * types that has l4 destination port parameters.\n-\t */\n-\tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_1[4];\n+\t/* Session Id. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX\n+\t/* Unused0 */\n+\tuint16_t\tunused0;\n+\t/* EM internal flow hanndle. */\n+\tuint64_t\tflow_handle;\n+\t/* EM Key value */\n+\tuint64_t\tem_key[8];\n+\t/* Number of bits in em_key. */\n+\tuint16_t\tem_key_bitlen;\n+\t/* unused. */\n+\tuint16_t\tunused1[3];\n } __rte_packed;\n \n-/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_free_output {\n+/* hwrm_tf_em_delete_output (size:128b/16B) */\n+struct hwrm_tf_em_delete_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39687,166 +42146,19 @@ struct hwrm_tunnel_dst_port_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_1[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/* Periodic statistics context DMA to host. */\n-/* ctx_hw_stats (size:1280b/160B) */\n-struct ctx_hw_stats {\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on receive path */\n-\tuint64_t\trx_discard_pkts;\n-\t/* Number of packets on receive path with error */\n-\tuint64_t\trx_error_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of packets on transmit path with error */\n-\tuint64_t\ttx_error_pkts;\n-\t/* Number of discarded packets on transmit path */\n-\tuint64_t\ttx_discard_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of TPA packets */\n-\tuint64_t\ttpa_pkts;\n-\t/* Number of TPA bytes */\n-\tuint64_t\ttpa_bytes;\n-\t/* Number of TPA events */\n-\tuint64_t\ttpa_events;\n-\t/* Number of TPA aborts */\n-\tuint64_t\ttpa_aborts;\n-} __rte_packed;\n-\n-/*\n- * Extended periodic statistics context DMA to host. On cards that\n- * support TPA v2, additional TPA related stats exist and can be retrieved\n- * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.\n- */\n-/* ctx_hw_stats_ext (size:1344b/168B) */\n-struct ctx_hw_stats_ext {\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on receive path */\n-\tuint64_t\trx_discard_pkts;\n-\t/* Number of packets on receive path with error */\n-\tuint64_t\trx_error_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of packets on transmit path with error */\n-\tuint64_t\ttx_error_pkts;\n-\t/* Number of discarded packets on transmit path */\n-\tuint64_t\ttx_discard_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of TPA eligible packets */\n-\tuint64_t\trx_tpa_eligible_pkt;\n-\t/* Number of TPA eligible bytes */\n-\tuint64_t\trx_tpa_eligible_bytes;\n-\t/* Number of TPA packets */\n-\tuint64_t\trx_tpa_pkt;\n-\t/* Number of TPA bytes */\n-\tuint64_t\trx_tpa_bytes;\n-\t/* Number of TPA errors */\n-\tuint64_t\trx_tpa_errors;\n-} __rte_packed;\n-\n-/* Periodic Engine statistics context DMA to host. */\n-/* ctx_eng_stats (size:512b/64B) */\n-struct ctx_eng_stats {\n-\t/*\n-\t * Count of data bytes into the Engine.\n-\t * This includes any user supplied prefix,\n-\t * but does not include any predefined\n-\t * prefix data.\n-\t */\n-\tuint64_t\teng_bytes_in;\n-\t/* Count of data bytes out of the Engine. */\n-\tuint64_t\teng_bytes_out;\n-\t/*\n-\t * Count, in 4-byte (dword) units, of bytes\n-\t * that are input as auxiliary data.\n-\t * This includes the aux_cmd data.\n-\t */\n-\tuint64_t\taux_bytes_in;\n-\t/*\n-\t * Count, in 4-byte (dword) units, of bytes\n-\t * that are output as auxiliary data.\n-\t * This count is the buffer space for aux_data\n-\t * output provided in the RQE, not the actual\n-\t * aux_data written\n-\t */\n-\tuint64_t\taux_bytes_out;\n-\t/* Count of number of commands executed. */\n-\tuint64_t\tcommands;\n-\t/*\n-\t * Count of number of error commands.\n-\t * These are the commands with a\n-\t * non-zero status value.\n-\t */\n-\tuint64_t\terror_commands;\n-\t/*\n-\t * Compression/Encryption Engine usage,\n-\t * the unit is count of clock cycles\n-\t */\n-\tuint64_t\tcce_engine_usage;\n-\t/*\n-\t * De-Compression/De-cryption Engine usage,\n-\t * the unit is count of clock cycles\n-\t */\n-\tuint64_t\tcdd_engine_usage;\n+\t/* Original stack allocation index. */\n+\tuint16_t\tem_index;\n+\t/* unused. */\n+\tuint16_t\tunused0[3];\n } __rte_packed;\n \n-/***********************\n- * hwrm_stat_ctx_alloc *\n- ***********************/\n+/********************\n+ * hwrm_tf_tcam_set *\n+ ********************/\n \n \n-/* hwrm_stat_ctx_alloc_input (size:256b/32B) */\n-struct hwrm_stat_ctx_alloc_input {\n+/* hwrm_tf_tcam_set_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_set_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39875,51 +42187,52 @@ struct hwrm_stat_ctx_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * This is the address for statistic block.\n-\t * > For new versions of the chip, this address should be 128B\n-\t * > aligned.\n-\t */\n-\tuint64_t\tstats_dma_addr;\n-\t/*\n-\t * The statistic block update period in ms.\n-\t * e.g. 250ms, 500ms, 750ms, 1000ms.\n-\t * If update_period_ms is 0, then the stats update\n-\t * shall be never done and the DMA address shall not be used.\n-\t * In this case, the stat block can only be read by\n-\t * hwrm_stat_ctx_query command.\n-\t * On Ethernet/L2 based devices:\n-\t * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),\n-\t * ctx_hw_stats_ext is used for DMA,\n-\t * else\n-\t * ctx_hw_stats is used for DMA.\n+\t * Indicate device data is being sent via DMA, the device\n+\t * data is packing does not change.\n \t */\n-\tuint32_t\tupdate_period_ms;\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n \t/*\n-\t * This field is used to specify statistics context specific\n-\t * configuration flags.\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\tuint8_t\tstat_ctx_flags;\n+\tuint32_t\ttype;\n+\t/* Index of TCAM entry. */\n+\tuint16_t\tidx;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint8_t\tkey_size;\n+\t/* Number of bytes in the TCAM result. */\n+\tuint8_t\tresult_size;\n \t/*\n-\t * When this bit is set to '1', the statistics context shall be\n-\t * allocated for RoCE traffic only. In this case, traffic other\n-\t * than offloaded RoCE traffic shall not be included in this\n-\t * statistic context.\n-\t * When this bit is set to '0', the statistics context shall be\n-\t * used for network traffic or engine traffic.\n+\t * Offset from which the mask bytes start in the device data\n+\t * array, key offset is always 0.\n \t */\n-\t#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)\n-\tuint8_t\tunused_0;\n+\tuint8_t\tmask_offset;\n+\t/* Offset from which the result bytes start in the device data array. */\n+\tuint8_t\tresult_offset;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n \t/*\n-\t * This is the size of the structure (ctx_hw_stats or\n-\t * ctx_hw_stats_ext) that the driver has allocated to be used\n-\t * for the periodic DMA updates.\n+\t * TCAM key located at offset 0, mask located at mask_offsec\n+\t * and result at result_offsec for the device.\n \t */\n-\tuint16_t\tstats_dma_length;\n+\tuint8_t\tdev_data[88];\n } __rte_packed;\n \n-/* hwrm_stat_ctx_alloc_output (size:128b/16B) */\n-struct hwrm_stat_ctx_alloc_output {\n+/* hwrm_tf_tcam_set_output (size:128b/16B) */\n+struct hwrm_tf_tcam_set_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39928,26 +42241,26 @@ struct hwrm_stat_ctx_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This is the statistics context ID value. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[3];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_stat_ctx_free *\n- **********************/\n+/********************\n+ * hwrm_tf_tcam_get *\n+ ********************/\n \n \n-/* hwrm_stat_ctx_free_input (size:192b/24B) */\n-struct hwrm_stat_ctx_free_input {\n+/* hwrm_tf_tcam_get_input (size:256b/32B) */\n+struct hwrm_tf_tcam_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -39976,13 +42289,31 @@ struct hwrm_stat_ctx_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of a TCAM entry. */\n+\tuint16_t\tidx;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n } __rte_packed;\n \n-/* hwrm_stat_ctx_free_output (size:128b/16B) */\n-struct hwrm_stat_ctx_free_output {\n+/* hwrm_tf_tcam_get_output (size:2368b/296B) */\n+struct hwrm_tf_tcam_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -39991,26 +42322,41 @@ struct hwrm_stat_ctx_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This is the statistics context ID value. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[3];\n+\t/* Number of bytes in the TCAM key. */\n+\tuint8_t\tkey_size;\n+\t/* Number of bytes in the TCAM entry. */\n+\tuint8_t\tresult_size;\n+\t/* Offset from which the mask bytes start in the device data array. */\n+\tuint8_t\tmask_offset;\n+\t/* Offset from which the result bytes start in the device data array. */\n+\tuint8_t\tresult_offset;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * TCAM key located at offset 0, mask located at mask_offsec\n+\t * and result at result_offsec for the device.\n+\t */\n+\tuint8_t\tdev_data[272];\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_stat_ctx_query *\n- ***********************/\n+/*********************\n+ * hwrm_tf_tcam_move *\n+ *********************/\n \n \n-/* hwrm_stat_ctx_query_input (size:192b/24B) */\n-struct hwrm_stat_ctx_query_input {\n+/* hwrm_tf_tcam_move_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_move_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40039,20 +42385,33 @@ struct hwrm_stat_ctx_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tflags;\n-\t/*\n-\t * This bit is set to 1 when request is for a counter mask,\n-\t * representing the width of each of the stats counters, rather\n-\t * than counters themselves.\n-\t */\n-\t#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n-\tuint8_t\tunused_0[3];\n-} __rte_packed;\n-\n-/* hwrm_stat_ctx_query_output (size:1408b/176B) */\n-struct hwrm_stat_ctx_query_output {\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Number of TCAM index pairs to be swapped for the device. */\n+\tuint16_t\tcount;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* TCAM index pairs to be swapped for the device. */\n+\tuint16_t\tidx_pairs[48];\n+} __rte_packed;\n+\n+/* hwrm_tf_tcam_move_output (size:128b/16B) */\n+struct hwrm_tf_tcam_move_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40061,64 +42420,26 @@ struct hwrm_stat_ctx_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of transmitted packets with error */\n-\tuint64_t\ttx_err_pkts;\n-\t/* Number of dropped packets on transmit path */\n-\tuint64_t\ttx_drop_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of received packets with error */\n-\tuint64_t\trx_err_pkts;\n-\t/* Number of dropped packets on receive path */\n-\tuint64_t\trx_drop_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of aggregated unicast packets */\n-\tuint64_t\trx_agg_pkts;\n-\t/* Number of aggregated unicast bytes */\n-\tuint64_t\trx_agg_bytes;\n-\t/* Number of aggregation events */\n-\tuint64_t\trx_agg_events;\n-\t/* Number of aborted aggregations */\n-\tuint64_t\trx_agg_aborts;\n-\tuint8_t\tunused_0[7];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_stat_ext_ctx_query *\n- ***************************/\n+/*********************\n+ * hwrm_tf_tcam_free *\n+ *********************/\n \n \n-/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */\n-struct hwrm_stat_ext_ctx_query_input {\n+/* hwrm_tf_tcam_free_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40147,21 +42468,33 @@ struct hwrm_stat_ext_ctx_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the extended statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tflags;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * This bit is set to 1 when request is for a counter mask,\n-\t * representing the width of each of the stats counters, rather\n-\t * than counters themselves.\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\t#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \\\n-\t\tUINT32_C(0x1)\n-\tuint8_t\tunused_0[3];\n+\tuint32_t\ttype;\n+\t/* Number of TCAM index to be deleted for the device. */\n+\tuint16_t\tcount;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* TCAM index list to be deleted for the device. */\n+\tuint16_t\tidx_list[48];\n } __rte_packed;\n \n-/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */\n-struct hwrm_stat_ext_ctx_query_output {\n+/* hwrm_tf_tcam_free_output (size:128b/16B) */\n+struct hwrm_tf_tcam_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40170,66 +42503,26 @@ struct hwrm_stat_ext_ctx_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on receive path */\n-\tuint64_t\trx_discard_pkts;\n-\t/* Number of packets on receive path with error */\n-\tuint64_t\trx_error_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of packets on transmit path with error */\n-\tuint64_t\ttx_error_pkts;\n-\t/* Number of discarded packets on transmit path */\n-\tuint64_t\ttx_discard_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of TPA eligible packets */\n-\tuint64_t\trx_tpa_eligible_pkt;\n-\t/* Number of TPA eligible bytes */\n-\tuint64_t\trx_tpa_eligible_bytes;\n-\t/* Number of TPA packets */\n-\tuint64_t\trx_tpa_pkt;\n-\t/* Number of TPA bytes */\n-\tuint64_t\trx_tpa_bytes;\n-\t/* Number of TPA errors */\n-\tuint64_t\trx_tpa_errors;\n-\tuint8_t\tunused_0[7];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_stat_ctx_eng_query *\n- ***************************/\n+/**************************\n+ * hwrm_tf_global_cfg_set *\n+ **************************/\n \n \n-/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */\n-struct hwrm_stat_ctx_eng_query_input {\n+/* hwrm_tf_global_cfg_set_input (size:448b/56B) */\n+struct hwrm_tf_global_cfg_set_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40258,13 +42551,34 @@ struct hwrm_stat_ctx_eng_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX\n+\t/* Global Cfg type */\n+\tuint32_t\ttype;\n+\t/* Offset of the type */\n+\tuint32_t\toffset;\n+\t/* Size of the data to set in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/* Data to set */\n+\tuint8_t\tdata[8];\n+\t/* Mask of data to set, 0 indicates no mask */\n+\tuint8_t\tmask[8];\n } __rte_packed;\n \n-/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */\n-struct hwrm_stat_ctx_eng_query_output {\n+/* hwrm_tf_global_cfg_set_output (size:128b/16B) */\n+struct hwrm_tf_global_cfg_set_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40273,65 +42587,26 @@ struct hwrm_stat_ctx_eng_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * Count of data bytes into the Engine.\n-\t * This includes any user supplied prefix,\n-\t * but does not include any predefined\n-\t * prefix data.\n-\t */\n-\tuint64_t\teng_bytes_in;\n-\t/* Count of data bytes out of the Engine. */\n-\tuint64_t\teng_bytes_out;\n-\t/*\n-\t * Count, in 4-byte (dword) units, of bytes\n-\t * that are input as auxiliary data.\n-\t * This includes the aux_cmd data.\n-\t */\n-\tuint64_t\taux_bytes_in;\n-\t/*\n-\t * Count, in 4-byte (dword) units, of bytes\n-\t * that are output as auxiliary data.\n-\t * This count is the buffer space for aux_data\n-\t * output provided in the RQE, not the actual\n-\t * aux_data written\n-\t */\n-\tuint64_t\taux_bytes_out;\n-\t/* Count of number of commands executed. */\n-\tuint64_t\tcommands;\n-\t/*\n-\t * Count of number of error commands.\n-\t * These are the commands with a\n-\t * non-zero status value.\n-\t */\n-\tuint64_t\terror_commands;\n-\t/*\n-\t * Compression/Encryption Engine usage,\n-\t * the unit is count of clock cycles\n-\t */\n-\tuint64_t\tcce_engine_usage;\n-\t/*\n-\t * De-Compression/De-cryption Engine usage,\n-\t * the unit is count of clock cycles\n-\t */\n-\tuint64_t\tcdd_engine_usage;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_stat_ctx_clr_stats *\n- ***************************/\n+/**************************\n+ * hwrm_tf_global_cfg_get *\n+ **************************/\n \n \n-/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */\n-struct hwrm_stat_ctx_clr_stats_input {\n+/* hwrm_tf_global_cfg_get_input (size:320b/40B) */\n+struct hwrm_tf_global_cfg_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40360,13 +42635,30 @@ struct hwrm_stat_ctx_clr_stats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX\n+\t/* Global Cfg type */\n+\tuint32_t\ttype;\n+\t/* Offset of the type */\n+\tuint32_t\toffset;\n+\t/* Size of the data to set in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n } __rte_packed;\n \n-/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */\n-struct hwrm_stat_ctx_clr_stats_output {\n+/* hwrm_tf_global_cfg_get_output (size:256b/32B) */\n+struct hwrm_tf_global_cfg_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40375,24 +42667,21 @@ struct hwrm_stat_ctx_clr_stats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n+\t/* Size of the data read in bytes */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/* Data to set */\n+\tuint8_t\tdata[16];\n } __rte_packed;\n \n-/********************\n- * hwrm_pcie_qstats *\n- ********************/\n+/**********************\n+ * hwrm_tf_if_tbl_get *\n+ **********************/\n \n \n-/* hwrm_pcie_qstats_input (size:256b/32B) */\n-struct hwrm_pcie_qstats_input {\n+/* hwrm_tf_if_tbl_get_input (size:256b/32B) */\n+struct hwrm_tf_if_tbl_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40421,22 +42710,31 @@ struct hwrm_pcie_qstats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n \t/*\n-\t * The size of PCIe statistics block in bytes.\n-\t * Firmware will DMA the PCIe statistics to\n-\t * the host with this field size in the response.\n-\t */\n-\tuint16_t\tpcie_stat_size;\n-\tuint8_t\tunused_0[6];\n-\t/*\n-\t * This is the host address where\n-\t * PCIe statistics will be stored\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\tuint64_t\tpcie_stat_host_addr;\n+\tuint32_t\ttype;\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n } __rte_packed;\n \n-/* hwrm_pcie_qstats_output (size:128b/16B) */\n-struct hwrm_pcie_qstats_output {\n+/* hwrm_tf_if_tbl_get_output (size:256b/32B) */\n+struct hwrm_tf_if_tbl_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40445,62 +42743,34 @@ struct hwrm_pcie_qstats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* The size of PCIe statistics block in bytes. */\n-\tuint16_t\tpcie_stat_size;\n-\tuint8_t\tunused_0[5];\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint16_t\tunused0;\n+\t/* Response data. */\n+\tuint8_t\tdata[8];\n+\t/* unused */\n+\tuint8_t\tunused1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* PCIe Statistics Formats */\n-/* pcie_ctx_hw_stats (size:768b/96B) */\n-struct pcie_ctx_hw_stats {\n-\t/* Number of physical layer receiver errors */\n-\tuint64_t\tpcie_pl_signal_integrity;\n-\t/* Number of DLLP CRC errors detected by Data Link Layer */\n-\tuint64_t\tpcie_dl_signal_integrity;\n-\t/*\n-\t * Number of TLP LCRC and sequence number errors detected\n-\t * by Data Link Layer\n-\t */\n-\tuint64_t\tpcie_tl_signal_integrity;\n-\t/* Number of times LTSSM entered Recovery state */\n-\tuint64_t\tpcie_link_integrity;\n-\t/* Report number of TLP bits that have been transmitted in Mbps */\n-\tuint64_t\tpcie_tx_traffic_rate;\n-\t/* Report number of TLP bits that have been received in Mbps */\n-\tuint64_t\tpcie_rx_traffic_rate;\n-\t/* Number of DLLP bytes that have been transmitted */\n-\tuint64_t\tpcie_tx_dllp_statistics;\n-\t/* Number of DLLP bytes that have been received */\n-\tuint64_t\tpcie_rx_dllp_statistics;\n-\t/*\n-\t * Number of times spent in each phase of gen3\n-\t * equalization\n-\t */\n-\tuint64_t\tpcie_equalization_time;\n-\t/* Records the last 16 transitions of the LTSSM */\n-\tuint32_t\tpcie_ltssm_histogram[4];\n-\t/*\n-\t * Record the last 8 reasons on why LTSSM transitioned\n-\t * to Recovery\n-\t */\n-\tuint64_t\tpcie_recovery_histogram;\n-} __rte_packed;\n-\n-/**********************\n- * hwrm_exec_fwd_resp *\n- **********************/\n+/***************************\n+ * hwrm_tf_if_tbl_type_set *\n+ ***************************/\n \n \n-/* hwrm_exec_fwd_resp_input (size:1024b/128B) */\n-struct hwrm_exec_fwd_resp_input {\n+/* hwrm_tf_if_tbl_set_input (size:384b/48B) */\n+struct hwrm_tf_if_tbl_set_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40529,26 +42799,37 @@ struct hwrm_exec_fwd_resp_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n \t/*\n-\t * This is an encapsulated request. This request should\n-\t * be executed by the HWRM and the response should be\n-\t * provided in the response buffer inside the encapsulated\n-\t * request.\n-\t */\n-\tuint32_t\tencap_request[26];\n-\t/*\n-\t * This value indicates the target id of the response to\n-\t * the encapsulated request.\n-\t * 0x0 - 0xFFF8 - Used for function ids\n-\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n-\t * 0xFFFF - HWRM\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\tuint16_t\tencap_resp_target_id;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\ttype;\n+\t/* Index of the type to set. */\n+\tuint32_t\tindex;\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused1[6];\n+\t/* Data to be set. */\n+\tuint8_t\tdata[8];\n } __rte_packed;\n \n-/* hwrm_exec_fwd_resp_output (size:128b/16B) */\n-struct hwrm_exec_fwd_resp_output {\n+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */\n+struct hwrm_tf_if_tbl_set_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40557,24 +42838,26 @@ struct hwrm_exec_fwd_resp_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/************************\n- * hwrm_reject_fwd_resp *\n- ************************/\n+/*****************************\n+ * hwrm_tf_tbl_type_bulk_get *\n+ *****************************/\n \n \n-/* hwrm_reject_fwd_resp_input (size:1024b/128B) */\n-struct hwrm_reject_fwd_resp_input {\n+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */\n+struct hwrm_tf_tbl_type_bulk_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40603,26 +42886,37 @@ struct hwrm_reject_fwd_resp_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n \t/*\n-\t * This is an encapsulated request. This request should\n-\t * be rejected by the HWRM and the error response should be\n-\t * provided in the response buffer inside the encapsulated\n-\t * request.\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\tuint32_t\tencap_request[26];\n-\t/*\n-\t * This value indicates the target id of the response to\n-\t * the encapsulated request.\n-\t * 0x0 - 0xFFF8 - Used for function ids\n-\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n-\t * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\tencap_resp_target_id;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\ttype;\n+\t/* Starting index of the type to retrieve. */\n+\tuint32_t\tstart_index;\n+\t/* Number of entries to retrieve. */\n+\tuint32_t\tnum_entries;\n+\t/* Number of entries to retrieve. */\n+\tuint32_t\tunused1;\n+\t/* Host memory where data will be stored. */\n+\tuint64_t\thost_addr;\n } __rte_packed;\n \n-/* hwrm_reject_fwd_resp_output (size:128b/16B) */\n-struct hwrm_reject_fwd_resp_output {\n+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */\n+struct hwrm_tf_tbl_type_bulk_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40631,24 +42925,30 @@ struct hwrm_reject_fwd_resp_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*****************\n- * hwrm_fwd_resp *\n- *****************/\n+/******************************\n+ * hwrm_tunnel_dst_port_query *\n+ ******************************/\n \n \n-/* hwrm_fwd_resp_input (size:1024b/128B) */\n-struct hwrm_fwd_resp_input {\n+/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40677,41 +42977,33 @@ struct hwrm_fwd_resp_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * This value indicates the target id of the encapsulated\n-\t * response.\n-\t * 0x0 - 0xFFF8 - Used for function ids\n-\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n-\t * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\tencap_resp_target_id;\n-\t/*\n-\t * This value indicates the completion ring the encapsulated\n-\t * response will be optionally completed on. If the value is\n-\t * -1, then no CR completion shall be generated for the\n-\t * encapsulated response. Any other value must be a\n-\t * valid CR ring_id value. If a valid encap_resp_cmpl_ring\n-\t * is provided, then a CR completion shall be generated for\n-\t * the encapsulated response.\n-\t */\n-\tuint16_t\tencap_resp_cmpl_ring;\n-\t/* This field indicates the length of encapsulated response. */\n-\tuint16_t\tencap_resp_len;\n-\tuint8_t\tunused_0;\n-\tuint8_t\tunused_1;\n-\t/*\n-\t * This is the host address where the encapsulated response\n-\t * will be written.\n-\t * This area must be 16B aligned and must be cleared to zero\n-\t * before the original request is made.\n-\t */\n-\tuint64_t\tencap_resp_addr;\n-\t/* This is an encapsulated response. */\n-\tuint32_t\tencap_resp[24];\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\tuint8_t\tunused_0[7];\n } __rte_packed;\n \n-/* hwrm_fwd_resp_output (size:128b/16B) */\n-struct hwrm_fwd_resp_output {\n+/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40720,7 +43012,25 @@ struct hwrm_fwd_resp_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field represents the identifier of L4 destination port\n+\t * used for the given tunnel type. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t */\n+\tuint16_t\ttunnel_dst_port_id;\n+\t/*\n+\t * This field represents the value of L4 destination port\n+\t * identified by tunnel_dst_port_id. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t * This field is in network byte order.\n+\t *\n+\t * A value of 0 means that the destination port is not\n+\t * configured.\n+\t */\n+\tuint16_t\ttunnel_dst_port_val;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -40731,13 +43041,13 @@ struct hwrm_fwd_resp_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*****************************\n- * hwrm_fwd_async_event_cmpl *\n- *****************************/\n+/******************************\n+ * hwrm_tunnel_dst_port_alloc *\n+ ******************************/\n \n \n-/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */\n-struct hwrm_fwd_async_event_cmpl_input {\n+/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40766,22 +43076,45 @@ struct hwrm_fwd_async_event_cmpl_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\tuint8_t\tunused_0;\n \t/*\n-\t * This value indicates the target id of the encapsulated\n-\t * asynchronous event.\n-\t * 0x0 - 0xFFF8 - Used for function ids\n-\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n-\t * 0xFFFF - Broadcast to all children VFs (only applicable when\n-\t * a PF is the requester)\n+\t * This field represents the value of L4 destination port used\n+\t * for the given tunnel type. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t *\n+\t * This field is in network byte order.\n+\t *\n+\t * A value of 0 shall fail the command.\n \t */\n-\tuint16_t\tencap_async_event_target_id;\n-\tuint8_t\tunused_0[6];\n-\t/* This is an encapsulated asynchronous event completion. */\n-\tuint32_t\tencap_async_event_cmpl[4];\n+\tuint16_t\ttunnel_dst_port_val;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */\n-struct hwrm_fwd_async_event_cmpl_output {\n+/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40790,7 +43123,12 @@ struct hwrm_fwd_async_event_cmpl_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n+\t * types that has l4 destination port parameters.\n+\t */\n+\tuint16_t\ttunnel_dst_port_id;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -40801,13 +43139,13 @@ struct hwrm_fwd_async_event_cmpl_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_nvm_raw_write_blk *\n- **************************/\n+/*****************************\n+ * hwrm_tunnel_dst_port_free *\n+ *****************************/\n \n \n-/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */\n-struct hwrm_nvm_raw_write_blk_input {\n+/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40836,22 +43174,39 @@ struct hwrm_nvm_raw_write_blk_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\tuint8_t\tunused_0;\n \t/*\n-\t * 64-bit Host Source Address.\n-\t * This is the location of the source data to be written.\n-\t */\n-\tuint64_t\thost_src_addr;\n-\t/*\n-\t * 32-bit Destination Address.\n-\t * This is the NVRAM byte-offset where the source data will be written to.\n+\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n+\t * types that has l4 destination port parameters.\n \t */\n-\tuint32_t\tdest_addr;\n-\t/* Length of data to be written, in bytes. */\n-\tuint32_t\tlen;\n+\tuint16_t\ttunnel_dst_port_id;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */\n-struct hwrm_nvm_raw_write_blk_output {\n+/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40860,7 +43215,7 @@ struct hwrm_nvm_raw_write_blk_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -40871,84 +43226,157 @@ struct hwrm_nvm_raw_write_blk_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*****************\n- * hwrm_nvm_read *\n- *****************/\n+/* Periodic statistics context DMA to host. */\n+/* ctx_hw_stats (size:1280b/160B) */\n+struct ctx_hw_stats {\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on receive path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\ttpa_pkts;\n+\t/* Number of TPA bytes */\n+\tuint64_t\ttpa_bytes;\n+\t/* Number of TPA events */\n+\tuint64_t\ttpa_events;\n+\t/* Number of TPA aborts */\n+\tuint64_t\ttpa_aborts;\n+} __rte_packed;\n \n+/*\n+ * Extended periodic statistics context DMA to host. On cards that\n+ * support TPA v2, additional TPA related stats exist and can be retrieved\n+ * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.\n+ */\n+/* ctx_hw_stats_ext (size:1408b/176B) */\n+struct ctx_hw_stats_ext {\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on receive path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA eligible packets */\n+\tuint64_t\trx_tpa_eligible_pkt;\n+\t/* Number of TPA eligible bytes */\n+\tuint64_t\trx_tpa_eligible_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\trx_tpa_pkt;\n+\t/* Number of TPA bytes */\n+\tuint64_t\trx_tpa_bytes;\n+\t/* Number of TPA errors */\n+\tuint64_t\trx_tpa_errors;\n+\t/* Number of TPA events */\n+\tuint64_t\trx_tpa_events;\n+} __rte_packed;\n \n-/* hwrm_nvm_read_input (size:320b/40B) */\n-struct hwrm_nvm_read_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+/* Periodic Engine statistics context DMA to host. */\n+/* ctx_eng_stats (size:512b/64B) */\n+struct ctx_eng_stats {\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Count of data bytes into the Engine.\n+\t * This includes any user supplied prefix,\n+\t * but does not include any predefined\n+\t * prefix data.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint64_t\teng_bytes_in;\n+\t/* Count of data bytes out of the Engine. */\n+\tuint64_t\teng_bytes_out;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are input as auxiliary data.\n+\t * This includes the aux_cmd data.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint64_t\taux_bytes_in;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are output as auxiliary data.\n+\t * This count is the buffer space for aux_data\n+\t * output provided in the RQE, not the actual\n+\t * aux_data written\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint64_t\taux_bytes_out;\n+\t/* Count of number of commands executed. */\n+\tuint64_t\tcommands;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Count of number of error commands.\n+\t * These are the commands with a\n+\t * non-zero status value.\n \t */\n-\tuint64_t\tresp_addr;\n+\tuint64_t\terror_commands;\n \t/*\n-\t * 64-bit Host Destination Address.\n-\t * This is the host address where the data will be written to.\n+\t * Compression/Encryption Engine usage,\n+\t * the unit is count of clock cycles\n \t */\n-\tuint64_t\thost_dest_addr;\n-\t/* The 0-based index of the directory entry. */\n-\tuint16_t\tdir_idx;\n-\tuint8_t\tunused_0[2];\n-\t/* The NVRAM byte-offset to read from. */\n-\tuint32_t\toffset;\n-\t/* The length of the data to be read, in bytes. */\n-\tuint32_t\tlen;\n-\tuint8_t\tunused_1[4];\n-} __rte_packed;\n-\n-/* hwrm_nvm_read_output (size:128b/16B) */\n-struct hwrm_nvm_read_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint64_t\tcce_engine_usage;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * De-Compression/De-cryption Engine usage,\n+\t * the unit is count of clock cycles\n \t */\n-\tuint8_t\tvalid;\n+\tuint64_t\tcdd_engine_usage;\n } __rte_packed;\n \n-/*********************\n- * hwrm_nvm_raw_dump *\n- *********************/\n+/***********************\n+ * hwrm_stat_ctx_alloc *\n+ ***********************/\n \n \n-/* hwrm_nvm_raw_dump_input (size:256b/32B) */\n-struct hwrm_nvm_raw_dump_input {\n+/* hwrm_stat_ctx_alloc_input (size:256b/32B) */\n+struct hwrm_stat_ctx_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -40978,18 +43406,50 @@ struct hwrm_nvm_raw_dump_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * 64-bit Host Destination Address.\n-\t * This is the host address where the data will be written to.\n+\t * This is the address for statistic block.\n+\t * > For new versions of the chip, this address should be 128B\n+\t * > aligned.\n \t */\n-\tuint64_t\thost_dest_addr;\n-\t/* 32-bit NVRAM byte-offset to read from. */\n-\tuint32_t\toffset;\n-\t/* Total length of NVRAM contents to be read, in bytes. */\n-\tuint32_t\tlen;\n+\tuint64_t\tstats_dma_addr;\n+\t/*\n+\t * The statistic block update period in ms.\n+\t * e.g. 250ms, 500ms, 750ms, 1000ms.\n+\t * If update_period_ms is 0, then the stats update\n+\t * shall be never done and the DMA address shall not be used.\n+\t * In this case, the stat block can only be read by\n+\t * hwrm_stat_ctx_query command.\n+\t * On Ethernet/L2 based devices:\n+\t * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),\n+\t * ctx_hw_stats_ext is used for DMA,\n+\t * else\n+\t * ctx_hw_stats is used for DMA.\n+\t */\n+\tuint32_t\tupdate_period_ms;\n+\t/*\n+\t * This field is used to specify statistics context specific\n+\t * configuration flags.\n+\t */\n+\tuint8_t\tstat_ctx_flags;\n+\t/*\n+\t * When this bit is set to '1', the statistics context shall be\n+\t * allocated for RoCE traffic only. In this case, traffic other\n+\t * than offloaded RoCE traffic shall not be included in this\n+\t * statistic context.\n+\t * When this bit is set to '0', the statistics context shall be\n+\t * used for network traffic or engine traffic.\n+\t */\n+\t#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * This is the size of the structure (ctx_hw_stats or\n+\t * ctx_hw_stats_ext) that the driver has allocated to be used\n+\t * for the periodic DMA updates.\n+\t */\n+\tuint16_t\tstats_dma_length;\n } __rte_packed;\n \n-/* hwrm_nvm_raw_dump_output (size:128b/16B) */\n-struct hwrm_nvm_raw_dump_output {\n+/* hwrm_stat_ctx_alloc_output (size:128b/16B) */\n+struct hwrm_stat_ctx_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -40998,7 +43458,9 @@ struct hwrm_nvm_raw_dump_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* This is the statistics context ID value. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41009,13 +43471,13 @@ struct hwrm_nvm_raw_dump_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/****************************\n- * hwrm_nvm_get_dir_entries *\n- ****************************/\n+/**********************\n+ * hwrm_stat_ctx_free *\n+ **********************/\n \n \n-/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */\n-struct hwrm_nvm_get_dir_entries_input {\n+/* hwrm_stat_ctx_free_input (size:192b/24B) */\n+struct hwrm_stat_ctx_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41044,15 +43506,13 @@ struct hwrm_nvm_get_dir_entries_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * 64-bit Host Destination Address.\n-\t * This is the host address where the directory will be written.\n-\t */\n-\tuint64_t\thost_dest_addr;\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */\n-struct hwrm_nvm_get_dir_entries_output {\n+/* hwrm_stat_ctx_free_output (size:128b/16B) */\n+struct hwrm_stat_ctx_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41061,7 +43521,9 @@ struct hwrm_nvm_get_dir_entries_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* This is the statistics context ID value. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41072,13 +43534,13 @@ struct hwrm_nvm_get_dir_entries_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_nvm_get_dir_info *\n- *************************/\n+/***********************\n+ * hwrm_stat_ctx_query *\n+ ***********************/\n \n \n-/* hwrm_nvm_get_dir_info_input (size:128b/16B) */\n-struct hwrm_nvm_get_dir_info_input {\n+/* hwrm_stat_ctx_query_input (size:192b/24B) */\n+struct hwrm_stat_ctx_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41107,10 +43569,20 @@ struct hwrm_nvm_get_dir_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-} __rte_packed;\n-\n-/* hwrm_nvm_get_dir_info_output (size:192b/24B) */\n-struct hwrm_nvm_get_dir_info_output {\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tflags;\n+\t/*\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n+} __rte_packed;\n+\n+/* hwrm_stat_ctx_query_output (size:1408b/176B) */\n+struct hwrm_stat_ctx_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41119,10 +43591,46 @@ struct hwrm_nvm_get_dir_info_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of directory entries in the directory. */\n-\tuint32_t\tentries;\n-\t/* Size of each directory entry, in bytes. */\n-\tuint32_t\tentry_length;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets discarded in transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of packets in transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of packets discarded in receive path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets in receive path with errors */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of aggregated unicast packets */\n+\tuint64_t\trx_agg_pkts;\n+\t/* Number of aggregated unicast bytes */\n+\tuint64_t\trx_agg_bytes;\n+\t/* Number of aggregation events */\n+\tuint64_t\trx_agg_events;\n+\t/* Number of aborted aggregations */\n+\tuint64_t\trx_agg_aborts;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -41134,13 +43642,13 @@ struct hwrm_nvm_get_dir_info_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************\n- * hwrm_nvm_write *\n- ******************/\n+/***************************\n+ * hwrm_stat_ext_ctx_query *\n+ ***************************/\n \n \n-/* hwrm_nvm_write_input (size:384b/48B) */\n-struct hwrm_nvm_write_input {\n+/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */\n+struct hwrm_stat_ext_ctx_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41169,49 +43677,21 @@ struct hwrm_nvm_write_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* ID of the extended statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tflags;\n \t/*\n-\t * 64-bit Host Source Address.\n-\t * This is where the source data is.\n-\t */\n-\tuint64_t\thost_src_addr;\n-\t/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */\n-\tuint16_t\tdir_type;\n-\t/*\n-\t * Directory ordinal.\n-\t * The 0-based instance of the combined Directory Entry Type and Extension.\n-\t */\n-\tuint16_t\tdir_ordinal;\n-\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */\n-\tuint16_t\tdir_ext;\n-\t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */\n-\tuint16_t\tdir_attr;\n-\t/*\n-\t * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.\n-\t * The data length stored in the directory entry will be updated to reflect this value once the write is complete.\n-\t */\n-\tuint32_t\tdir_data_length;\n-\t/* Option. */\n-\tuint16_t\toption;\n-\tuint16_t\tflags;\n-\t/*\n-\t * When this bit is '1', the original active image\n-\t * will not be removed. TBD: what purpose is this?\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n \t */\n-\t#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \\\n+\t#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).\n-\t * If this value is less than the specified data length, it will be ignored.\n-\t * The response will contain the actual allocated item length, which may be greater than the requested item length.\n-\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate\n-\t * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).\n-\t */\n-\tuint32_t\tdir_item_length;\n-\tuint32_t\tunused_0;\n+\tuint8_t\tunused_0[3];\n } __rte_packed;\n \n-/* hwrm_nvm_write_output (size:128b/16B) */\n-struct hwrm_nvm_write_output {\n+/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */\n+struct hwrm_stat_ext_ctx_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41220,14 +43700,51 @@ struct hwrm_nvm_write_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.\n-\t * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.\n-\t */\n-\tuint32_t\tdir_item_length;\n-\t/* The directory index of the created or modified item. */\n-\tuint16_t\tdir_idx;\n-\tuint8_t\tunused_0;\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on receive path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA eligible packets */\n+\tuint64_t\trx_tpa_eligible_pkt;\n+\t/* Number of TPA eligible bytes */\n+\tuint64_t\trx_tpa_eligible_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\trx_tpa_pkt;\n+\t/* Number of TPA bytes */\n+\tuint64_t\trx_tpa_bytes;\n+\t/* Number of TPA errors */\n+\tuint64_t\trx_tpa_errors;\n+\t/* Number of TPA events */\n+\tuint64_t\trx_tpa_events;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41238,31 +43755,13 @@ struct hwrm_nvm_write_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_write_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_write_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* Unable to complete operation due to fragmentation */\n-\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)\n-\t/* nvm is completely full. */\n-\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)\n-\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/*******************\n- * hwrm_nvm_modify *\n- *******************/\n+/***************************\n+ * hwrm_stat_ctx_eng_query *\n+ ***************************/\n \n \n-/* hwrm_nvm_modify_input (size:320b/40B) */\n-struct hwrm_nvm_modify_input {\n+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */\n+struct hwrm_stat_ctx_eng_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41291,42 +43790,13 @@ struct hwrm_nvm_modify_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * 64-bit Host Source Address.\n-\t * This is where the modified data is.\n-\t */\n-\tuint64_t\thost_src_addr;\n-\t/* 16-bit directory entry index. */\n-\tuint16_t\tdir_idx;\n-\tuint16_t\tflags;\n-\t/*\n-\t * This flag indicates the sender wants to modify a continuous NVRAM\n-\t * area using a batch of this HWRM requests. The offset of a request\n-\t * must be continuous to the end of previous request's. Firmware does\n-\t * not update the directory entry until receiving the last request,\n-\t * which is indicated by the batch_last flag.\n-\t * This flag is set usually when a sender does not have a block of\n-\t * memory that is big enough to hold the entire NVRAM data for send\n-\t * at one time.\n-\t */\n-\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)\n-\t/*\n-\t * This flag can be used only when the batch_mode flag is set.\n-\t * It indicates this request is the last of batch requests.\n-\t */\n-\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)\n-\t/* 32-bit NVRAM byte-offset to modify content from. */\n-\tuint32_t\toffset;\n-\t/*\n-\t * Length of data to be modified, in bytes. The length shall\n-\t * be non-zero.\n-\t */\n-\tuint32_t\tlen;\n-\tuint8_t\tunused_1[4];\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_nvm_modify_output (size:128b/16B) */\n-struct hwrm_nvm_modify_output {\n+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */\n+struct hwrm_stat_ctx_eng_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41335,6 +43805,47 @@ struct hwrm_nvm_modify_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Count of data bytes into the Engine.\n+\t * This includes any user supplied prefix,\n+\t * but does not include any predefined\n+\t * prefix data.\n+\t */\n+\tuint64_t\teng_bytes_in;\n+\t/* Count of data bytes out of the Engine. */\n+\tuint64_t\teng_bytes_out;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are input as auxiliary data.\n+\t * This includes the aux_cmd data.\n+\t */\n+\tuint64_t\taux_bytes_in;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are output as auxiliary data.\n+\t * This count is the buffer space for aux_data\n+\t * output provided in the RQE, not the actual\n+\t * aux_data written\n+\t */\n+\tuint64_t\taux_bytes_out;\n+\t/* Count of number of commands executed. */\n+\tuint64_t\tcommands;\n+\t/*\n+\t * Count of number of error commands.\n+\t * These are the commands with a\n+\t * non-zero status value.\n+\t */\n+\tuint64_t\terror_commands;\n+\t/*\n+\t * Compression/Encryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcce_engine_usage;\n+\t/*\n+\t * De-Compression/De-cryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcdd_engine_usage;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -41347,12 +43858,12 @@ struct hwrm_nvm_modify_output {\n } __rte_packed;\n \n /***************************\n- * hwrm_nvm_find_dir_entry *\n+ * hwrm_stat_ctx_clr_stats *\n ***************************/\n \n \n-/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */\n-struct hwrm_nvm_find_dir_entry_input {\n+/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */\n+struct hwrm_stat_ctx_clr_stats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41381,42 +43892,13 @@ struct hwrm_nvm_find_dir_entry_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the dir_idx_valid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \\\n-\t\tUINT32_C(0x1)\n-\t/* Directory Entry Index */\n-\tuint16_t\tdir_idx;\n-\t/* Directory Entry (Image) Type */\n-\tuint16_t\tdir_type;\n-\t/*\n-\t * Directory ordinal.\n-\t * The instance of this Directory Type\n-\t */\n-\tuint16_t\tdir_ordinal;\n-\t/* The Directory Entry Extension flags. */\n-\tuint16_t\tdir_ext;\n-\t/* This value indicates the search option using dir_ordinal. */\n-\tuint8_t\topt_ordinal;\n-\t/* This value indicates the search option using dir_ordinal. */\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0\n-\t/* Equal to specified ordinal value. */\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)\n-\t/* Greater than or equal to specified ordinal value */\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)\n-\t/* Greater than specified ordinal value */\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)\n-\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \\\n-\t\tHWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT\n-\tuint8_t\tunused_0[3];\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */\n-struct hwrm_nvm_find_dir_entry_output {\n+/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */\n+struct hwrm_stat_ctx_clr_stats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41425,19 +43907,6 @@ struct hwrm_nvm_find_dir_entry_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Allocated NVRAM for this directory entry, in bytes. */\n-\tuint32_t\tdir_item_length;\n-\t/* Size of the stored data for this directory entry, in bytes. */\n-\tuint32_t\tdir_data_length;\n-\t/*\n-\t * Firmware version.\n-\t * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.\n-\t */\n-\tuint32_t\tfw_ver;\n-\t/* Directory ordinal. */\n-\tuint16_t\tdir_ordinal;\n-\t/* Directory Entry Index */\n-\tuint16_t\tdir_idx;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -41449,13 +43918,13 @@ struct hwrm_nvm_find_dir_entry_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/****************************\n- * hwrm_nvm_erase_dir_entry *\n- ****************************/\n+/********************\n+ * hwrm_pcie_qstats *\n+ ********************/\n \n \n-/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */\n-struct hwrm_nvm_erase_dir_entry_input {\n+/* hwrm_pcie_qstats_input (size:256b/32B) */\n+struct hwrm_pcie_qstats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41484,13 +43953,22 @@ struct hwrm_nvm_erase_dir_entry_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Directory Entry Index */\n-\tuint16_t\tdir_idx;\n+\t/*\n+\t * The size of PCIe statistics block in bytes.\n+\t * Firmware will DMA the PCIe statistics to\n+\t * the host with this field size in the response.\n+\t */\n+\tuint16_t\tpcie_stat_size;\n \tuint8_t\tunused_0[6];\n+\t/*\n+\t * This is the host address where\n+\t * PCIe statistics will be stored\n+\t */\n+\tuint64_t\tpcie_stat_host_addr;\n } __rte_packed;\n \n-/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */\n-struct hwrm_nvm_erase_dir_entry_output {\n+/* hwrm_pcie_qstats_output (size:128b/16B) */\n+struct hwrm_pcie_qstats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41499,7 +43977,9 @@ struct hwrm_nvm_erase_dir_entry_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* The size of PCIe statistics block in bytes. */\n+\tuint16_t\tpcie_stat_size;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41510,13 +43990,49 @@ struct hwrm_nvm_erase_dir_entry_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*************************\n- * hwrm_nvm_get_dev_info *\n- *************************/\n+/* PCIe Statistics Formats */\n+/* pcie_ctx_hw_stats (size:768b/96B) */\n+struct pcie_ctx_hw_stats {\n+\t/* Number of physical layer receiver errors */\n+\tuint64_t\tpcie_pl_signal_integrity;\n+\t/* Number of DLLP CRC errors detected by Data Link Layer */\n+\tuint64_t\tpcie_dl_signal_integrity;\n+\t/*\n+\t * Number of TLP LCRC and sequence number errors detected\n+\t * by Data Link Layer\n+\t */\n+\tuint64_t\tpcie_tl_signal_integrity;\n+\t/* Number of times LTSSM entered Recovery state */\n+\tuint64_t\tpcie_link_integrity;\n+\t/* Report number of TLP bits that have been transmitted in Mbps */\n+\tuint64_t\tpcie_tx_traffic_rate;\n+\t/* Report number of TLP bits that have been received in Mbps */\n+\tuint64_t\tpcie_rx_traffic_rate;\n+\t/* Number of DLLP bytes that have been transmitted */\n+\tuint64_t\tpcie_tx_dllp_statistics;\n+\t/* Number of DLLP bytes that have been received */\n+\tuint64_t\tpcie_rx_dllp_statistics;\n+\t/*\n+\t * Number of times spent in each phase of gen3\n+\t * equalization\n+\t */\n+\tuint64_t\tpcie_equalization_time;\n+\t/* Records the last 16 transitions of the LTSSM */\n+\tuint32_t\tpcie_ltssm_histogram[4];\n+\t/*\n+\t * Record the last 8 reasons on why LTSSM transitioned\n+\t * to Recovery\n+\t */\n+\tuint64_t\tpcie_recovery_histogram;\n+} __rte_packed;\n \n+/**********************\n+ * hwrm_exec_fwd_resp *\n+ **********************/\n \n-/* hwrm_nvm_get_dev_info_input (size:128b/16B) */\n-struct hwrm_nvm_get_dev_info_input {\n+\n+/* hwrm_exec_fwd_resp_input (size:1024b/128B) */\n+struct hwrm_exec_fwd_resp_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41545,10 +44061,26 @@ struct hwrm_nvm_get_dev_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/*\n+\t * This is an encapsulated request. This request should\n+\t * be executed by the HWRM and the response should be\n+\t * provided in the response buffer inside the encapsulated\n+\t * request.\n+\t */\n+\tuint32_t\tencap_request[26];\n+\t/*\n+\t * This value indicates the target id of the response to\n+\t * the encapsulated request.\n+\t * 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n+\t * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\tencap_resp_target_id;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_nvm_get_dev_info_output (size:256b/32B) */\n-struct hwrm_nvm_get_dev_info_output {\n+/* hwrm_exec_fwd_resp_output (size:128b/16B) */\n+struct hwrm_exec_fwd_resp_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41557,23 +44089,7 @@ struct hwrm_nvm_get_dev_info_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Manufacturer ID. */\n-\tuint16_t\tmanufacturer_id;\n-\t/* Device ID. */\n-\tuint16_t\tdevice_id;\n-\t/* Sector size of the NVRAM device. */\n-\tuint32_t\tsector_size;\n-\t/* Total size, in bytes of the NVRAM device. */\n-\tuint32_t\tnvram_size;\n-\tuint32_t\treserved_size;\n-\t/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */\n-\tuint32_t\tavailable_size;\n-\t/* This field represents the major version of NVM cfg */\n-\tuint8_t\tnvm_cfg_ver_maj;\n-\t/* This field represents the minor version of NVM cfg */\n-\tuint8_t\tnvm_cfg_ver_min;\n-\t/* This field represents the update version of NVM cfg */\n-\tuint8_t\tnvm_cfg_ver_upd;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41584,13 +44100,13 @@ struct hwrm_nvm_get_dev_info_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_nvm_mod_dir_entry *\n- **************************/\n+/************************\n+ * hwrm_reject_fwd_resp *\n+ ************************/\n \n \n-/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */\n-struct hwrm_nvm_mod_dir_entry_input {\n+/* hwrm_reject_fwd_resp_input (size:1024b/128B) */\n+struct hwrm_reject_fwd_resp_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41619,32 +44135,26 @@ struct hwrm_nvm_mod_dir_entry_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the checksum field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)\n-\t/* Directory Entry Index */\n-\tuint16_t\tdir_idx;\n-\t/*\n-\t * Directory ordinal.\n-\t * The (0-based) instance of this Directory Type.\n+\t * This is an encapsulated request. This request should\n+\t * be rejected by the HWRM and the error response should be\n+\t * provided in the response buffer inside the encapsulated\n+\t * request.\n \t */\n-\tuint16_t\tdir_ordinal;\n-\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */\n-\tuint16_t\tdir_ext;\n-\t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */\n-\tuint16_t\tdir_attr;\n+\tuint32_t\tencap_request[26];\n \t/*\n-\t * If valid, then this field updates the checksum\n-\t * value of the content in the directory entry.\n+\t * This value indicates the target id of the response to\n+\t * the encapsulated request.\n+\t * 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n+\t * 0xFFFF - HWRM\n \t */\n-\tuint32_t\tchecksum;\n+\tuint16_t\tencap_resp_target_id;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */\n-struct hwrm_nvm_mod_dir_entry_output {\n+/* hwrm_reject_fwd_resp_output (size:128b/16B) */\n+struct hwrm_reject_fwd_resp_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41664,13 +44174,13 @@ struct hwrm_nvm_mod_dir_entry_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_nvm_verify_update *\n- **************************/\n+/*****************\n+ * hwrm_fwd_resp *\n+ *****************/\n \n \n-/* hwrm_nvm_verify_update_input (size:192b/24B) */\n-struct hwrm_nvm_verify_update_input {\n+/* hwrm_fwd_resp_input (size:1024b/128B) */\n+struct hwrm_fwd_resp_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41699,26 +44209,41 @@ struct hwrm_nvm_verify_update_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Directory Entry Type, to be verified. */\n-\tuint16_t\tdir_type;\n \t/*\n-\t * Directory ordinal.\n-\t * The instance of the Directory Type to be verified.\n+\t * This value indicates the target id of the encapsulated\n+\t * response.\n+\t * 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n+\t * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tdir_ordinal;\n+\tuint16_t\tencap_resp_target_id;\n \t/*\n-\t * The Directory Entry Extension flags.\n-\t * The \"UPDATE\" extension flag must be set in this value.\n-\t * A corresponding directory entry with the same type and ordinal values but *without*\n-\t * the \"UPDATE\" extension flag must also exist. The other flags of the extension must\n-\t * be identical between the active and update entries.\n+\t * This value indicates the completion ring the encapsulated\n+\t * response will be optionally completed on. If the value is\n+\t * -1, then no CR completion shall be generated for the\n+\t * encapsulated response. Any other value must be a\n+\t * valid CR ring_id value. If a valid encap_resp_cmpl_ring\n+\t * is provided, then a CR completion shall be generated for\n+\t * the encapsulated response.\n \t */\n-\tuint16_t\tdir_ext;\n-\tuint8_t\tunused_0[2];\n+\tuint16_t\tencap_resp_cmpl_ring;\n+\t/* This field indicates the length of encapsulated response. */\n+\tuint16_t\tencap_resp_len;\n+\tuint8_t\tunused_0;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * This is the host address where the encapsulated response\n+\t * will be written.\n+\t * This area must be 16B aligned and must be cleared to zero\n+\t * before the original request is made.\n+\t */\n+\tuint64_t\tencap_resp_addr;\n+\t/* This is an encapsulated response. */\n+\tuint32_t\tencap_resp[24];\n } __rte_packed;\n \n-/* hwrm_nvm_verify_update_output (size:128b/16B) */\n-struct hwrm_nvm_verify_update_output {\n+/* hwrm_fwd_resp_output (size:128b/16B) */\n+struct hwrm_fwd_resp_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41738,13 +44263,13 @@ struct hwrm_nvm_verify_update_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_nvm_install_update *\n- ***************************/\n+/*****************************\n+ * hwrm_fwd_async_event_cmpl *\n+ *****************************/\n \n \n-/* hwrm_nvm_install_update_input (size:192b/24B) */\n-struct hwrm_nvm_install_update_input {\n+/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */\n+struct hwrm_fwd_async_event_cmpl_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41774,56 +44299,21 @@ struct hwrm_nvm_install_update_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Installation type. If the value 3 through 0xffff is used,\n-\t * only packaged items with that type value will be installed and\n-\t * conditional installation directives for those packaged items\n-\t * will be over-ridden (i.e. 'create' or 'replace' will be treated\n-\t * as 'install').\n-\t */\n-\tuint32_t\tinstall_type;\n-\t/*\n-\t * Perform a normal package installation. Conditional installation\n-\t * directives (e.g. 'create' and 'replace') of packaged items\n-\t * will be followed.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)\n-\t/*\n-\t * Install all packaged items regardless of installation directive\n-\t * (i.e. treat all packaged items as though they have an installation\n-\t * directive of 'install').\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \\\n-\t\tUINT32_C(0xffffffff)\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL\n-\tuint16_t\tflags;\n-\t/* If set to 1, then securely erase all unused locations in persistent storage. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * If set to 1, then unspecified images, images not in the package file, will be safely deleted.\n-\t * When combined with erase_unused_space then unspecified images will be securely erased.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * If set to 1, FW will defragment the NVM if defragmentation is required for the update.\n-\t * Allow additional time for this command to complete if this bit is set to 1.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * If set to 1, FW will verify the package in the \"UPDATE\" NVM item\n-\t * without installing it. This flag is for FW internal use only.\n-\t * Users should not set this flag. The request will otherwise fail.\n+\t * This value indicates the target id of the encapsulated\n+\t * asynchronous event.\n+\t * 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors\n+\t * 0xFFFF - Broadcast to all children VFs (only applicable when\n+\t * a PF is the requester)\n \t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \\\n-\t\tUINT32_C(0x8)\n-\tuint8_t\tunused_0[2];\n+\tuint16_t\tencap_async_event_target_id;\n+\tuint8_t\tunused_0[6];\n+\t/* This is an encapsulated asynchronous event completion. */\n+\tuint32_t\tencap_async_event_cmpl[4];\n } __rte_packed;\n \n-/* hwrm_nvm_install_update_output (size:192b/24B) */\n-struct hwrm_nvm_install_update_output {\n+/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */\n+struct hwrm_fwd_async_event_cmpl_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41832,55 +44322,7 @@ struct hwrm_nvm_install_update_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Bit-mask of successfully installed items.\n-\t * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.\n-\t * A value of 0 indicates that no items were successfully installed.\n-\t */\n-\tuint64_t\tinstalled_items;\n-\t/* result is 8 b */\n-\tuint8_t\tresult;\n-\t/* There was no problem with the package installation. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS\n-\t/* problem_item is 8 b */\n-\tuint8_t\tproblem_item;\n-\t/* There was no problem with any packaged items. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/* There was a problem with the NVM package itself. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE\n-\t/* reset_required is 8 b */\n-\tuint8_t\treset_required;\n-\t/*\n-\t * No reset is required for installed/updated firmware or\n-\t * microcode to take effect.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/*\n-\t * A PCIe reset (e.g. system reboot) is\n-\t * required for newly installed/updated firmware or\n-\t * microcode to take effect.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * A controller power reset (e.g. system power-cycle) is\n-\t * required for newly installed/updated firmware or\n-\t * microcode to take effect. Some newly installed/updated\n-\t * firmware or microcode may still take effect upon the\n-\t * next PCIe reset.\n-\t */\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER\n-\tuint8_t\tunused_0[4];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -41891,31 +44333,13 @@ struct hwrm_nvm_install_update_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_install_update_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* Unable to complete operation due to fragmentation */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)\n-\t/* nvm is completely full. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/******************\n- * hwrm_nvm_flush *\n- ******************/\n+/**************************\n+ * hwrm_nvm_raw_write_blk *\n+ **************************/\n \n \n-/* hwrm_nvm_flush_input (size:128b/16B) */\n-struct hwrm_nvm_flush_input {\n+/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */\n+struct hwrm_nvm_raw_write_blk_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -41944,10 +44368,22 @@ struct hwrm_nvm_flush_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/*\n+\t * 64-bit Host Source Address.\n+\t * This is the location of the source data to be written.\n+\t */\n+\tuint64_t\thost_src_addr;\n+\t/*\n+\t * 32-bit Destination Address.\n+\t * This is the NVRAM byte-offset where the source data will be written to.\n+\t */\n+\tuint32_t\tdest_addr;\n+\t/* Length of data to be written, in bytes. */\n+\tuint32_t\tlen;\n } __rte_packed;\n \n-/* hwrm_nvm_flush_output (size:128b/16B) */\n-struct hwrm_nvm_flush_output {\n+/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */\n+struct hwrm_nvm_raw_write_blk_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -41967,29 +44403,13 @@ struct hwrm_nvm_flush_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_flush_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_flush_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* flush could not be performed */\n-\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)\n-\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/*************************\n- * hwrm_nvm_get_variable *\n- *************************/\n+/*****************\n+ * hwrm_nvm_read *\n+ *****************/\n \n \n-/* hwrm_nvm_get_variable_input (size:320b/40B) */\n-struct hwrm_nvm_get_variable_input {\n+/* hwrm_nvm_read_input (size:320b/40B) */\n+struct hwrm_nvm_read_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42019,49 +44439,22 @@ struct hwrm_nvm_get_variable_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * This is the host address where\n-\t * nvm variable will be stored\n-\t */\n-\tuint64_t\tdest_data_addr;\n-\t/* size of data in bits */\n-\tuint16_t\tdata_len;\n-\t/* nvm cfg option number */\n-\tuint16_t\toption_num;\n-\t/* reserved. */\n-\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n-\t/* reserved. */\n-\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \\\n-\t\tHWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF\n-\t/*\n-\t * Number of dimensions for this nvm configuration variable.\n-\t * This value indicates how many of the indexN values to use.\n-\t * A value of 0 means that none of the indexN values are valid.\n-\t * A value of 1 requires at index0 is valued, a value of 2\n-\t * requires that index0 and index1 are valid, and so forth\n-\t */\n-\tuint16_t\tdimensions;\n-\t/* index for the 1st dimensions */\n-\tuint16_t\tindex_0;\n-\t/* index for the 2nd dimensions */\n-\tuint16_t\tindex_1;\n-\t/* index for the 3rd dimensions */\n-\tuint16_t\tindex_2;\n-\t/* index for the 4th dimensions */\n-\tuint16_t\tindex_3;\n-\tuint8_t\tflags;\n-\t/*\n-\t * When this bit is set to 1, the factory default value will be returned,\n-\t * 0 returns the operational value.\n+\t * 64-bit Host Destination Address.\n+\t * This is the host address where the data will be written to.\n \t */\n-\t#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \\\n-\t\tUINT32_C(0x1)\n-\tuint8_t\tunused_0;\n+\tuint64_t\thost_dest_addr;\n+\t/* The 0-based index of the directory entry. */\n+\tuint16_t\tdir_idx;\n+\tuint8_t\tunused_0[2];\n+\t/* The NVRAM byte-offset to read from. */\n+\tuint32_t\toffset;\n+\t/* The length of the data to be read, in bytes. */\n+\tuint32_t\tlen;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_nvm_get_variable_output (size:128b/16B) */\n-struct hwrm_nvm_get_variable_output {\n+/* hwrm_nvm_read_output (size:128b/16B) */\n+struct hwrm_nvm_read_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42070,25 +44463,7 @@ struct hwrm_nvm_get_variable_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* size of data of the actual variable retrieved in bits */\n-\tuint16_t\tdata_len;\n-\t/*\n-\t * option_num is the option number for the data retrieved. It is possible in the\n-\t * future that the option number returned would be different than requested. This\n-\t * condition could occur if an option is deprecated and a new option id is defined\n-\t * with similar characteristics, but has a slightly different definition. This\n-\t * also makes it convenient for the caller to identify the variable result with\n-\t * the option id from the response.\n-\t */\n-\tuint16_t\toption_num;\n-\t/* reserved. */\n-\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n-\t/* reserved. */\n-\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \\\n-\t\tHWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -42099,33 +44474,13 @@ struct hwrm_nvm_get_variable_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_get_variable_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* variable does not exist */\n-\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)\n-\t/* configuration is corrupted and the variable cannot be saved */\n-\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)\n-\t/* length specified is too small */\n-\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)\n-\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/*************************\n- * hwrm_nvm_set_variable *\n- *************************/\n+/*********************\n+ * hwrm_nvm_raw_dump *\n+ *********************/\n \n \n-/* hwrm_nvm_set_variable_input (size:320b/40B) */\n-struct hwrm_nvm_set_variable_input {\n+/* hwrm_nvm_raw_dump_input (size:256b/32B) */\n+struct hwrm_nvm_raw_dump_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42155,70 +44510,18 @@ struct hwrm_nvm_set_variable_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * This is the host address where\n-\t * nvm variable will be copied from\n-\t */\n-\tuint64_t\tsrc_data_addr;\n-\t/* size of data in bits */\n-\tuint16_t\tdata_len;\n-\t/* nvm cfg option number */\n-\tuint16_t\toption_num;\n-\t/* reserved. */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n-\t/* reserved. */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \\\n-\t\tHWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF\n-\t/*\n-\t * Number of dimensions for this nvm configuration variable.\n-\t * This value indicates how many of the indexN values to use.\n-\t * A value of 0 means that none of the indexN values are valid.\n-\t * A value of 1 requires at index0 is valued, a value of 2\n-\t * requires that index0 and index1 are valid, and so forth\n+\t * 64-bit Host Destination Address.\n+\t * This is the host address where the data will be written to.\n \t */\n-\tuint16_t\tdimensions;\n-\t/* index for the 1st dimensions */\n-\tuint16_t\tindex_0;\n-\t/* index for the 2nd dimensions */\n-\tuint16_t\tindex_1;\n-\t/* index for the 3rd dimensions */\n-\tuint16_t\tindex_2;\n-\t/* index for the 4th dimensions */\n-\tuint16_t\tindex_3;\n-\tuint8_t\tflags;\n-\t/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \\\n-\t\tUINT32_C(0x1)\n-\t/* encryption method */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \\\n-\t\tUINT32_C(0xe)\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1\n-\t/* No encryption. */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \\\n-\t\t(UINT32_C(0x0) << 1)\n-\t/* one-way encryption. */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \\\n-\t\t(UINT32_C(0x1) << 1)\n-\t/* symmetric AES256 encryption. */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \\\n-\t\t(UINT32_C(0x2) << 1)\n-\t/* SHA1 digest appended to plaintext contents, for authentication */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \\\n-\t\t(UINT32_C(0x3) << 1)\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \\\n-\t\tHWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \\\n-\t\tUINT32_C(0x70)\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4\n-\t/* When this bit is 1, update the factory default region */\n-\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \\\n-\t\tUINT32_C(0x80)\n-\tuint8_t\tunused_0;\n+\tuint64_t\thost_dest_addr;\n+\t/* 32-bit NVRAM byte-offset to read from. */\n+\tuint32_t\toffset;\n+\t/* Total length of NVRAM contents to be read, in bytes. */\n+\tuint32_t\tlen;\n } __rte_packed;\n \n-/* hwrm_nvm_set_variable_output (size:128b/16B) */\n-struct hwrm_nvm_set_variable_output {\n+/* hwrm_nvm_raw_dump_output (size:128b/16B) */\n+struct hwrm_nvm_raw_dump_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42238,31 +44541,13 @@ struct hwrm_nvm_set_variable_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_set_variable_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* variable does not exist */\n-\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)\n-\t/* configuration is corrupted and the variable cannot be saved */\n-\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)\n-\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n /****************************\n- * hwrm_nvm_validate_option *\n+ * hwrm_nvm_get_dir_entries *\n ****************************/\n \n \n-/* hwrm_nvm_validate_option_input (size:320b/40B) */\n-struct hwrm_nvm_validate_option_input {\n+/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */\n+struct hwrm_nvm_get_dir_entries_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42292,43 +44577,14 @@ struct hwrm_nvm_validate_option_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * This is the host address where\n-\t * nvm variable will be copied from\n-\t */\n-\tuint64_t\tsrc_data_addr;\n-\t/* size of data in bits */\n-\tuint16_t\tdata_len;\n-\t/* nvm cfg option number */\n-\tuint16_t\toption_num;\n-\t/* reserved. */\n-\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \\\n-\t\tUINT32_C(0x0)\n-\t/* reserved. */\n-\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \\\n-\t\tHWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF\n-\t/*\n-\t * Number of dimensions for this nvm configuration variable.\n-\t * This value indicates how many of the indexN values to use.\n-\t * A value of 0 means that none of the indexN values are valid.\n-\t * A value of 1 requires at index0 is valued, a value of 2\n-\t * requires that index0 and index1 are valid, and so forth\n+\t * 64-bit Host Destination Address.\n+\t * This is the host address where the directory will be written.\n \t */\n-\tuint16_t\tdimensions;\n-\t/* index for the 1st dimensions */\n-\tuint16_t\tindex_0;\n-\t/* index for the 2nd dimensions */\n-\tuint16_t\tindex_1;\n-\t/* index for the 3rd dimensions */\n-\tuint16_t\tindex_2;\n-\t/* index for the 4th dimensions */\n-\tuint16_t\tindex_3;\n-\tuint8_t\tunused_0[2];\n+\tuint64_t\thost_dest_addr;\n } __rte_packed;\n \n-/* hwrm_nvm_validate_option_output (size:128b/16B) */\n-struct hwrm_nvm_validate_option_output {\n+/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */\n+struct hwrm_nvm_get_dir_entries_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42337,14 +44593,7 @@ struct hwrm_nvm_validate_option_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tresult;\n-\t/* indicates that the value provided for the option is not matching with the saved data. */\n-\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)\n-\t/* indicates that the value provided for the option is matching the saved data. */\n-\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)\n-\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \\\n-\t\tHWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -42355,27 +44604,13 @@ struct hwrm_nvm_validate_option_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_validate_option_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/****************\n- * hwrm_oem_cmd *\n- ****************/\n+/*************************\n+ * hwrm_nvm_get_dir_info *\n+ *************************/\n \n \n-/* hwrm_oem_cmd_input (size:1024b/128B) */\n-struct hwrm_oem_cmd_input {\n+/* hwrm_nvm_get_dir_info_input (size:128b/16B) */\n+struct hwrm_nvm_get_dir_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42404,14 +44639,10 @@ struct hwrm_oem_cmd_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tIANA;\n-\tuint32_t\tunused_0;\n-\t/* This field contains the vendor specific command data. */\n-\tuint32_t\toem_data[26];\n } __rte_packed;\n \n-/* hwrm_oem_cmd_output (size:768b/96B) */\n-struct hwrm_oem_cmd_output {\n+/* hwrm_nvm_get_dir_info_output (size:192b/24B) */\n+struct hwrm_nvm_get_dir_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42420,11 +44651,11 @@ struct hwrm_oem_cmd_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tIANA;\n-\tuint32_t\tunused_0;\n-\t/* This field contains the vendor specific response data. */\n-\tuint32_t\toem_data[18];\n-\tuint8_t\tunused_1[7];\n+\t/* Number of directory entries in the directory. */\n+\tuint32_t\tentries;\n+\t/* Size of each directory entry, in bytes. */\n+\tuint32_t\tentry_length;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -42435,150 +44666,13 @@ struct hwrm_oem_cmd_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*****************\n- * hwrm_fw_reset *\n+/******************\n+ * hwrm_nvm_write *\n ******************/\n \n \n-/* hwrm_fw_reset_input (size:192b/24B) */\n-struct hwrm_fw_reset_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t req_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t cmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t seq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t target_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t resp_addr;\n-\t/* Type of embedded processor. */\n-\tuint8_t embedded_proc_type;\n-\t/* Boot Processor */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \\\n-\t\tUINT32_C(0x0)\n-\t/* Management Processor */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \\\n-\t\tUINT32_C(0x1)\n-\t/* Network control processor */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \\\n-\t\tUINT32_C(0x2)\n-\t/* RoCE control processor */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \\\n-\t\tUINT32_C(0x3)\n-\t/*\n-\t * Host (in multi-host environment): This is only valid if requester is IPC.\n-\t * Reinit host hardware resources and PCIe.\n-\t */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \\\n-\t\tUINT32_C(0x4)\n-\t/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \\\n-\t\tUINT32_C(0x5)\n-\t/* Reset all blocks of the chip (including all processors) */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \\\n-\t\tUINT32_C(0x6)\n-\t/*\n-\t * Host (in multi-host environment): This is only valid if requester is IPC.\n-\t * Reinit host hardware resources.\n-\t */\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \\\n-\t\tUINT32_C(0x7)\n-\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \\\n-\t\tHWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT\n-\t/* Type of self reset. */\n-\tuint8_t selfrst_status;\n-\t/* No Self Reset */\n-\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \\\n-\t\tUINT32_C(0x0)\n-\t/* Self Reset as soon as possible to do so safely */\n-\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \\\n-\t\tUINT32_C(0x1)\n-\t/* Self Reset on PCIe Reset */\n-\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n-\t\tUINT32_C(0x2)\n-\t/* Self Reset immediately after notification to all clients. */\n-\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n-\t\tUINT32_C(0x3)\n-\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \\\n-\t\tHWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n-\t/*\n-\t * Indicate which host is being reset. 0 means first host.\n-\t * Only valid when embedded_proc_type is host in multihost\n-\t * environment\n-\t */\n-\tuint8_t host_idx;\n-\tuint8_t flags;\n-\t/*\n-\t * When this bit is '1', then the core firmware initiates\n-\t * the reset only after graceful shut down of all registered instances.\n-\t * If not, the device will continue with the existing firmware.\n-\t */\n-\t#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)\n-\tuint8_t unused_0[4];\n-} __rte_packed;\n-\n-/* hwrm_fw_reset_output (size:128b/16B) */\n-struct hwrm_fw_reset_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t error_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t req_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t seq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t resp_len;\n-\t/* Type of self reset. */\n-\tuint8_t selfrst_status;\n-\t/* No Self Reset */\n-\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \\\n-\t\tUINT32_C(0x0)\n-\t/* Self Reset as soon as possible to do so safely */\n-\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \\\n-\t\tUINT32_C(0x1)\n-\t/* Self Reset on PCIe Reset */\n-\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n-\t\tUINT32_C(0x2)\n-\t/* Self Reset immediately after notification to all clients. */\n-\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n-\t\tUINT32_C(0x3)\n-\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \\\n-\t\tHWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n-\tuint8_t unused_0[6];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t valid;\n-} __rte_packed;\n-\n-/**********************\n- * hwrm_port_ts_query *\n- ***********************/\n-\n-\n-/* hwrm_port_ts_query_input (size:192b/24B) */\n-struct hwrm_port_ts_query_input {\n+/* hwrm_nvm_write_input (size:384b/48B) */\n+struct hwrm_nvm_write_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42607,31 +44701,49 @@ struct hwrm_port_ts_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n \t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * 64-bit Host Source Address.\n+\t * This is where the source data is.\n \t */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH\t\t0x1UL\n-\t/* tx path */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX\t\t0x0UL\n-\t/* rx path */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX\t\t0x1UL\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST\t\\\n-\t\tHWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX\n+\tuint64_t\thost_src_addr;\n+\t/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */\n+\tuint16_t\tdir_type;\n \t/*\n-\t * If set, the response includes the current value of the free\n-\t * running timer.\n+\t * Directory ordinal.\n+\t * The 0-based instance of the combined Directory Entry Type and Extension.\n \t */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME\t0x2UL\n-\t/* Port ID of port that is being queried. */\n-\tuint16_t\tport_id;\n-\tuint8_t\t\tunused_0[2];\n+\tuint16_t\tdir_ordinal;\n+\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */\n+\tuint16_t\tdir_ext;\n+\t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */\n+\tuint16_t\tdir_attr;\n+\t/*\n+\t * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.\n+\t * The data length stored in the directory entry will be updated to reflect this value once the write is complete.\n+\t */\n+\tuint32_t\tdir_data_length;\n+\t/* Option. */\n+\tuint16_t\toption;\n+\tuint16_t\tflags;\n+\t/*\n+\t * When this bit is '1', the original active image\n+\t * will not be removed. TBD: what purpose is this?\n+\t */\n+\t#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).\n+\t * If this value is less than the specified data length, it will be ignored.\n+\t * The response will contain the actual allocated item length, which may be greater than the requested item length.\n+\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate\n+\t * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).\n+\t */\n+\tuint32_t\tdir_item_length;\n+\tuint32_t\tunused_0;\n } __rte_packed;\n \n-/* hwrm_port_ts_query_output (size:192b/24B) */\n-struct hwrm_port_ts_query_output {\n+/* hwrm_nvm_write_output (size:128b/16B) */\n+struct hwrm_nvm_write_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42641,13 +44753,13 @@ struct hwrm_port_ts_query_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Timestamp value of PTP message captured, or current value of\n-\t * free running timer.\n+\t * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.\n+\t * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.\n \t */\n-\tuint32_t\tptp_msg_ts[2];\n-\t/* Sequence ID of the PTP message captured. */\n-\tuint16_t\tptp_msg_seqid;\n-\tuint8_t\t\tunused_0[5];\n+\tuint32_t\tdir_item_length;\n+\t/* The directory index of the created or modified item. */\n+\tuint16_t\tdir_idx;\n+\tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -42655,65 +44767,34 @@ struct hwrm_port_ts_query_output {\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\t\tvalid;\n+\tuint8_t\tvalid;\n } __rte_packed;\n \n-/*\n- * This structure is fixed at the beginning of the ChiMP SRAM (GRC\n- * offset: 0x31001F0). Host software is expected to read from this\n- * location for a defined signature. If it exists, the software can\n- * assume the presence of this structure and the validity of the\n- * FW_STATUS location in the next field.\n- */\n-/* hcomm_status (size:64b/8B) */\n-struct hcomm_status {\n-\tuint32_t\tsig_ver;\n-\t/*\n-\t * This field defines the version of the structure. The latest\n-\t * version value is 1.\n-\t */\n-\t#define HCOMM_STATUS_VER_MASK\t\tUINT32_C(0xff)\n-\t#define HCOMM_STATUS_VER_SFT\t\t0\n-\t#define HCOMM_STATUS_VER_LATEST\t\tUINT32_C(0x1)\n-\t#define HCOMM_STATUS_VER_LAST\t\tHCOMM_STATUS_VER_LATEST\n-\t/*\n-\t * This field is to store the signature value to indicate the\n-\t * presence of the structure.\n-\t */\n-\t#define HCOMM_STATUS_SIGNATURE_MASK\tUINT32_C(0xffffff00)\n-\t#define HCOMM_STATUS_SIGNATURE_SFT\t8\n-\t#define HCOMM_STATUS_SIGNATURE_VAL\t(UINT32_C(0x484353) << 8)\n-\t#define HCOMM_STATUS_SIGNATURE_LAST\tHCOMM_STATUS_SIGNATURE_VAL\n-\tuint32_t\tfw_status_loc;\n-\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK\tUINT32_C(0x3)\n-\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT\t0\n-\t/* PCIE configuration space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG\tUINT32_C(0x0)\n-\t/* GRC space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC\tUINT32_C(0x1)\n-\t/* BAR0 space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0\tUINT32_C(0x2)\n-\t/* BAR1 space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\tUINT32_C(0x3)\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST\t\\\n-\t\tHCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\n+/* hwrm_nvm_write_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_write_cmd_err {\n \t/*\n-\t * This offset where the fw_status register is located. The value\n-\t * is generally 4-byte aligned.\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n \t */\n-\t#define HCOMM_STATUS_TRUE_OFFSET_MASK\t\tUINT32_C(0xfffffffc)\n-\t#define HCOMM_STATUS_TRUE_OFFSET_SFT\t\t2\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* Unable to complete operation due to fragmentation */\n+\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)\n+\t/* nvm is completely full. */\n+\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)\n+\t#define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE\n+\tuint8_t\tunused_0[7];\n } __rte_packed;\n-/* This is the GRC offset where the hcomm_status struct resides. */\n-#define HCOMM_STATUS_STRUCT_LOC\t\t0x31001F0UL\n \n-/**************************\n- * hwrm_cfa_counter_qcaps *\n- **************************/\n+/*******************\n+ * hwrm_nvm_modify *\n+ *******************/\n \n \n-/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */\n-struct hwrm_cfa_counter_qcaps_input {\n+/* hwrm_nvm_modify_input (size:320b/40B) */\n+struct hwrm_nvm_modify_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42742,10 +44823,42 @@ struct hwrm_cfa_counter_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/*\n+\t * 64-bit Host Source Address.\n+\t * This is where the modified data is.\n+\t */\n+\tuint64_t\thost_src_addr;\n+\t/* 16-bit directory entry index. */\n+\tuint16_t\tdir_idx;\n+\tuint16_t\tflags;\n+\t/*\n+\t * This flag indicates the sender wants to modify a continuous NVRAM\n+\t * area using a batch of this HWRM requests. The offset of a request\n+\t * must be continuous to the end of previous request's. Firmware does\n+\t * not update the directory entry until receiving the last request,\n+\t * which is indicated by the batch_last flag.\n+\t * This flag is set usually when a sender does not have a block of\n+\t * memory that is big enough to hold the entire NVRAM data for send\n+\t * at one time.\n+\t */\n+\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)\n+\t/*\n+\t * This flag can be used only when the batch_mode flag is set.\n+\t * It indicates this request is the last of batch requests.\n+\t */\n+\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)\n+\t/* 32-bit NVRAM byte-offset to modify content from. */\n+\tuint32_t\toffset;\n+\t/*\n+\t * Length of data to be modified, in bytes. The length shall\n+\t * be non-zero.\n+\t */\n+\tuint32_t\tlen;\n+\tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */\n-struct hwrm_cfa_counter_qcaps_output {\n+/* hwrm_nvm_modify_output (size:128b/16B) */\n+struct hwrm_nvm_modify_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42754,46 +44867,7 @@ struct hwrm_cfa_counter_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/* Enumeration denoting the supported CFA counter format. */\n-\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \\\n-\t\tUINT32_C(0x1)\n-\t/* CFA counter types are not supported. */\n-\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/* 64-bit packet counters followed by 64-bit byte counters format. */\n-\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \\\n-\t\tHWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT\n-\tuint32_t\tunused_0;\n-\t/* Minimum guaranteed number of flow counters supported for this function, in RX direction. */\n-\tuint32_t\tmin_rx_fc;\n-\t/* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */\n-\tuint32_t\tmax_rx_fc;\n-\t/* Minimum guaranteed number of flow counters supported for this function, in TX direction. */\n-\tuint32_t\tmin_tx_fc;\n-\t/* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */\n-\tuint32_t\tmax_tx_fc;\n-\t/* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */\n-\tuint32_t\tmin_rx_efc;\n-\t/* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */\n-\tuint32_t\tmax_rx_efc;\n-\t/* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */\n-\tuint32_t\tmin_tx_efc;\n-\t/* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */\n-\tuint32_t\tmax_tx_efc;\n-\t/* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */\n-\tuint32_t\tmin_rx_mdc;\n-\t/* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */\n-\tuint32_t\tmax_rx_mdc;\n-\t/* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */\n-\tuint32_t\tmin_tx_mdc;\n-\t/* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */\n-\tuint32_t\tmax_tx_mdc;\n-\t/* Maximum guaranteed number of flow counters which can be used during flow alloc. */\n-\tuint32_t\tmax_flow_alloc_fc;\n-\tuint8_t\tunused_1[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -42804,13 +44878,13 @@ struct hwrm_cfa_counter_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/************************\n- * hwrm_cfa_counter_cfg *\n- ************************/\n+/***************************\n+ * hwrm_nvm_find_dir_entry *\n+ ***************************/\n \n \n-/* hwrm_cfa_counter_cfg_input (size:256b/32B) */\n-struct hwrm_cfa_counter_cfg_input {\n+/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */\n+struct hwrm_nvm_find_dir_entry_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42839,64 +44913,42 @@ struct hwrm_cfa_counter_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint16_t\tflags;\n-\t/* Enumeration denoting the configuration mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \\\n-\t\tUINT32_C(0x1)\n-\t/* Disable the configuration mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \\\n-\t\tUINT32_C(0x0)\n-\t/* Enable the configuration mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \\\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the dir_idx_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \\\n \t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \\\n-\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE\n-\t/* Enumeration denoting the RX, TX type of the resource. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \\\n-\t\tUINT32_C(0x2)\n-\t/* Tx path. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \\\n-\t\t(UINT32_C(0x0) << 1)\n-\t/* Rx path. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \\\n-\t\t(UINT32_C(0x1) << 1)\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX\n-\t/* Enumeration denoting the data transfer mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \\\n-\t\tUINT32_C(0xc)\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2\n-\t/* Push mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \\\n-\t\t(UINT32_C(0x0) << 2)\n-\t/* Pull mode. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \\\n-\t\t(UINT32_C(0x1) << 2)\n-\t/* Pull on async update. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \\\n-\t\t(UINT32_C(0x2) << 2)\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \\\n-\t\tHWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC\n-\tuint16_t\tcounter_type;\n-\t/* Flow counters. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)\n-\t/* Extended flow counters. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)\n-\t/* Meter drop counters. */\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)\n-\t#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \\\n-\t\tHWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC\n-\t/* Ctx memory handle to be used for the counter. */\n-\tuint16_t\tctx_id;\n-\t/* Counter update cadence hint (only in Push mode). */\n-\tuint16_t\tupdate_tmr_ms;\n-\t/* Total number of entries. */\n-\tuint32_t\tnum_entries;\n-\tuint32_t\tunused_0;\n+\t/* Directory Entry Index */\n+\tuint16_t\tdir_idx;\n+\t/* Directory Entry (Image) Type */\n+\tuint16_t\tdir_type;\n+\t/*\n+\t * Directory ordinal.\n+\t * The instance of this Directory Type\n+\t */\n+\tuint16_t\tdir_ordinal;\n+\t/* The Directory Entry Extension flags. */\n+\tuint16_t\tdir_ext;\n+\t/* This value indicates the search option using dir_ordinal. */\n+\tuint8_t\topt_ordinal;\n+\t/* This value indicates the search option using dir_ordinal. */\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0\n+\t/* Equal to specified ordinal value. */\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)\n+\t/* Greater than or equal to specified ordinal value */\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)\n+\t/* Greater than specified ordinal value */\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)\n+\t#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \\\n+\t\tHWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT\n+\tuint8_t\tunused_0[3];\n } __rte_packed;\n \n-/* hwrm_cfa_counter_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_counter_cfg_output {\n+/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */\n+struct hwrm_nvm_find_dir_entry_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42905,6 +44957,19 @@ struct hwrm_cfa_counter_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* Allocated NVRAM for this directory entry, in bytes. */\n+\tuint32_t\tdir_item_length;\n+\t/* Size of the stored data for this directory entry, in bytes. */\n+\tuint32_t\tdir_data_length;\n+\t/*\n+\t * Firmware version.\n+\t * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.\n+\t */\n+\tuint32_t\tfw_ver;\n+\t/* Directory ordinal. */\n+\tuint16_t\tdir_ordinal;\n+\t/* Directory Entry Index */\n+\tuint16_t\tdir_idx;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -42916,13 +44981,13 @@ struct hwrm_cfa_counter_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***************************\n- * hwrm_cfa_counter_qstats *\n- ***************************/\n+/****************************\n+ * hwrm_nvm_erase_dir_entry *\n+ ****************************/\n \n \n-/* hwrm_cfa_counter_qstats_input (size:320b/40B) */\n-struct hwrm_cfa_counter_qstats_input {\n+/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */\n+struct hwrm_nvm_erase_dir_entry_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -42951,27 +45016,13 @@ struct hwrm_cfa_counter_qstats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint16_t\tflags;\n-\t/* Enumeration denoting the RX, TX type of the resource. */\n-\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* Tx path. */\n-\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* Rx path. */\n-\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX\n-\tuint16_t\tcounter_type;\n-\tuint16_t\tinput_flow_ctx_id;\n-\tuint16_t\tnum_entries;\n-\tuint16_t\tdelta_time_ms;\n-\tuint16_t\tmeter_instance_id;\n-\tuint16_t\tmdc_ctx_id;\n-\tuint8_t\tunused_0[2];\n-\tuint64_t\texpected_count;\n+\t/* Directory Entry Index */\n+\tuint16_t\tdir_idx;\n+\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_cfa_counter_qstats_output (size:128b/16B) */\n-struct hwrm_cfa_counter_qstats_output {\n+/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */\n+struct hwrm_nvm_erase_dir_entry_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -42991,13 +45042,13 @@ struct hwrm_cfa_counter_qstats_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_cfa_pair_alloc *\n- ***********************/\n+/*************************\n+ * hwrm_nvm_get_dev_info *\n+ *************************/\n \n \n-/* hwrm_cfa_pair_alloc_input (size:576b/72B) */\n-struct hwrm_cfa_pair_alloc_input {\n+/* hwrm_nvm_get_dev_info_input (size:128b/16B) */\n+struct hwrm_nvm_get_dev_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -43026,104 +45077,256 @@ struct hwrm_cfa_pair_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,\n-\t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n+} __rte_packed;\n+\n+/* hwrm_nvm_get_dev_info_output (size:640b/80B) */\n+struct hwrm_nvm_get_dev_info_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Manufacturer ID. */\n+\tuint16_t\tmanufacturer_id;\n+\t/* Device ID. */\n+\tuint16_t\tdevice_id;\n+\t/* Sector size of the NVRAM device. */\n+\tuint32_t\tsector_size;\n+\t/* Total size, in bytes of the NVRAM device. */\n+\tuint32_t\tnvram_size;\n+\tuint32_t\treserved_size;\n+\t/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */\n+\tuint32_t\tavailable_size;\n+\t/* This field represents the major version of NVM cfg */\n+\tuint8_t\tnvm_cfg_ver_maj;\n+\t/* This field represents the minor version of NVM cfg */\n+\tuint8_t\tnvm_cfg_ver_min;\n+\t/* This field represents the update version of NVM cfg */\n+\tuint8_t\tnvm_cfg_ver_upd;\n+\tuint8_t\tflags;\n+\t/*\n+\t * If set to 1, firmware will provide various firmware version\n+\t * information stored in the flash.\n \t */\n-\tuint16_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \\\n-\t\tUINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \\\n+\t#define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \\\n \t\tUINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \\\n-\t\tUINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \\\n-\t\tUINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \\\n-\t\tUINT32_C(0x4)\n-\t/* Modify existing rep2fn pair and move pair to new PF. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \\\n-\t\tUINT32_C(0x5)\n-\t/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \\\n-\t\tUINT32_C(0x6)\n-\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \\\n-\t\tUINT32_C(0x7)\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \\\n-\t\tHWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_a_id;\n-\t/* Logical Host (0xff-local host). */\n-\tuint8_t\thost_b_id;\n-\t/* Logical PF (0xff-PF for command channel). */\n-\tuint8_t\tpf_b_id;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_b_id;\n-\t/* Loopback port (0xff-internal loopback), valid for mode-3. */\n-\tuint8_t\tport_id;\n-\t/* Priority used for encap of loopback packets valid for mode-3. */\n-\tuint8_t\tpri;\n-\t/* New PF for rep2fn modify, valid for mode 5. */\n-\tuint16_t\tnew_pf_fid;\n+\t/*\n+\t * This field represents the board package name stored in the flash.\n+\t * (ASCII chars with NULL at the end).\n+\t */\n+\tchar\tpkg_name[16];\n+\t/*\n+\t * This field represents the major version of HWRM firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\thwrm_fw_major;\n+\t/*\n+\t * This field represents the minor version of HWRM firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\thwrm_fw_minor;\n+\t/*\n+\t * This field represents the build version of HWRM firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\thwrm_fw_build;\n+\t/*\n+\t * This field can be used to represent firmware branches or customer\n+\t * specific releases tied to a specific (major, minor, build) version\n+\t * of the HWRM firmware.\n+\t */\n+\tuint16_t\thwrm_fw_patch;\n+\t/*\n+\t * This field represents the major version of mgmt firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\tmgmt_fw_major;\n+\t/*\n+\t * This field represents the minor version of mgmt firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\tmgmt_fw_minor;\n+\t/*\n+\t * This field represents the build version of mgmt firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\tmgmt_fw_build;\n+\t/*\n+\t * This field can be used to represent firmware branches or customer\n+\t * specific releases tied to a specific (major, minor, build) version\n+\t * of the mgmt firmware.\n+\t */\n+\tuint16_t\tmgmt_fw_patch;\n+\t/*\n+\t * This field represents the major version of roce firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\troce_fw_major;\n+\t/*\n+\t * This field represents the minor version of roce firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\troce_fw_minor;\n+\t/*\n+\t * This field represents the build version of roce firmware, stored in\n+\t * the flash.\n+\t */\n+\tuint16_t\troce_fw_build;\n+\t/*\n+\t * This field can be used to represent firmware branches or customer\n+\t * specific releases tied to a specific (major, minor, build) version\n+\t * of the roce firmware.\n+\t */\n+\tuint16_t\troce_fw_patch;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_nvm_mod_dir_entry *\n+ **************************/\n+\n+\n+/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */\n+struct hwrm_nvm_mod_dir_entry_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n \tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the q_ab field to be\n+\t * This bit must be '1' for the checksum field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)\n+\t#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)\n+\t/* Directory Entry Index */\n+\tuint16_t\tdir_idx;\n \t/*\n-\t * This bit must be '1' for the q_ba field to be\n-\t * configured.\n+\t * Directory ordinal.\n+\t * The (0-based) instance of this Directory Type.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)\n+\tuint16_t\tdir_ordinal;\n+\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */\n+\tuint16_t\tdir_ext;\n+\t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */\n+\tuint16_t\tdir_attr;\n \t/*\n-\t * This bit must be '1' for the fc_ab field to be\n-\t * configured.\n+\t * If valid, then this field updates the checksum\n+\t * value of the content in the directory entry.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)\n+\tuint32_t\tchecksum;\n+} __rte_packed;\n+\n+/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */\n+struct hwrm_nvm_mod_dir_entry_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This bit must be '1' for the fc_ba field to be\n-\t * configured.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_nvm_verify_update *\n+ **************************/\n+\n+\n+/* hwrm_nvm_verify_update_input (size:192b/24B) */\n+struct hwrm_nvm_verify_update_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * The q_ab value specifies the logical index of the TX/RX CoS\n-\t * queue to be assigned for traffic in the A to B direction of\n-\t * the interface pair. The default value is 0.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tq_ab;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * The q_ba value specifies the logical index of the TX/RX CoS\n-\t * queue to be assigned for traffic in the B to A direction of\n-\t * the interface pair. The default value is 1.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tq_ba;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Specifies whether RX ring flow control is disabled (0) or enabled\n-\t * (1) in the A to B direction. The default value is 0, meaning that\n-\t * packets will be dropped when the B-side RX rings are full.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint8_t\tfc_ab;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Specifies whether RX ring flow control is disabled (0) or enabled\n-\t * (1) in the B to A direction. The default value is 1, meaning that\n-\t * the RX CoS queue will be flow controlled when the A-side RX rings\n-\t * are full.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint8_t\tfc_ba;\n-\tuint8_t\tunused_1[4];\n+\tuint64_t\tresp_addr;\n+\t/* Directory Entry Type, to be verified. */\n+\tuint16_t\tdir_type;\n+\t/*\n+\t * Directory ordinal.\n+\t * The instance of the Directory Type to be verified.\n+\t */\n+\tuint16_t\tdir_ordinal;\n+\t/*\n+\t * The Directory Entry Extension flags.\n+\t * The \"UPDATE\" extension flag must be set in this value.\n+\t * A corresponding directory entry with the same type and ordinal values but *without*\n+\t * the \"UPDATE\" extension flag must also exist. The other flags of the extension must\n+\t * be identical between the active and update entries.\n+\t */\n+\tuint16_t\tdir_ext;\n+\tuint8_t\tunused_0[2];\n } __rte_packed;\n \n-/* hwrm_cfa_pair_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_pair_alloc_output {\n+/* hwrm_nvm_verify_update_output (size:128b/16B) */\n+struct hwrm_nvm_verify_update_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -43132,18 +45335,10 @@ struct hwrm_cfa_pair_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Only valid for modes 1 and 2. */\n-\tuint16_t\trx_cfa_code_a;\n-\t/* Only valid for modes 1 and 2. */\n-\tuint16_t\ttx_cfa_action_a;\n-\t/* Only valid for mode 2. */\n-\tuint16_t\trx_cfa_code_b;\n-\t/* Only valid for mode 2. */\n-\tuint16_t\ttx_cfa_action_b;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -43151,13 +45346,13 @@ struct hwrm_cfa_pair_alloc_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_cfa_pair_free *\n- **********************/\n+/***************************\n+ * hwrm_nvm_install_update *\n+ ***************************/\n \n \n-/* hwrm_cfa_pair_free_input (size:448b/56B) */\n-struct hwrm_cfa_pair_free_input {\n+/* hwrm_nvm_install_update_input (size:192b/24B) */\n+struct hwrm_nvm_install_update_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -43186,40 +45381,181 @@ struct hwrm_cfa_pair_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n-\t/* Logical PF (0xff-PF for command channel). */\n-\tuint8_t\tpf_b_id;\n-\tuint8_t\tunused_0[3];\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_id;\n \t/*\n-\t * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,\n-\t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n+\t * Installation type. If the value 3 through 0xffff is used,\n+\t * only packaged items with that type value will be installed and\n+\t * conditional installation directives for those packaged items\n+\t * will be over-ridden (i.e. 'create' or 'replace' will be treated\n+\t * as 'install').\n \t */\n-\tuint16_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n-\t/* Modify existing rep2fn pair and move pair to new PF. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)\n-\t/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)\n-\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)\n-\t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \\\n-\t\tHWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW\n+\tuint32_t\tinstall_type;\n+\t/*\n+\t * Perform a normal package installation. Conditional installation\n+\t * directives (e.g. 'create' and 'replace') of packaged items\n+\t * will be followed.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)\n+\t/*\n+\t * Install all packaged items regardless of installation directive\n+\t * (i.e. treat all packaged items as though they have an installation\n+\t * directive of 'install').\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \\\n+\t\tUINT32_C(0xffffffff)\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \\\n+\t\tHWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL\n+\tuint16_t\tflags;\n+\t/* If set to 1, then securely erase all unused locations in persistent storage. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, then unspecified images, images not in the package file, will be safely deleted.\n+\t * When combined with erase_unused_space then unspecified images will be securely erased.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, FW will defragment the NVM if defragmentation is required for the update.\n+\t * Allow additional time for this command to complete if this bit is set to 1.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, FW will verify the package in the \"UPDATE\" NVM item\n+\t * without installing it. This flag is for FW internal use only.\n+\t * Users should not set this flag. The request will otherwise fail.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \\\n+\t\tUINT32_C(0x8)\n+\tuint8_t\tunused_0[2];\n } __rte_packed;\n \n-/* hwrm_cfa_pair_free_output (size:128b/16B) */\n-struct hwrm_cfa_pair_free_output {\n+/* hwrm_nvm_install_update_output (size:192b/24B) */\n+struct hwrm_nvm_install_update_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Bit-mask of successfully installed items.\n+\t * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.\n+\t * A value of 0 indicates that no items were successfully installed.\n+\t */\n+\tuint64_t\tinstalled_items;\n+\t/* result is 8 b */\n+\tuint8_t\tresult;\n+\t/* There was no problem with the package installation. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \\\n+\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS\n+\t/* problem_item is 8 b */\n+\tuint8_t\tproblem_item;\n+\t/* There was no problem with any packaged items. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* There was a problem with the NVM package itself. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \\\n+\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE\n+\t/* reset_required is 8 b */\n+\tuint8_t\treset_required;\n+\t/*\n+\t * No reset is required for installed/updated firmware or\n+\t * microcode to take effect.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * A PCIe reset (e.g. system reboot) is\n+\t * required for newly installed/updated firmware or\n+\t * microcode to take effect.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * A controller power reset (e.g. system power-cycle) is\n+\t * required for newly installed/updated firmware or\n+\t * microcode to take effect. Some newly installed/updated\n+\t * firmware or microcode may still take effect upon the\n+\t * next PCIe reset.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \\\n+\t\tHWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER\n+\tuint8_t\tunused_0[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_install_update_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* Unable to complete operation due to fragmentation */\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)\n+\t/* nvm is completely full. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/******************\n+ * hwrm_nvm_flush *\n+ ******************/\n+\n+\n+/* hwrm_nvm_flush_input (size:128b/16B) */\n+struct hwrm_nvm_flush_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __rte_packed;\n+\n+/* hwrm_nvm_flush_output (size:128b/16B) */\n+struct hwrm_nvm_flush_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -43231,7 +45567,7 @@ struct hwrm_cfa_pair_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -43239,4 +45575,743 @@ struct hwrm_cfa_pair_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/* hwrm_nvm_flush_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_flush_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* flush could not be performed */\n+\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)\n+\t#define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/*************************\n+ * hwrm_nvm_get_variable *\n+ *************************/\n+\n+\n+/* hwrm_nvm_get_variable_input (size:320b/40B) */\n+struct hwrm_nvm_get_variable_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * This is the host address where\n+\t * nvm variable will be stored\n+\t */\n+\tuint64_t\tdest_data_addr;\n+\t/* size of data in bits */\n+\tuint16_t\tdata_len;\n+\t/* nvm cfg option number */\n+\tuint16_t\toption_num;\n+\t/* reserved. */\n+\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n+\t/* reserved. */\n+\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \\\n+\t\tHWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF\n+\t/*\n+\t * Number of dimensions for this nvm configuration variable.\n+\t * This value indicates how many of the indexN values to use.\n+\t * A value of 0 means that none of the indexN values are valid.\n+\t * A value of 1 requires at index0 is valued, a value of 2\n+\t * requires that index0 and index1 are valid, and so forth\n+\t */\n+\tuint16_t\tdimensions;\n+\t/* index for the 1st dimensions */\n+\tuint16_t\tindex_0;\n+\t/* index for the 2nd dimensions */\n+\tuint16_t\tindex_1;\n+\t/* index for the 3rd dimensions */\n+\tuint16_t\tindex_2;\n+\t/* index for the 4th dimensions */\n+\tuint16_t\tindex_3;\n+\tuint8_t\tflags;\n+\t/*\n+\t * When this bit is set to 1, the factory default value will be returned,\n+\t * 0 returns the operational value.\n+\t */\n+\t#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0;\n+} __rte_packed;\n+\n+/* hwrm_nvm_get_variable_output (size:128b/16B) */\n+struct hwrm_nvm_get_variable_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* size of data of the actual variable retrieved in bits */\n+\tuint16_t\tdata_len;\n+\t/*\n+\t * option_num is the option number for the data retrieved. It is possible in the\n+\t * future that the option number returned would be different than requested. This\n+\t * condition could occur if an option is deprecated and a new option id is defined\n+\t * with similar characteristics, but has a slightly different definition. This\n+\t * also makes it convenient for the caller to identify the variable result with\n+\t * the option id from the response.\n+\t */\n+\tuint16_t\toption_num;\n+\t/* reserved. */\n+\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n+\t/* reserved. */\n+\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \\\n+\t\tHWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_get_variable_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* variable does not exist */\n+\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)\n+\t/* configuration is corrupted and the variable cannot be saved */\n+\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)\n+\t/* length specified is too small */\n+\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)\n+\t#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/*************************\n+ * hwrm_nvm_set_variable *\n+ *************************/\n+\n+\n+/* hwrm_nvm_set_variable_input (size:320b/40B) */\n+struct hwrm_nvm_set_variable_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * This is the host address where\n+\t * nvm variable will be copied from\n+\t */\n+\tuint64_t\tsrc_data_addr;\n+\t/* size of data in bits */\n+\tuint16_t\tdata_len;\n+\t/* nvm cfg option number */\n+\tuint16_t\toption_num;\n+\t/* reserved. */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)\n+\t/* reserved. */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \\\n+\t\tHWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF\n+\t/*\n+\t * Number of dimensions for this nvm configuration variable.\n+\t * This value indicates how many of the indexN values to use.\n+\t * A value of 0 means that none of the indexN values are valid.\n+\t * A value of 1 requires at index0 is valued, a value of 2\n+\t * requires that index0 and index1 are valid, and so forth\n+\t */\n+\tuint16_t\tdimensions;\n+\t/* index for the 1st dimensions */\n+\tuint16_t\tindex_0;\n+\t/* index for the 2nd dimensions */\n+\tuint16_t\tindex_1;\n+\t/* index for the 3rd dimensions */\n+\tuint16_t\tindex_2;\n+\t/* index for the 4th dimensions */\n+\tuint16_t\tindex_3;\n+\tuint8_t\tflags;\n+\t/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \\\n+\t\tUINT32_C(0x1)\n+\t/* encryption method */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \\\n+\t\tUINT32_C(0xe)\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1\n+\t/* No encryption. */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* one-way encryption. */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/* symmetric AES256 encryption. */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t/* SHA1 digest appended to plaintext contents, for authentication */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \\\n+\t\tHWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \\\n+\t\tUINT32_C(0x70)\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4\n+\t/* When this bit is 1, update the factory default region */\n+\t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \\\n+\t\tUINT32_C(0x80)\n+\tuint8_t\tunused_0;\n+} __rte_packed;\n+\n+/* hwrm_nvm_set_variable_output (size:128b/16B) */\n+struct hwrm_nvm_set_variable_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_set_variable_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* variable does not exist */\n+\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)\n+\t/* configuration is corrupted and the variable cannot be saved */\n+\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)\n+\t#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_nvm_validate_option *\n+ ****************************/\n+\n+\n+/* hwrm_nvm_validate_option_input (size:320b/40B) */\n+struct hwrm_nvm_validate_option_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * This is the host address where\n+\t * nvm variable will be copied from\n+\t */\n+\tuint64_t\tsrc_data_addr;\n+\t/* size of data in bits */\n+\tuint16_t\tdata_len;\n+\t/* nvm cfg option number */\n+\tuint16_t\toption_num;\n+\t/* reserved. */\n+\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* reserved. */\n+\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \\\n+\t\tHWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF\n+\t/*\n+\t * Number of dimensions for this nvm configuration variable.\n+\t * This value indicates how many of the indexN values to use.\n+\t * A value of 0 means that none of the indexN values are valid.\n+\t * A value of 1 requires at index0 is valued, a value of 2\n+\t * requires that index0 and index1 are valid, and so forth\n+\t */\n+\tuint16_t\tdimensions;\n+\t/* index for the 1st dimensions */\n+\tuint16_t\tindex_0;\n+\t/* index for the 2nd dimensions */\n+\tuint16_t\tindex_1;\n+\t/* index for the 3rd dimensions */\n+\tuint16_t\tindex_2;\n+\t/* index for the 4th dimensions */\n+\tuint16_t\tindex_3;\n+\tuint8_t\tunused_0[2];\n+} __rte_packed;\n+\n+/* hwrm_nvm_validate_option_output (size:128b/16B) */\n+struct hwrm_nvm_validate_option_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tresult;\n+\t/* indicates that the value provided for the option is not matching with the saved data. */\n+\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)\n+\t/* indicates that the value provided for the option is matching the saved data. */\n+\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)\n+\t#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \\\n+\t\tHWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH\n+\tuint8_t\tunused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_validate_option_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/****************\n+ * hwrm_oem_cmd *\n+ ****************/\n+\n+\n+/* hwrm_oem_cmd_input (size:1024b/128B) */\n+struct hwrm_oem_cmd_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tIANA;\n+\tuint32_t\tunused_0;\n+\t/* This field contains the vendor specific command data. */\n+\tuint32_t\toem_data[26];\n+} __rte_packed;\n+\n+/* hwrm_oem_cmd_output (size:768b/96B) */\n+struct hwrm_oem_cmd_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tIANA;\n+\tuint32_t\tunused_0;\n+\t/* This field contains the vendor specific response data. */\n+\tuint32_t\toem_data[18];\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*****************\n+ * hwrm_fw_reset *\n+ ******************/\n+\n+\n+/* hwrm_fw_reset_input (size:192b/24B) */\n+struct hwrm_fw_reset_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t req_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t cmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t seq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t resp_addr;\n+\t/* Type of embedded processor. */\n+\tuint8_t embedded_proc_type;\n+\t/* Boot Processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \\\n+\t\tUINT32_C(0x0)\n+\t/* Management Processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \\\n+\t\tUINT32_C(0x1)\n+\t/* Network control processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \\\n+\t\tUINT32_C(0x2)\n+\t/* RoCE control processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \\\n+\t\tUINT32_C(0x3)\n+\t/*\n+\t * Host (in multi-host environment): This is only valid if requester is IPC.\n+\t * Reinit host hardware resources and PCIe.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \\\n+\t\tUINT32_C(0x4)\n+\t/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \\\n+\t\tUINT32_C(0x5)\n+\t/* Reset all blocks of the chip (including all processors) */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \\\n+\t\tUINT32_C(0x6)\n+\t/*\n+\t * Host (in multi-host environment): This is only valid if requester is IPC.\n+\t * Reinit host hardware resources.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \\\n+\t\tUINT32_C(0x7)\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \\\n+\t\tHWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT\n+\t/* Type of self reset. */\n+\tuint8_t selfrst_status;\n+\t/* No Self Reset */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Self Reset as soon as possible to do so safely */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \\\n+\t\tUINT32_C(0x1)\n+\t/* Self Reset on PCIe Reset */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n+\t\tUINT32_C(0x2)\n+\t/* Self Reset immediately after notification to all clients. */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \\\n+\t\tHWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n+\t/*\n+\t * Indicate which host is being reset. 0 means first host.\n+\t * Only valid when embedded_proc_type is host in multihost\n+\t * environment\n+\t */\n+\tuint8_t host_idx;\n+\tuint8_t flags;\n+\t/*\n+\t * When this bit is '1', then the core firmware initiates\n+\t * the reset only after graceful shut down of all registered instances.\n+\t * If not, the device will continue with the existing firmware.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)\n+\tuint8_t unused_0[4];\n+} __rte_packed;\n+\n+/* hwrm_fw_reset_output (size:128b/16B) */\n+struct hwrm_fw_reset_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t error_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t req_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t seq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t resp_len;\n+\t/* Type of self reset. */\n+\tuint8_t selfrst_status;\n+\t/* No Self Reset */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Self Reset as soon as possible to do so safely */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \\\n+\t\tUINT32_C(0x1)\n+\t/* Self Reset on PCIe Reset */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n+\t\tUINT32_C(0x2)\n+\t/* Self Reset immediately after notification to all clients. */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \\\n+\t\tHWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n+\tuint8_t unused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_port_ts_query *\n+ ***********************/\n+\n+\n+/* hwrm_port_ts_query_input (size:192b/24B) */\n+struct hwrm_port_ts_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH\t\t0x1UL\n+\t/* tx path */\n+\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX\t\t0x0UL\n+\t/* rx path */\n+\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX\t\t0x1UL\n+\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST\t\\\n+\t\tHWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX\n+\t/*\n+\t * If set, the response includes the current value of the free\n+\t * running timer.\n+\t */\n+\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME\t0x2UL\n+\t/* Port ID of port that is being queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\t\tunused_0[2];\n+} __rte_packed;\n+\n+/* hwrm_port_ts_query_output (size:192b/24B) */\n+struct hwrm_port_ts_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Timestamp value of PTP message captured, or current value of\n+\t * free running timer.\n+\t */\n+\tuint32_t\tptp_msg_ts[2];\n+\t/* Sequence ID of the PTP message captured. */\n+\tuint16_t\tptp_msg_seqid;\n+\tuint8_t\t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\t\tvalid;\n+} __rte_packed;\n+\n+/*\n+ * This structure is fixed at the beginning of the ChiMP SRAM (GRC\n+ * offset: 0x31001F0). Host software is expected to read from this\n+ * location for a defined signature. If it exists, the software can\n+ * assume the presence of this structure and the validity of the\n+ * FW_STATUS location in the next field.\n+ */\n+/* hcomm_status (size:64b/8B) */\n+struct hcomm_status {\n+\tuint32_t\tsig_ver;\n+\t/*\n+\t * This field defines the version of the structure. The latest\n+\t * version value is 1.\n+\t */\n+\t#define HCOMM_STATUS_VER_MASK\t\tUINT32_C(0xff)\n+\t#define HCOMM_STATUS_VER_SFT\t\t0\n+\t#define HCOMM_STATUS_VER_LATEST\t\tUINT32_C(0x1)\n+\t#define HCOMM_STATUS_VER_LAST\t\tHCOMM_STATUS_VER_LATEST\n+\t/*\n+\t * This field is to store the signature value to indicate the\n+\t * presence of the structure.\n+\t */\n+\t#define HCOMM_STATUS_SIGNATURE_MASK\tUINT32_C(0xffffff00)\n+\t#define HCOMM_STATUS_SIGNATURE_SFT\t8\n+\t#define HCOMM_STATUS_SIGNATURE_VAL\t(UINT32_C(0x484353) << 8)\n+\t#define HCOMM_STATUS_SIGNATURE_LAST\tHCOMM_STATUS_SIGNATURE_VAL\n+\tuint32_t\tfw_status_loc;\n+\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK\tUINT32_C(0x3)\n+\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT\t0\n+\t/* PCIE configuration space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG\tUINT32_C(0x0)\n+\t/* GRC space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC\tUINT32_C(0x1)\n+\t/* BAR0 space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0\tUINT32_C(0x2)\n+\t/* BAR1 space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\tUINT32_C(0x3)\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST\t\\\n+\t\tHCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\n+\t/*\n+\t * This offset where the fw_status register is located. The value\n+\t * is generally 4-byte aligned.\n+\t */\n+\t#define HCOMM_STATUS_TRUE_OFFSET_MASK\t\tUINT32_C(0xfffffffc)\n+\t#define HCOMM_STATUS_TRUE_OFFSET_SFT\t\t2\n+} __rte_packed;\n+/* This is the GRC offset where the hcomm_status struct resides. */\n+#define HCOMM_STATUS_STRUCT_LOC\t\t0x31001F0UL\n #endif /* _HSI_STRUCT_DEF_DPDK_H_ */\n", "prefixes": [ "2/3" ] }