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{
    "id": 79127,
    "url": "http://patches.dpdk.org/api/patches/79127/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200929015632.109364-4-simei.su@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200929015632.109364-4-simei.su@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200929015632.109364-4-simei.su@intel.com",
    "date": "2020-09-29T01:56:31",
    "name": "[v2,3/4] net/ice: support ACL filter in DCF",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "d3299ad8ed112e082f417d24ad2406e4b7ba2975",
    "submitter": {
        "id": 1298,
        "url": "http://patches.dpdk.org/api/people/1298/?format=api",
        "name": "Simei Su",
        "email": "simei.su@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200929015632.109364-4-simei.su@intel.com/mbox/",
    "series": [
        {
            "id": 12571,
            "url": "http://patches.dpdk.org/api/series/12571/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12571",
            "date": "2020-09-29T01:56:28",
            "name": "net/ice: support DCF ACL capabiltiy",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/12571/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/79127/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/79127/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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        ],
        "IronPort-SDR": [
            "\n LMV2EQ2vDJFtCU2+P8GV/zq6m5blWL1E84S3Zl/hN83DCg6+55PzHtZ1okjVaRMwqgnvGdANcx\n OTyCKkKY3wrQ==",
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        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9758\"; a=\"141498644\"",
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        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Simei Su <simei.su@intel.com>",
        "To": "qi.z.zhang@intel.com,\n\tqiming.yang@intel.com",
        "Cc": "dev@dpdk.org, haiyue.wang@intel.com, beilei.xing@intel.com,\n Simei Su <simei.su@intel.com>, Xuan Ding <xuan.ding@intel.com>",
        "Date": "Tue, 29 Sep 2020 09:56:31 +0800",
        "Message-Id": "<20200929015632.109364-4-simei.su@intel.com>",
        "X-Mailer": "git-send-email 2.9.5",
        "In-Reply-To": "<20200929015632.109364-1-simei.su@intel.com>",
        "References": "<1599723455-353059-1-git-send-email-simei.su@intel.com>\n <20200929015632.109364-1-simei.su@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 3/4] net/ice: support ACL filter in DCF",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add ice_acl_create_filter to create a rule and ice_acl_destroy_filter\nto destroy a rule. If a flow is matched by ACL filter, filter rule\nwill be set to HW. Currently IPV4/IPV4_UDP/IPV4_TCP/IPV4_SCTP pattern\nand drop action are supported.\n\nSigned-off-by: Simei Su <simei.su@intel.com>\nSigned-off-by: Xuan Ding <xuan.ding@intel.com>\n---\n doc/guides/rel_notes/release_20_11.rst |    5 +\n drivers/net/ice/ice_acl_filter.c       | 1088 ++++++++++++++++++++++++++++++++\n drivers/net/ice/ice_ethdev.h           |   17 +\n drivers/net/ice/ice_generic_flow.c     |    2 +\n drivers/net/ice/meson.build            |    3 +-\n 5 files changed, 1114 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/ice/ice_acl_filter.c",
    "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 96d8c14..1d3afb2 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -90,6 +90,11 @@ New Features\n \n   * Added support for flexible descriptor metadata extraction.\n \n+* **Updated the Intel ice driver.**\n+\n+  Updated the Intel ice driver with new features and improvements, including:\n+\n+  * Added acl filter support for Intel DCF.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/ice/ice_acl_filter.c b/drivers/net/ice/ice_acl_filter.c\nnew file mode 100644\nindex 0000000..758362a\n--- /dev/null\n+++ b/drivers/net/ice/ice_acl_filter.c\n@@ -0,0 +1,1088 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include <sys/queue.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <stdint.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <stdarg.h>\n+#include <rte_debug.h>\n+#include <rte_ether.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+#include <rte_eth_ctrl.h>\n+#include <rte_tailq.h>\n+#include <rte_flow_driver.h>\n+#include <rte_flow.h>\n+#include <rte_bitmap.h>\n+#include \"base/ice_type.h\"\n+#include \"base/ice_acl.h\"\n+#include \"ice_logs.h\"\n+#include \"ice_ethdev.h\"\n+#include \"ice_generic_flow.h\"\n+#include \"base/ice_flow.h\"\n+\n+#define MAX_ACL_SLOTS_ID 2048\n+\n+#define ICE_ACL_INSET_ETH_IPV4 ( \\\n+\tICE_INSET_SMAC | ICE_INSET_DMAC | \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST)\n+#define ICE_ACL_INSET_ETH_IPV4_UDP ( \\\n+\tICE_INSET_SMAC | ICE_INSET_DMAC | \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT)\n+#define ICE_ACL_INSET_ETH_IPV4_TCP ( \\\n+\tICE_INSET_SMAC | ICE_INSET_DMAC | \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT)\n+#define ICE_ACL_INSET_ETH_IPV4_SCTP ( \\\n+\tICE_INSET_SMAC | ICE_INSET_DMAC | \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_SCTP_SRC_PORT | ICE_INSET_SCTP_DST_PORT)\n+\n+static struct ice_flow_parser ice_acl_parser;\n+\n+static struct\n+ice_pattern_match_item ice_acl_pattern[] = {\n+\t{pattern_eth_ipv4,      ICE_ACL_INSET_ETH_IPV4,      ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp,  ICE_ACL_INSET_ETH_IPV4_UDP,  ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_tcp,  ICE_ACL_INSET_ETH_IPV4_TCP,  ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_sctp, ICE_ACL_INSET_ETH_IPV4_SCTP, ICE_INSET_NONE},\n+};\n+\n+static int\n+ice_acl_prof_alloc(struct ice_hw *hw)\n+{\n+\tenum ice_fltr_ptype ptype, fltr_ptype;\n+\n+\tif (!hw->acl_prof) {\n+\t\thw->acl_prof = (struct ice_fd_hw_prof **)\n+\t\t\tice_malloc(hw, ICE_FLTR_PTYPE_MAX *\n+\t\t\t\t   sizeof(*hw->acl_prof));\n+\t\tif (!hw->acl_prof)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (ptype = ICE_FLTR_PTYPE_NONF_NONE + 1;\n+\t     ptype < ICE_FLTR_PTYPE_MAX; ptype++) {\n+\t\tif (!hw->acl_prof[ptype]) {\n+\t\t\thw->acl_prof[ptype] = (struct ice_fd_hw_prof *)\n+\t\t\t\tice_malloc(hw, sizeof(**hw->acl_prof));\n+\t\t\tif (!hw->acl_prof[ptype])\n+\t\t\t\tgoto fail_mem;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+fail_mem:\n+\tfor (fltr_ptype = ICE_FLTR_PTYPE_NONF_NONE + 1;\n+\t     fltr_ptype < ptype; fltr_ptype++) {\n+\t\trte_free(hw->acl_prof[fltr_ptype]);\n+\t\thw->acl_prof[fltr_ptype] = NULL;\n+\t}\n+\n+\trte_free(hw->acl_prof);\n+\thw->acl_prof = NULL;\n+\n+\treturn -ENOMEM;\n+}\n+\n+/**\n+ * ice_acl_setup - Reserve and initialize the ACL resources\n+ * @pf: board private structure\n+ */\n+static int\n+ice_acl_setup(struct ice_pf *pf)\n+{\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tu32 pf_num = hw->dev_caps.num_funcs;\n+\tstruct ice_acl_tbl_params params;\n+\tu16 scen_id;\n+\tint err = 0;\n+\n+\tmemset(&params, 0, sizeof(params));\n+\n+\t/* create for IPV4 table */\n+\tif (pf_num < 4)\n+\t\tparams.width = ICE_AQC_ACL_KEY_WIDTH_BYTES * 6;\n+\telse\n+\t\tparams.width = ICE_AQC_ACL_KEY_WIDTH_BYTES * 3;\n+\n+\tparams.depth = ICE_AQC_ACL_TCAM_DEPTH;\n+\tparams.entry_act_pairs = 1;\n+\tparams.concurr = false;\n+\n+\terr = ice_acl_create_tbl(hw, &params);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = ice_acl_create_scen(hw, params.width, params.depth,\n+\t\t\t\t  &scen_id);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_deinit_acl - Unroll the initialization of the ACL block\n+ * @pf: ptr to PF device\n+ *\n+ * returns 0 on success, negative on error\n+ */\n+static void ice_deinit_acl(struct ice_pf *pf)\n+{\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\n+\tice_acl_destroy_tbl(hw);\n+\n+\trte_free(hw->acl_tbl);\n+\thw->acl_tbl = NULL;\n+}\n+\n+/**\n+ * ice_acl_erase_flow_from_hw - Remove a flow from the HW profile tables\n+ * @hw: hardware structure containing the filter list\n+ * @flow_type: flow type to release\n+ */\n+static void\n+ice_acl_erase_flow_from_hw(struct ice_hw *hw, enum ice_fltr_ptype flow_type)\n+{\n+\tint tun;\n+\n+\tif (!hw->acl_prof || !hw->acl_prof[flow_type])\n+\t\treturn;\n+\n+\tstruct ice_fd_hw_prof *prof = hw->acl_prof[flow_type];\n+\tfor (tun = 0; tun < ICE_FD_HW_SEG_TUN; tun++) {\n+\t\tuint64_t prof_id;\n+\t\tint j;\n+\n+\t\tprof_id = flow_type + tun * ICE_FLTR_PTYPE_MAX;\n+\t\tfor (j = 0; j < prof->cnt; j++) {\n+\t\t\tuint16_t vsi_num;\n+\n+\t\t\tif (!prof->entry_h[j][tun] && !prof->vsi_h[j])\n+\t\t\t\tcontinue;\n+\t\t\tvsi_num = ice_get_hw_vsi_num(hw, prof->vsi_h[j]);\n+\t\t\tice_rem_prof_id_flow(hw, ICE_BLK_ACL, vsi_num, prof_id);\n+\t\t\tice_flow_rem_entry(hw, ICE_BLK_ACL,\n+\t\t\t\t\t   prof->entry_h[j][tun]);\n+\t\t\tprof->entry_h[j][tun] = 0;\n+\t\t}\n+\t\tice_flow_rem_prof(hw, ICE_BLK_ACL, prof_id);\n+\t}\n+}\n+\n+/**\n+ * ice_acl_rem_flow - Release the ice_flow structures for a filter type\n+ * @hw: hardware structure containing the filter list\n+ * @flow_type: flow type to release\n+ */\n+static void ice_acl_rem_flow(struct ice_hw *hw, enum ice_fltr_ptype flow_type)\n+{\n+\tstruct ice_fd_hw_prof *prof;\n+\tint tun, i;\n+\n+\tif (!hw->acl_prof || !hw->acl_prof[flow_type])\n+\t\treturn;\n+\n+\tprof = hw->acl_prof[flow_type];\n+\n+\tice_acl_erase_flow_from_hw(hw, flow_type);\n+\tfor (i = 0; i < prof->cnt; i++)\n+\t\tprof->vsi_h[i] = 0;\n+\tfor (tun = 0; tun < ICE_FD_HW_SEG_MAX; tun++) {\n+\t\tif (!prof->fdir_seg[tun])\n+\t\t\tcontinue;\n+\t\trte_free(prof->fdir_seg[tun]);\n+\t\tprof->fdir_seg[tun] = NULL;\n+\t}\n+\tprof->cnt = 0;\n+}\n+\n+static int\n+acl_prof_helper_function(struct ice_hw *hw, struct ice_flow_seg_info *seg,\n+\t\t\t bool is_l4, uint16_t src_port, uint16_t dst_port)\n+{\n+\tuint16_t val_loc, mask_loc;\n+\n+\tif (hw->dev_caps.num_funcs < 4) {\n+\t\t/* mac source address */\n+\t\tval_loc = offsetof(struct ice_fdir_fltr,\n+\t\t\t\t   ext_data.src_mac);\n+\t\tmask_loc = offsetof(struct ice_fdir_fltr,\n+\t\t\t\t    ext_mask.src_mac);\n+\t\tice_flow_set_fld(seg, ICE_FLOW_FIELD_IDX_ETH_SA,\n+\t\t\t\t val_loc, mask_loc,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL, false);\n+\n+\t\t/* mac destination address */\n+\t\tval_loc = offsetof(struct ice_fdir_fltr,\n+\t\t\t\t   ext_data.dst_mac);\n+\t\tmask_loc = offsetof(struct ice_fdir_fltr,\n+\t\t\t\t    ext_mask.dst_mac);\n+\t\tice_flow_set_fld(seg, ICE_FLOW_FIELD_IDX_ETH_DA,\n+\t\t\t\t val_loc, mask_loc,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL, false);\n+\t}\n+\n+\t/* IP source address */\n+\tval_loc = offsetof(struct ice_fdir_fltr, ip.v4.src_ip);\n+\tmask_loc = offsetof(struct ice_fdir_fltr, mask.v4.src_ip);\n+\tice_flow_set_fld(seg, ICE_FLOW_FIELD_IDX_IPV4_SA, val_loc,\n+\t\t\t mask_loc, ICE_FLOW_FLD_OFF_INVAL, false);\n+\n+\t/* IP destination address */\n+\tval_loc = offsetof(struct ice_fdir_fltr, ip.v4.dst_ip);\n+\tmask_loc = offsetof(struct ice_fdir_fltr, mask.v4.dst_ip);\n+\tice_flow_set_fld(seg, ICE_FLOW_FIELD_IDX_IPV4_DA, val_loc,\n+\t\t\t mask_loc, ICE_FLOW_FLD_OFF_INVAL, false);\n+\n+\tif (is_l4) {\n+\t\t/* Layer 4 source port */\n+\t\tval_loc = offsetof(struct ice_fdir_fltr, ip.v4.src_port);\n+\t\tmask_loc = offsetof(struct ice_fdir_fltr, mask.v4.src_port);\n+\t\tice_flow_set_fld(seg, src_port, val_loc,\n+\t\t\t\t mask_loc, ICE_FLOW_FLD_OFF_INVAL, false);\n+\n+\t\t/* Layer 4 destination port */\n+\t\tval_loc = offsetof(struct ice_fdir_fltr, ip.v4.dst_port);\n+\t\tmask_loc = offsetof(struct ice_fdir_fltr, mask.v4.dst_port);\n+\t\tice_flow_set_fld(seg, dst_port, val_loc,\n+\t\t\t\t mask_loc, ICE_FLOW_FLD_OFF_INVAL, false);\n+\t}\n+\n+\treturn 0;\n+};\n+\n+/**\n+ * ice_acl_prof_init - Initialize ACL profile\n+ * @pf: ice PF structure\n+ *\n+ * Returns 0 on success.\n+ */\n+static int\n+ice_acl_prof_init(struct ice_pf *pf)\n+{\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tstruct ice_flow_prof *prof_1 = NULL;\n+\tstruct ice_flow_prof *prof_2 = NULL;\n+\tstruct ice_flow_prof *prof_3 = NULL;\n+\tstruct ice_flow_prof *prof_4 = NULL;\n+\tstruct ice_flow_seg_info *seg_1, *seg_2, *seg_3, *seg_4;\n+\tint i;\n+\n+\tseg_1 = (struct ice_flow_seg_info *)\n+\t\t ice_malloc(hw, sizeof(*seg_1));\n+\n+\tseg_2 = (struct ice_flow_seg_info *)\n+\t\t ice_malloc(hw, sizeof(*seg_2));\n+\n+\tseg_3 = (struct ice_flow_seg_info *)\n+\t\t ice_malloc(hw, sizeof(*seg_3));\n+\n+\tseg_4 = (struct ice_flow_seg_info *)\n+\t\t ice_malloc(hw, sizeof(*seg_4));\n+\n+\tICE_FLOW_SET_HDRS(seg_1, ICE_FLOW_SEG_HDR_IPV4);\n+\tacl_prof_helper_function(hw, seg_1, false, 0, 0);\n+\tice_flow_add_prof(hw, ICE_BLK_ACL, ICE_FLOW_RX,\n+\t\t\t  ICE_FLTR_PTYPE_NONF_IPV4_OTHER,\n+\t\t\t  seg_1, 1, NULL, 0, &prof_1);\n+\n+\tICE_FLOW_SET_HDRS(seg_2, ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);\n+\tacl_prof_helper_function(hw, seg_2, true,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_UDP_SRC_PORT,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_UDP_DST_PORT);\n+\tice_flow_add_prof(hw, ICE_BLK_ACL, ICE_FLOW_RX,\n+\t\t\t  ICE_FLTR_PTYPE_NONF_IPV4_UDP,\n+\t\t\t  seg_2, 1, NULL, 0, &prof_2);\n+\n+\tICE_FLOW_SET_HDRS(seg_3, ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);\n+\tacl_prof_helper_function(hw, seg_3, true,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_TCP_SRC_PORT,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_TCP_DST_PORT);\n+\tice_flow_add_prof(hw, ICE_BLK_ACL, ICE_FLOW_RX,\n+\t\t\t  ICE_FLTR_PTYPE_NONF_IPV4_TCP,\n+\t\t\t  seg_3, 1, NULL, 0, &prof_3);\n+\n+\tICE_FLOW_SET_HDRS(seg_4, ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);\n+\tacl_prof_helper_function(hw, seg_4, true,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT,\n+\t\t\t\t ICE_FLOW_FIELD_IDX_SCTP_DST_PORT);\n+\tice_flow_add_prof(hw, ICE_BLK_ACL, ICE_FLOW_RX,\n+\t\t\t  ICE_FLTR_PTYPE_NONF_IPV4_SCTP,\n+\t\t\t  seg_4, 1, NULL, 0, &prof_4);\n+\n+\tfor (i = 0; i < pf->main_vsi->idx; i++) {\n+\t\tice_flow_assoc_prof(hw, ICE_BLK_ACL, prof_1, i);\n+\t\tice_flow_assoc_prof(hw, ICE_BLK_ACL, prof_2, i);\n+\t\tice_flow_assoc_prof(hw, ICE_BLK_ACL, prof_3, i);\n+\t\tice_flow_assoc_prof(hw, ICE_BLK_ACL, prof_4, i);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_acl_set_input_set - Helper function to set the input set for ACL\n+ * @hw: pointer to HW instance\n+ * @filter: pointer to ACL info\n+ * @input: filter structure\n+ *\n+ * Return error value or 0 on success.\n+ */\n+static int\n+ice_acl_set_input_set(struct ice_acl_conf *filter, struct ice_fdir_fltr *input)\n+{\n+\tif (!input)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tinput->q_index = filter->input.q_index;\n+\tinput->dest_vsi = filter->input.dest_vsi;\n+\tinput->dest_ctl = filter->input.dest_ctl;\n+\tinput->fltr_status = ICE_FLTR_PRGM_DESC_FD_STATUS_FD_ID;\n+\tinput->flow_type = filter->input.flow_type;\n+\n+\tswitch (input->flow_type) {\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_TCP:\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_UDP:\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_SCTP:\n+\t\tinput->ip.v4.dst_port = filter->input.ip.v4.dst_port;\n+\t\tinput->ip.v4.src_port = filter->input.ip.v4.src_port;\n+\t\tinput->ip.v4.dst_ip = filter->input.ip.v4.dst_ip;\n+\t\tinput->ip.v4.src_ip = filter->input.ip.v4.src_ip;\n+\n+\t\tinput->mask.v4.dst_port = filter->input.mask.v4.dst_port;\n+\t\tinput->mask.v4.src_port = filter->input.mask.v4.src_port;\n+\t\tinput->mask.v4.dst_ip = filter->input.mask.v4.dst_ip;\n+\t\tinput->mask.v4.src_ip = filter->input.mask.v4.src_ip;\n+\n+\t\trte_memcpy(&input->ext_data.src_mac,\n+\t\t\t   &filter->input.ext_data.src_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\trte_memcpy(&input->ext_mask.src_mac,\n+\t\t\t   &filter->input.ext_mask.src_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\n+\t\trte_memcpy(&input->ext_data.dst_mac,\n+\t\t\t   &filter->input.ext_data.dst_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\trte_memcpy(&input->ext_mask.dst_mac,\n+\t\t\t   &filter->input.ext_mask.dst_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_OTHER:\n+\t\trte_memcpy(&input->ip.v4, &filter->input.ip.v4,\n+\t\t\t   sizeof(struct ice_fdir_v4));\n+\t\trte_memcpy(&input->mask.v4, &filter->input.mask.v4,\n+\t\t\t   sizeof(struct ice_fdir_v4));\n+\n+\t\trte_memcpy(&input->ext_data.src_mac,\n+\t\t\t   &filter->input.ext_data.src_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\trte_memcpy(&input->ext_mask.src_mac,\n+\t\t\t   &filter->input.ext_mask.src_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\n+\t\trte_memcpy(&input->ext_data.dst_mac,\n+\t\t\t   &filter->input.ext_data.dst_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\trte_memcpy(&input->ext_mask.dst_mac,\n+\t\t\t   &filter->input.ext_mask.dst_mac,\n+\t\t\t   RTE_ETHER_ADDR_LEN);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+struct acl_rule {\n+\tenum ice_fltr_ptype flow_type;\n+\tuint32_t entry_id[4];\n+\tstruct ice_fdir_fltr *input;\n+};\n+\n+/* Allocate slot_id from bitmap table. */\n+static inline uint32_t\n+ice_acl_alloc_slot_id(struct rte_bitmap *slots, struct rte_flow_error *error)\n+{\n+\tuint32_t pos = 0;\n+\tuint64_t slab = 0;\n+\tuint32_t i = 0;\n+\n+\t__rte_bitmap_scan_init(slots);\n+\tif (!rte_bitmap_scan(slots, &pos, &slab)) {\n+\t\trte_flow_error_set(error, ENOMEM,\n+\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t   \"Failed with init acl bitmap.\");\n+\t\treturn -rte_errno;\n+\t}\n+\ti = rte_bsf64(slab);\n+\tpos += i;\n+\trte_bitmap_clear(slots, pos);\n+\n+\treturn pos;\n+}\n+\n+static int\n+ice_acl_create_filter(struct ice_adapter *ad,\n+\t\tstruct rte_flow *flow,\n+\t\tvoid *meta,\n+\t\tstruct rte_flow_error *error)\n+{\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tstruct ice_acl_conf *filter = meta;\n+\tstruct acl_rule *rule;\n+\tstruct ice_fdir_fltr *input;\n+\tstruct ice_flow_action acts[1];\n+\tint act_cnt, ret;\n+\tuint32_t slot_id;\n+\tenum ice_block blk = ICE_BLK_ACL;\n+\tenum ice_fltr_ptype flow_type = filter->input.flow_type;\n+\tuint64_t entry_id;\n+\tuint64_t entry_0, entry_1, entry_2, entry_3, entry_4, entry_5, entry_6;\n+\n+\trule = rte_zmalloc(\"acl_rule\", sizeof(*rule), 0);\n+\tinput = rte_zmalloc(\"acl_entry\", sizeof(*input), 0);\n+\tif (!input) {\n+\t\trte_flow_error_set(error, ENOMEM,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"Failed to allocate memory\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tret = ice_acl_set_input_set(filter, input);\n+\tif (ret) {\n+\t\trte_flow_error_set(error, -ret,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"failed to set input set.\");\n+\t}\n+\n+\tact_cnt = 1;\n+\tif (filter->input.dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DROP_PKT) {\n+\t\tacts[0].type = ICE_FLOW_ACT_DROP;\n+\t\tacts[0].data.acl_act.mdid = ICE_MDID_RX_PKT_DROP;\n+\t\tacts[0].data.acl_act.prio = 0x3;\n+\t\tacts[0].data.acl_act.value = CPU_TO_LE16(0x1);\n+\t}\n+\n+\tinput->acl_fltr = true;\n+\n+\tswitch (flow_type) {\n+\t/* For IPV4_OTHER type, should add entry for all types. */\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_OTHER:\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)(ICE_FLTR_PTYPE_NONF_IPV4_OTHER) << 32) |\n+\t\t\t     slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_OTHER,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_0);\n+\t\trule->entry_id[0] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_0;\n+\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)(ICE_FLTR_PTYPE_NONF_IPV4_UDP) << 32) |\n+\t\t\t     slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_UDP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_1);\n+\t\trule->entry_id[1] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_1;\n+\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)(ICE_FLTR_PTYPE_NONF_IPV4_TCP) << 32) |\n+\t\t\t     slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_TCP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_2);\n+\t\trule->entry_id[2] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_2;\n+\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)(ICE_FLTR_PTYPE_NONF_IPV4_SCTP) << 32) |\n+\t\t\t     slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_SCTP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_3);\n+\t\trule->entry_id[3] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_3;\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_UDP:\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)flow_type << 32) | slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_UDP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_4);\n+\t\trule->entry_id[0] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_4;\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_TCP:\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)flow_type << 32) | slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_TCP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_5);\n+\t\trule->entry_id[0] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_5;\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_SCTP:\n+\t\tslot_id = ice_acl_alloc_slot_id(pf->slots, error);\n+\t\tentry_id = ((uint64_t)flow_type << 32) | slot_id;\n+\t\tice_flow_add_entry(hw, blk,\n+\t\t\t\t   ICE_FLTR_PTYPE_NONF_IPV4_SCTP,\n+\t\t\t\t   entry_id, pf->main_vsi->idx,\n+\t\t\t\t   ICE_FLOW_PRIO_NORMAL, input, acts,\n+\t\t\t\t   act_cnt, &entry_6);\n+\t\trule->entry_id[0] = slot_id;\n+\t\tpf->hw_entry_id[slot_id] = entry_6;\n+\t\tbreak;\n+\tdefault:\n+\t\trte_flow_error_set(error, ENOMEM,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n+\t\t\t\t   \"error flow type\");\n+\t\tbreak;\n+\t}\n+\trule->flow_type = flow_type;\n+\trule->input = input;\n+\tflow->rule = (void *)rule;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_acl_destroy_filter(struct ice_adapter *ad,\n+\t\tstruct rte_flow *flow,\n+\t\tstruct rte_flow_error *error __rte_unused)\n+{\n+\tstruct acl_rule *rule = (struct acl_rule *)flow->rule;\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tint ret = 0;\n+\tuint32_t slot_id0, slot_id1, slot_id2, slot_id3;\n+\n+\tswitch (rule->flow_type) {\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_OTHER:\n+\t\tslot_id0 = rule->entry_id[0];\n+\t\trte_bitmap_set(pf->slots, slot_id0);\n+\t\tice_flow_rem_entry(hw, ICE_BLK_ACL, pf->hw_entry_id[slot_id0]);\n+\n+\t\tslot_id1 = rule->entry_id[1];\n+\t\trte_bitmap_set(pf->slots, slot_id1);\n+\t\tice_flow_rem_entry(hw, ICE_BLK_ACL, pf->hw_entry_id[slot_id1]);\n+\n+\t\tslot_id2 = rule->entry_id[2];\n+\t\trte_bitmap_set(pf->slots, slot_id2);\n+\t\tice_flow_rem_entry(hw, ICE_BLK_ACL, pf->hw_entry_id[slot_id2]);\n+\n+\t\tslot_id3 = rule->entry_id[3];\n+\t\trte_bitmap_set(pf->slots, slot_id3);\n+\t\tice_flow_rem_entry(hw, ICE_BLK_ACL, pf->hw_entry_id[slot_id3]);\n+\n+\t\tice_acl_rem_flow(hw, rule->flow_type);\n+\t\tbreak;\n+\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_UDP:\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_TCP:\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_SCTP:\n+\t\tslot_id0 = rule->entry_id[0];\n+\t\trte_bitmap_set(pf->slots, slot_id0);\n+\t\tice_flow_rem_entry(&ad->hw, ICE_BLK_ACL,\n+\t\t\t\t   pf->hw_entry_id[slot_id0]);\n+\t\tice_acl_rem_flow(hw, rule->flow_type);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\trte_free(flow->rule);\n+\tflow->rule = NULL;\n+\treturn ret;\n+}\n+\n+static void\n+ice_acl_filter_free(struct rte_flow *flow)\n+{\n+\trte_free(flow->rule);\n+}\n+\n+static int\n+ice_acl_parse_action(__rte_unused struct ice_adapter *ad,\n+\t\t     const struct rte_flow_action actions[],\n+\t\t     struct rte_flow_error *error,\n+\t\t     struct ice_acl_conf *filter)\n+{\n+\tuint32_t dest_num = 0;\n+\n+\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n+\t\tswitch (actions->type) {\n+\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n+\t\t\tdest_num++;\n+\n+\t\t\tfilter->input.dest_ctl =\n+\t\t\t\tICE_FLTR_PRGM_DESC_DEST_DROP_PKT;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ACTION, actions,\n+\t\t\t\t   \"Invalid action.\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t}\n+\n+\tif (dest_num == 0 || dest_num >= 2) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t   RTE_FLOW_ERROR_TYPE_ACTION, actions,\n+\t\t\t   \"Unsupported action combination\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_acl_parse_pattern(__rte_unused struct ice_adapter *ad,\n+\t\t       const struct rte_flow_item pattern[],\n+\t\t       struct rte_flow_error *error,\n+\t\t       struct ice_acl_conf *filter)\n+{\n+\tconst struct rte_flow_item *item = pattern;\n+\tenum rte_flow_item_type item_type;\n+\tenum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;\n+\tconst struct rte_flow_item_eth *eth_spec, *eth_mask;\n+\tconst struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;\n+\tconst struct rte_flow_item_tcp *tcp_spec, *tcp_mask;\n+\tconst struct rte_flow_item_udp *udp_spec, *udp_mask;\n+\tconst struct rte_flow_item_sctp *sctp_spec, *sctp_mask;\n+\tuint64_t input_set = ICE_INSET_NONE;\n+\tuint8_t flow_type = ICE_FLTR_PTYPE_NONF_NONE;\n+\n+\tfor (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n+\t\titem_type = item->type;\n+\n+\t\tswitch (item_type) {\n+\t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n+\t\t\teth_spec = item->spec;\n+\t\t\teth_mask = item->mask;\n+\n+\t\t\tif (eth_spec && eth_mask) {\n+\t\t\t\tif (rte_is_broadcast_ether_addr(&eth_mask->dst) ||\n+\t\t\t\t    rte_is_broadcast_ether_addr(&eth_mask->src)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid mac addr mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif (!rte_is_zero_ether_addr(&eth_spec->src) &&\n+\t\t\t\t    !rte_is_zero_ether_addr(&eth_mask->src)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_SMAC;\n+\t\t\t\t\trte_memcpy(&filter->input.ext_data.src_mac,\n+\t\t\t\t\t\t   &eth_spec->src,\n+\t\t\t\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\t\t\t\trte_memcpy(&filter->input.ext_mask.src_mac,\n+\t\t\t\t\t\t   &eth_mask->src,\n+\t\t\t\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\t\t\t}\n+\n+\t\t\t\tif (!rte_is_zero_ether_addr(&eth_spec->dst) &&\n+\t\t\t\t    !rte_is_zero_ether_addr(&eth_mask->dst)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_DMAC;\n+\t\t\t\t\trte_memcpy(&filter->input.ext_data.dst_mac,\n+\t\t\t\t\t\t   &eth_spec->dst,\n+\t\t\t\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\t\t\t\trte_memcpy(&filter->input.ext_mask.dst_mac,\n+\t\t\t\t\t\t   &eth_mask->dst,\n+\t\t\t\t\t\t   RTE_ETHER_ADDR_LEN);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n+\t\t\tl3 = RTE_FLOW_ITEM_TYPE_IPV4;\n+\t\t\tipv4_spec = item->spec;\n+\t\t\tipv4_mask = item->mask;\n+\n+\t\t\tif (ipv4_spec && ipv4_mask) {\n+\t\t\t\t/* Check IPv4 mask and update input set */\n+\t\t\t\tif (ipv4_mask->hdr.version_ihl ||\n+\t\t\t\t    ipv4_mask->hdr.total_length ||\n+\t\t\t\t    ipv4_mask->hdr.packet_id ||\n+\t\t\t\t    ipv4_mask->hdr.fragment_offset ||\n+\t\t\t\t    ipv4_mask->hdr.hdr_checksum) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid IPv4 mask.\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((ipv4_mask->hdr.src_addr == UINT32_MAX) ||\n+\t\t\t\t    (ipv4_mask->hdr.dst_addr == UINT32_MAX)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid IPv4 mask.\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((ipv4_spec->hdr.src_addr != 0) &&\n+\t\t\t\t    (ipv4_mask->hdr.src_addr != 0)) {\n+\t\t\t\t\tfilter->input.ip.v4.src_ip =\n+\t\t\t\t\t\tipv4_spec->hdr.src_addr;\n+\t\t\t\t\tfilter->input.mask.v4.src_ip =\n+\t\t\t\t\t\tipv4_mask->hdr.src_addr;\n+\n+\t\t\t\t\tinput_set |= ICE_INSET_IPV4_SRC;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((ipv4_spec->hdr.dst_addr != 0) &&\n+\t\t\t\t    (ipv4_mask->hdr.dst_addr != 0)) {\n+\t\t\t\t\tfilter->input.ip.v4.dst_ip =\n+\t\t\t\t\t\tipv4_spec->hdr.dst_addr;\n+\t\t\t\t\tfilter->input.mask.v4.dst_ip =\n+\t\t\t\t\t\tipv4_mask->hdr.dst_addr;\n+\n+\t\t\t\t\tinput_set |= ICE_INSET_IPV4_DST;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tflow_type = ICE_FLTR_PTYPE_NONF_IPV4_OTHER;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n+\t\t\ttcp_spec = item->spec;\n+\t\t\ttcp_mask = item->mask;\n+\n+\t\t\tif (tcp_spec && tcp_mask) {\n+\t\t\t\t/* Check TCP mask and update input set */\n+\t\t\t\tif (tcp_mask->hdr.sent_seq ||\n+\t\t\t\t    tcp_mask->hdr.recv_ack ||\n+\t\t\t\t    tcp_mask->hdr.data_off ||\n+\t\t\t\t    tcp_mask->hdr.tcp_flags ||\n+\t\t\t\t    tcp_mask->hdr.rx_win ||\n+\t\t\t\t    tcp_mask->hdr.cksum ||\n+\t\t\t\t    tcp_mask->hdr.tcp_urp) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid TCP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((tcp_mask->hdr.src_port == UINT16_MAX) ||\n+\t\t\t\t    (tcp_mask->hdr.dst_port == UINT16_MAX)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid TCP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((tcp_mask->hdr.src_port == UINT16_MAX) ||\n+\t\t\t\t    (tcp_mask->hdr.dst_port == UINT16_MAX)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid TCP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (tcp_spec->hdr.src_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_TCP_SRC_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.src_port =\n+\t\t\t\t\t\ttcp_spec->hdr.src_port;\n+\t\t\t\t\tfilter->input.mask.v4.src_port =\n+\t\t\t\t\t\ttcp_mask->hdr.src_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (tcp_spec->hdr.dst_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_TCP_DST_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.dst_port =\n+\t\t\t\t\t\ttcp_spec->hdr.dst_port;\n+\t\t\t\t\tfilter->input.mask.v4.dst_port =\n+\t\t\t\t\t\ttcp_mask->hdr.dst_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif (l3 == RTE_FLOW_ITEM_TYPE_IPV4)\n+\t\t\t\t\tflow_type =\n+\t\t\t\t\t\tICE_FLTR_PTYPE_NONF_IPV4_TCP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n+\t\t\tudp_spec = item->spec;\n+\t\t\tudp_mask = item->mask;\n+\n+\t\t\tif (udp_spec && udp_mask) {\n+\t\t\t\t/* Check UDP mask and update input set*/\n+\t\t\t\tif (udp_mask->hdr.dgram_len ||\n+\t\t\t\t    udp_mask->hdr.dgram_cksum) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid UDP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((udp_mask->hdr.src_port == UINT16_MAX) ||\n+\t\t\t\t    (udp_mask->hdr.dst_port == UINT16_MAX)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid UDP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (udp_spec->hdr.src_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_UDP_SRC_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.src_port =\n+\t\t\t\t\t\tudp_spec->hdr.src_port;\n+\t\t\t\t\tfilter->input.mask.v4.src_port =\n+\t\t\t\t\t\tudp_mask->hdr.src_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (udp_spec->hdr.dst_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_UDP_DST_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.dst_port =\n+\t\t\t\t\t\tudp_spec->hdr.dst_port;\n+\t\t\t\t\tfilter->input.mask.v4.dst_port =\n+\t\t\t\t\t\tudp_mask->hdr.dst_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif (l3 == RTE_FLOW_ITEM_TYPE_IPV4)\n+\t\t\t\t\tflow_type =\n+\t\t\t\t\t\tICE_FLTR_PTYPE_NONF_IPV4_UDP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n+\t\t\tsctp_spec = item->spec;\n+\t\t\tsctp_mask = item->mask;\n+\n+\t\t\tif (sctp_spec && sctp_mask) {\n+\t\t\t\tif ((sctp_mask->hdr.src_port == UINT16_MAX) ||\n+\t\t\t\t    (sctp_mask->hdr.dst_port == UINT16_MAX)) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid SCTP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (sctp_spec->hdr.src_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_SCTP_SRC_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.src_port =\n+\t\t\t\t\t\tsctp_spec->hdr.src_port;\n+\t\t\t\t\tfilter->input.mask.v4.src_port =\n+\t\t\t\t\t\tsctp_mask->hdr.src_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif ((l3 == RTE_FLOW_ITEM_TYPE_IPV4) &&\n+\t\t\t\t    (sctp_spec->hdr.dst_port != 0)) {\n+\t\t\t\t\tinput_set |= ICE_INSET_SCTP_DST_PORT;\n+\t\t\t\t\tfilter->input.ip.v4.dst_port =\n+\t\t\t\t\t\tsctp_spec->hdr.dst_port;\n+\t\t\t\t\tfilter->input.mask.v4.dst_port =\n+\t\t\t\t\t\tsctp_mask->hdr.dst_port;\n+\t\t\t\t}\n+\n+\t\t\t\tif (l3 == RTE_FLOW_ITEM_TYPE_IPV4)\n+\t\t\t\t\tflow_type =\n+\t\t\t\t\t\tICE_FLTR_PTYPE_NONF_IPV4_SCTP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\titem,\n+\t\t\t\t\"Invalid pattern item.\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t}\n+\n+\tfilter->input.flow_type = flow_type;\n+\tfilter->input_set = input_set;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_acl_parse(struct ice_adapter *ad,\n+\t       struct ice_pattern_match_item *array,\n+\t       uint32_t array_len,\n+\t       const struct rte_flow_item pattern[],\n+\t       const struct rte_flow_action actions[],\n+\t       void **meta,\n+\t       struct rte_flow_error *error)\n+{\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_acl_conf *filter = &pf->acl.conf;\n+\tstruct ice_pattern_match_item *item = NULL;\n+\tuint64_t input_set;\n+\tint ret;\n+\n+\tmemset(filter, 0, sizeof(*filter));\n+\titem = ice_search_pattern_match_item(pattern, array, array_len, error);\n+\tif (!item)\n+\t\treturn -rte_errno;\n+\n+\tret = ice_acl_parse_pattern(ad, pattern, error, filter);\n+\tif (ret)\n+\t\tgoto error;\n+\tinput_set = filter->input_set;\n+\tif (!input_set || input_set & ~item->input_set_mask) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM_SPEC,\n+\t\t\t\t   pattern,\n+\t\t\t\t   \"Invalid input set\");\n+\t\tret = -rte_errno;\n+\t\tgoto error;\n+\t}\n+\n+\tret = ice_acl_parse_action(ad, actions, error, filter);\n+\tif (ret)\n+\t\tgoto error;\n+\n+\tif (meta)\n+\t\t*meta = filter;\n+\n+error:\n+\trte_free(item);\n+\treturn ret;\n+}\n+\n+static int\n+ice_acl_bitmap_init(struct ice_pf *pf)\n+{\n+\tuint32_t bmp_size;\n+\tvoid *mem = NULL;\n+\tstruct rte_bitmap *slots;\n+\tbmp_size = rte_bitmap_get_memory_footprint(MAX_ACL_SLOTS_ID);\n+\tmem = rte_zmalloc(\"create_acl_bmap\", bmp_size, RTE_CACHE_LINE_SIZE);\n+\tif (mem == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for acl bitmap.\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tslots = rte_bitmap_init_with_all_set(MAX_ACL_SLOTS_ID, mem, bmp_size);\n+\tif (slots == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for acl bitmap.\");\n+\t\treturn -rte_errno;\n+\t}\n+\tpf->slots = slots;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_acl_init(struct ice_adapter *ad)\n+{\n+\tint ret = 0;\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tstruct ice_flow_parser *parser = &ice_acl_parser;\n+\n+\tret = ice_acl_prof_alloc(hw);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Cannot allocate memory for \"\n+\t\t\t    \"ACL profile.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = ice_acl_setup(pf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ice_acl_bitmap_init(pf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ice_acl_prof_init(pf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn ice_register_parser(parser, ad);\n+}\n+\n+static void\n+ice_acl_prof_free(struct ice_hw *hw)\n+{\n+\tenum ice_fltr_ptype ptype;\n+\n+\tfor (ptype = ICE_FLTR_PTYPE_NONF_NONE + 1;\n+\t     ptype < ICE_FLTR_PTYPE_MAX; ptype++) {\n+\t\trte_free(hw->acl_prof[ptype]);\n+\t\thw->acl_prof[ptype] = NULL;\n+\t}\n+\n+\trte_free(hw->acl_prof);\n+\thw->acl_prof = NULL;\n+}\n+\n+static void\n+ice_acl_uninit(struct ice_adapter *ad)\n+{\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tstruct ice_flow_parser *parser = &ice_acl_parser;\n+\n+\tice_unregister_parser(parser, ad);\n+\n+\tice_deinit_acl(pf);\n+\tice_acl_prof_free(hw);\n+}\n+\n+static struct\n+ice_flow_engine ice_acl_engine = {\n+\t.init = ice_acl_init,\n+\t.uninit = ice_acl_uninit,\n+\t.create = ice_acl_create_filter,\n+\t.destroy = ice_acl_destroy_filter,\n+\t.free = ice_acl_filter_free,\n+\t.type = ICE_FLOW_ENGINE_ACL,\n+};\n+\n+static struct\n+ice_flow_parser ice_acl_parser = {\n+\t.engine = &ice_acl_engine,\n+\t.array = ice_acl_pattern,\n+\t.array_len = RTE_DIM(ice_acl_pattern),\n+\t.parse_pattern_action = ice_acl_parse,\n+\t.stage = ICE_FLOW_STAGE_DISTRIBUTOR,\n+};\n+\n+RTE_INIT(ice_acl_engine_init)\n+{\n+\tstruct ice_flow_engine *engine = &ice_acl_engine;\n+\tice_register_flow_engine(engine);\n+}\ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 37b956e..38de4c6 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -49,6 +49,8 @@\n #define ICE_PKG_FILE_SEARCH_PATH_UPDATES \"/lib/firmware/updates/intel/ice/ddp/\"\n #define ICE_MAX_PKG_FILENAME_SIZE   256\n \n+#define MAX_ACL_ENTRIES\t512\n+\n /**\n  * vlan_id is a 12 bit number.\n  * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.\n@@ -398,6 +400,18 @@ struct ice_hash_gtpu_ctx {\n \tstruct ice_hash_cfg ipv6_tcp;\n };\n \n+struct ice_acl_conf {\n+\tstruct ice_fdir_fltr input;\n+\tuint64_t input_set;\n+};\n+\n+/**\n+ * A structure used to define fields of ACL related info.\n+ */\n+struct ice_acl_info {\n+\tstruct ice_acl_conf conf;\n+};\n+\n struct ice_pf {\n \tstruct ice_adapter *adapter; /* The adapter this PF associate to */\n \tstruct ice_vsi *main_vsi; /* pointer to main VSI structure */\n@@ -421,6 +435,7 @@ struct ice_pf {\n \tuint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */\n \tuint16_t fdir_qp_offset;\n \tstruct ice_fdir_info fdir; /* flow director info */\n+\tstruct ice_acl_info acl; /* ACL info */\n \tstruct ice_hash_gtpu_ctx gtpu_hash_ctx;\n \tuint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];\n \tuint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];\n@@ -440,6 +455,8 @@ struct ice_pf {\n \tuint64_t old_rx_bytes;\n \tuint64_t old_tx_bytes;\n \tuint64_t supported_rxdid; /* bitmap for supported RXDID */\n+\tstruct rte_bitmap *slots;\n+\tuint64_t hw_entry_id[MAX_ACL_ENTRIES];\n };\n \n #define ICE_MAX_QUEUE_NUM  2048\ndiff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c\nindex 54b0316..1429cbc 100644\n--- a/drivers/net/ice/ice_generic_flow.c\n+++ b/drivers/net/ice/ice_generic_flow.c\n@@ -1896,6 +1896,8 @@ ice_register_parser(struct ice_flow_parser *parser,\n \t\t\tTAILQ_INSERT_TAIL(list, parser_node, node);\n \t\telse if (parser->engine->type == ICE_FLOW_ENGINE_FDIR)\n \t\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n+\t\telse if (parser->engine->type == ICE_FLOW_ENGINE_ACL)\n+\t\t\tTAILQ_INSERT_HEAD(list, parser_node, node);\n \t\telse\n \t\t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build\nindex 99e1b77..254595a 100644\n--- a/drivers/net/ice/meson.build\n+++ b/drivers/net/ice/meson.build\n@@ -10,7 +10,8 @@ sources = files(\n \t'ice_switch_filter.c',\n \t'ice_generic_flow.c',\n \t'ice_fdir_filter.c',\n-\t'ice_hash.c'\n+\t'ice_hash.c',\n+\t'ice_acl_filter.c'\n \t)\n \n deps += ['hash', 'net', 'common_iavf']\n",
    "prefixes": [
        "v2",
        "3/4"
    ]
}