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GET /api/patches/78316/?format=api
{ "id": 78316, "url": "http://patches.dpdk.org/api/patches/78316/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200922085401.12272-2-huwei013@chinasoftinc.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200922085401.12272-2-huwei013@chinasoftinc.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200922085401.12272-2-huwei013@chinasoftinc.com", "date": "2020-09-22T08:53:45", "name": "[01/17] net/hns3: add VLAN configuration compatibility", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "35439be47db5d7818fd28798b1e0dd55c2531493", "submitter": { "id": 1537, "url": "http://patches.dpdk.org/api/people/1537/?format=api", "name": "Wei Hu (Xavier)", "email": "huwei013@chinasoftinc.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200922085401.12272-2-huwei013@chinasoftinc.com/mbox/", "series": [ { "id": 12401, "url": "http://patches.dpdk.org/api/series/12401/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12401", "date": "2020-09-22T08:53:46", "name": "updates for hns3 PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/12401/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/78316/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/78316/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0E0CDA04E1;\n\tTue, 22 Sep 2020 11:03:18 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B17611DC4D;\n\tTue, 22 Sep 2020 10:55:16 +0200 (CEST)", "from incedge.chinasoftinc.com (unknown [114.113.233.8])\n by dpdk.org (Postfix) with ESMTP id A37C51DBC0\n for <dev@dpdk.org>; Tue, 22 Sep 2020 10:54:57 +0200 (CEST)", "from mail.chinasoftinc.com ([10.168.0.51]) by\n incedge.chinasoftinc.com with ESMTP id nfnepaXp7XLcMxXv (version=TLSv1\n cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NO);\n Tue, 22 Sep 2020 16:54:53 +0800 (CST)", "from localhost.localdomain (120.133.139.157) by INCCAS001.ito.icss\n (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Tue, 22 Sep 2020\n 16:54:51 +0800" ], "X-ASG-Debug-ID": "1600764890-149d111baf19b000003-TfluYd", "X-Barracuda-Envelope-From": "huwei013@chinasoftinc.com", "X-Barracuda-RBL-Trusted-Forwarder": [ "10.168.0.51", "10.168.0.60" ], "X-ASG-Whitelist": "Client", "From": "\"Wei Hu (Xavier)\" <huwei013@chinasoftinc.com>", "To": "<dev@dpdk.org>", "CC": "<xavier.huwei@huawei.com>", "Date": "Tue, 22 Sep 2020 16:53:45 +0800", "X-ASG-Orig-Subj": "[PATCH 01/17] net/hns3: add VLAN configuration compatibility", "Message-ID": "<20200922085401.12272-2-huwei013@chinasoftinc.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20200922085401.12272-1-huwei013@chinasoftinc.com>", "References": "<20200922085401.12272-1-huwei013@chinasoftinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[120.133.139.157]", "X-Barracuda-Connect": "UNKNOWN[10.168.0.51]", "X-Barracuda-Start-Time": "1600764893", "X-Barracuda-Encrypted": "ECDHE-RSA-AES256-SHA", "X-Barracuda-URL": "https://incspam.chinasofti.com:443/cgi-mod/mark.cgi", "X-Virus-Scanned": "by bsmtpd at chinasoftinc.com", "X-Barracuda-Scan-Msg-Size": "20333", "Subject": "[dpdk-dev] [PATCH 01/17] net/hns3: add VLAN configuration\n\tcompatibility", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>\n\nBecause of hardware limitation based on the old version of hns3 network\nengine, there are some restrictions:\na) HNS3 PMD driver needs select different processing mode for VLAN based\n on whether PVID is set which means our driver need sense the PVID\n states.\nb) For packets transmitting process, only two layer of VLAN tag is\n supported. If the total number of VLAN tags in mbuf and VLAN offload\n by haredware (VLAN insert by descriptor) exceeds two, the VLAN in mbuf\n will be overwritten by VLAN in the descriptor.\nc) If port based VLAN is set, only one VLAN header is allowed in mbuf or\n it will be discard by hardware.\n\nIn order to solve these restriction, two change is implemented on the new\nverions of network engine.\n1) add a new VLAN tagged insertion mode, named tag shift mode;\n2) add a new VLAN strip control bit, named strip hide enable;\n\nThe tag shift mode means that VLAN tag will shift automatically when the\ninserted place has a tag. For PMD driver, the VLAN tag1 and tag2\nconfigurations in Tx side do not need to be considered because the hardware\ncompletes it. However, the related configuration will still be retained to\nbe compatible with the old version of network engine.\n\nThe VLAN strip hide means that hardware will strip the VLAN tag and hide\nVLAN in descriptor (VLAN ID exposed as zero and related STRIP_TAGP is off).\n\nThese changes make it no longer necessary for the hns3 PMD driver to be\naware of the PVID status and have the ability to send mult-layer (more than\ntwo) VLANs packets. Therefore, hns3 PMD driver introduces the concept of\nVLAN mode and adds a new VLAN mode named HNS3_PVID_MODE to indicate that\nPVID-related IO process can be implemented by the hardware. And VF driver\ndoes not need to be modified because the related mailbox messages will not\nbe sent by PF kernel mode netdev driver under new network engine and all\nthe related hardware configuration is on the PF side.\n\nSigned-off-by: Chengchang Tang <tangchengchang@huawei.com>\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.h | 3 +++\n drivers/net/hns3/hns3_ethdev.c | 33 ++++++++++++++++++++----\n drivers/net/hns3/hns3_ethdev.h | 58 +++++++++++++++++++++++++++++++++++-------\n drivers/net/hns3/hns3_mbx.c | 2 +-\n drivers/net/hns3/hns3_rxtx.c | 48 ++++++++++++++++++++++++++--------\n drivers/net/hns3/hns3_rxtx.h | 39 ++++++++++++++++++----------\n 6 files changed, 144 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex 87d6053..629b114 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -449,11 +449,14 @@ struct hns3_umv_spc_alc_cmd {\n #define HNS3_CFG_NIC_ROCE_SEL_B\t\t4\n #define HNS3_ACCEPT_TAG2_B\t\t5\n #define HNS3_ACCEPT_UNTAG2_B\t\t6\n+#define HNS3_TAG_SHIFT_MODE_EN_B\t7\n \n #define HNS3_REM_TAG1_EN_B\t\t0\n #define HNS3_REM_TAG2_EN_B\t\t1\n #define HNS3_SHOW_TAG1_EN_B\t\t2\n #define HNS3_SHOW_TAG2_EN_B\t\t3\n+#define HNS3_DISCARD_TAG1_EN_B\t\t5\n+#define HNS3_DISCARD_TAG2_EN_B\t\t6\n \n /* Factor used to calculate offset and bitmap of VF num */\n #define HNS3_VF_NUM_PER_CMD 64\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 73d5042..3e98df3 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -477,6 +477,11 @@ hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,\n \thns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,\n \t\t vcfg->vlan2_vlan_prionly ? 1 : 0);\n \n+\t/* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */\n+\thns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,\n+\t\t vcfg->strip_tag1_discard_en ? 1 : 0);\n+\thns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,\n+\t\t vcfg->strip_tag2_discard_en ? 1 : 0);\n \t/*\n \t * In current version VF is not supported when PF is driven by DPDK\n \t * driver, just need to configure parameters for PF vport.\n@@ -518,11 +523,14 @@ hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)\n \tif (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {\n \t\trxvlan_cfg.strip_tag1_en = false;\n \t\trxvlan_cfg.strip_tag2_en = enable;\n+\t\trxvlan_cfg.strip_tag2_discard_en = false;\n \t} else {\n \t\trxvlan_cfg.strip_tag1_en = enable;\n \t\trxvlan_cfg.strip_tag2_en = true;\n+\t\trxvlan_cfg.strip_tag2_discard_en = true;\n \t}\n \n+\trxvlan_cfg.strip_tag1_discard_en = false;\n \trxvlan_cfg.vlan1_vlan_prionly = false;\n \trxvlan_cfg.vlan2_vlan_prionly = false;\n \trxvlan_cfg.rx_vlan_offload_en = enable;\n@@ -678,6 +686,10 @@ hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,\n \t\t vcfg->insert_tag2_en ? 1 : 0);\n \thns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);\n \n+\t/* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */\n+\thns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,\n+\t\t vcfg->tag_shift_mode_en ? 1 : 0);\n+\n \t/*\n \t * In current version VF is not supported when PF is driven by DPDK\n \t * driver, just need to configure parameters for PF vport.\n@@ -707,7 +719,8 @@ hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,\n \t\ttxvlan_cfg.insert_tag1_en = false;\n \t\ttxvlan_cfg.default_tag1 = 0;\n \t} else {\n-\t\ttxvlan_cfg.accept_tag1 = false;\n+\t\ttxvlan_cfg.accept_tag1 =\n+\t\t\thw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;\n \t\ttxvlan_cfg.insert_tag1_en = true;\n \t\ttxvlan_cfg.default_tag1 = pvid;\n \t}\n@@ -717,6 +730,7 @@ hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,\n \ttxvlan_cfg.accept_untag2 = true;\n \ttxvlan_cfg.insert_tag2_en = false;\n \ttxvlan_cfg.default_tag2 = 0;\n+\ttxvlan_cfg.tag_shift_mode_en = true;\n \n \tret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);\n \tif (ret) {\n@@ -841,14 +855,17 @@ hns3_en_pvid_strip(struct hns3_adapter *hns, int on)\n \tbool rx_strip_en;\n \tint ret;\n \n-\trx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;\n+\trx_strip_en = old_cfg->rx_vlan_offload_en;\n \tif (on) {\n \t\trx_vlan_cfg.strip_tag1_en = rx_strip_en;\n \t\trx_vlan_cfg.strip_tag2_en = true;\n+\t\trx_vlan_cfg.strip_tag2_discard_en = true;\n \t} else {\n \t\trx_vlan_cfg.strip_tag1_en = false;\n \t\trx_vlan_cfg.strip_tag2_en = rx_strip_en;\n+\t\trx_vlan_cfg.strip_tag2_discard_en = false;\n \t}\n+\trx_vlan_cfg.strip_tag1_discard_en = false;\n \trx_vlan_cfg.vlan1_vlan_prionly = false;\n \trx_vlan_cfg.vlan2_vlan_prionly = false;\n \trx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;\n@@ -940,9 +957,13 @@ hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)\n \trte_spinlock_unlock(&hw->lock);\n \tif (ret)\n \t\treturn ret;\n-\n-\tif (pvid_en_state_change)\n-\t\thns3_update_all_queues_pvid_state(hw);\n+\t/*\n+\t * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx\n+\t * need be processed by PMD driver.\n+\t */\n+\tif (pvid_en_state_change &&\n+\t hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)\n+\t\thns3_update_all_queues_pvid_proc_en(hw);\n \n \treturn 0;\n }\n@@ -2904,6 +2925,7 @@ hns3_get_capability(struct hns3_hw *hw)\n \t\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;\n \t\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;\n \t\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;\n+\t\thw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;\n \t\thw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;\n \t\treturn 0;\n \t}\n@@ -2919,6 +2941,7 @@ hns3_get_capability(struct hns3_hw *hw)\n \thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;\n \thw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;\n \thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;\n+\thw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;\n \thw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;\n \n \treturn 0;\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex fd6a9f9..a70223f 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -37,6 +37,9 @@\n #define HNS3_PF_FUNC_ID\t\t\t0\n #define HNS3_1ST_VF_FUNC_ID\t\t1\n \n+#define HNS3_SW_SHIFT_AND_DISCARD_MODE\t\t0\n+#define HNS3_HW_SHIFT_AND_DISCARD_MODE\t\t1\n+\n #define HNS3_UC_MACADDR_NUM\t\t128\n #define HNS3_VF_UC_MACADDR_NUM\t\t48\n #define HNS3_MC_MACADDR_NUM\t\t128\n@@ -474,6 +477,28 @@ struct hns3_hw {\n \n \tstruct hns3_queue_intr intr;\n \n+\t/*\n+\t * vlan mode.\n+\t * value range:\n+\t * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE\n+\t *\n+\t * - HNS3_SW_SHIFT_AND_DISCARD_MODE\n+\t * For some versions of hardware network engine, because of the\n+\t * hardware limitation, PMD driver needs to detect the PVID status\n+\t * to work with haredware to implement PVID-related functions.\n+\t * For example, driver need discard the stripped PVID tag to ensure\n+\t * the PVID will not report to mbuf and shift the inserted VLAN tag\n+\t * to avoid port based VLAN covering it.\n+\t *\n+\t * - HNS3_HW_SHIT_AND_DISCARD_MODE\n+\t * PMD driver does not need to process PVID-related functions in\n+\t * I/O process, Hardware will adjust the sequence between port based\n+\t * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by\n+\t * PVID will be invisible to driver. And in this mode, hns3 is able\n+\t * to send a multi-layer VLAN packets when hw VLAN insert offload\n+\t * is enabled.\n+\t */\n+\tuint8_t vlan_mode;\n \tuint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */\n \n \tstruct hns3_port_base_vlan_config port_base_vlan_cfg;\n@@ -532,11 +557,21 @@ struct hns3_user_vlan_table {\n \n /* Vlan tag configuration for RX direction */\n struct hns3_rx_vtag_cfg {\n-\tuint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */\n-\tuint8_t strip_tag1_en; /* Whether strip inner vlan tag */\n-\tuint8_t strip_tag2_en; /* Whether strip outer vlan tag */\n-\tuint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */\n-\tuint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */\n+\tbool rx_vlan_offload_en; /* Whether enable rx vlan offload */\n+\tbool strip_tag1_en; /* Whether strip inner vlan tag */\n+\tbool strip_tag2_en; /* Whether strip outer vlan tag */\n+\t/*\n+\t * If strip_tag_en is enabled, this bit decide whether to map the vlan\n+\t * tag to descriptor.\n+\t */\n+\tbool strip_tag1_discard_en;\n+\tbool strip_tag2_discard_en;\n+\t/*\n+\t * If this bit is enabled, only map inner/outer priority to descriptor\n+\t * and the vlan tag is always 0.\n+\t */\n+\tbool vlan1_vlan_prionly;\n+\tbool vlan2_vlan_prionly;\n };\n \n /* Vlan tag configuration for TX direction */\n@@ -545,10 +580,15 @@ struct hns3_tx_vtag_cfg {\n \tbool accept_untag1; /* Whether accept untag1 packet from host */\n \tbool accept_tag2;\n \tbool accept_untag2;\n-\tbool insert_tag1_en; /* Whether insert inner vlan tag */\n-\tbool insert_tag2_en; /* Whether insert outer vlan tag */\n-\tuint16_t default_tag1; /* The default inner vlan tag to insert */\n-\tuint16_t default_tag2; /* The default outer vlan tag to insert */\n+\tbool insert_tag1_en; /* Whether insert outer vlan tag */\n+\tbool insert_tag2_en; /* Whether insert inner vlan tag */\n+\t/*\n+\t * In shift mode, hw will shift the sequence of port based VLAN and\n+\t * BD VLAN.\n+\t */\n+\tbool tag_shift_mode_en; /* hw shift vlan tag automatically */\n+\tuint16_t default_tag1; /* The default outer vlan tag to insert */\n+\tuint16_t default_tag2; /* The default inner vlan tag to insert */\n };\n \n struct hns3_vtag_cfg {\ndiff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c\nindex 2510582..305007a 100644\n--- a/drivers/net/hns3/hns3_mbx.c\n+++ b/drivers/net/hns3/hns3_mbx.c\n@@ -347,7 +347,7 @@ hns3_update_port_base_vlan_info(struct hns3_hw *hw,\n \t */\n \tif (hw->port_base_vlan_cfg.state != new_pvid_state) {\n \t\thw->port_base_vlan_cfg.state = new_pvid_state;\n-\t\thns3_update_all_queues_pvid_state(hw);\n+\t\thns3_update_all_queues_pvid_proc_en(hw);\n \t}\n }\n \ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex 816c39c..cf55d94 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -339,26 +339,26 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)\n }\n \n void\n-hns3_update_all_queues_pvid_state(struct hns3_hw *hw)\n+hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)\n {\n \tuint16_t nb_rx_q = hw->data->nb_rx_queues;\n \tuint16_t nb_tx_q = hw->data->nb_tx_queues;\n \tstruct hns3_rx_queue *rxq;\n \tstruct hns3_tx_queue *txq;\n-\tint pvid_state;\n+\tbool pvid_en;\n \tint i;\n \n-\tpvid_state = hw->port_base_vlan_cfg.state;\n+\tpvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;\n \tfor (i = 0; i < hw->cfg_max_queues; i++) {\n \t\tif (i < nb_rx_q) {\n \t\t\trxq = hw->data->rx_queues[i];\n \t\t\tif (rxq != NULL)\n-\t\t\t\trxq->pvid_state = pvid_state;\n+\t\t\t\trxq->pvid_sw_discard_en = pvid_en;\n \t\t}\n \t\tif (i < nb_tx_q) {\n \t\t\ttxq = hw->data->tx_queues[i];\n \t\t\tif (txq != NULL)\n-\t\t\t\ttxq->pvid_state = pvid_state;\n+\t\t\t\ttxq->pvid_sw_shift_en = pvid_en;\n \t\t}\n \t}\n }\n@@ -1405,7 +1405,20 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,\n \trxq->pkt_first_seg = NULL;\n \trxq->pkt_last_seg = NULL;\n \trxq->port_id = dev->data->port_id;\n-\trxq->pvid_state = hw->port_base_vlan_cfg.state;\n+\t/*\n+\t * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,\n+\t * the pvid_sw_discard_en in the queue struct should not be changed,\n+\t * because PVID-related operations do not need to be processed by PMD\n+\t * driver. For hns3 VF device, whether it needs to process PVID depends\n+\t * on the configuration of PF kernel mode netdevice driver. And the\n+\t * related PF configuration is delivered through the mailbox and finally\n+\t * reflectd in port_base_vlan_cfg.\n+\t */\n+\tif (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)\n+\t\trxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==\n+\t\t\t\t HNS3_PORT_BASE_VLAN_ENABLE;\n+\telse\n+\t\trxq->pvid_sw_discard_en = false;\n \trxq->configured = true;\n \trxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +\n \t\t\t\tidx * HNS3_TQP_REG_SIZE);\n@@ -1592,7 +1605,7 @@ hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,\n \t};\n \tstrip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,\n \t\t\t\t HNS3_RXD_STRP_TAGP_S);\n-\treport_mode = report_type[rxq->pvid_state][strip_status];\n+\treport_mode = report_type[rxq->pvid_sw_discard_en][strip_status];\n \tswitch (report_mode) {\n \tcase HNS3_NO_STRP_VLAN_VLD:\n \t\tmb->vlan_tci = 0;\n@@ -2151,7 +2164,20 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,\n \t}\n \n \ttxq->port_id = dev->data->port_id;\n-\ttxq->pvid_state = hw->port_base_vlan_cfg.state;\n+\t/*\n+\t * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,\n+\t * the pvid_sw_shift_en in the queue struct should not be changed,\n+\t * because PVID-related operations do not need to be processed by PMD\n+\t * driver. For hns3 VF device, whether it needs to process PVID depends\n+\t * on the configuration of PF kernel mode netdev driver. And the\n+\t * related PF configuration is delivered through the mailbox and finally\n+\t * reflectd in port_base_vlan_cfg.\n+\t */\n+\tif (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)\n+\t\ttxq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==\n+\t\t\t\t\tHNS3_PORT_BASE_VLAN_ENABLE;\n+\telse\n+\t\ttxq->pvid_sw_shift_en = false;\n \ttxq->configured = true;\n \ttxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +\n \t\t\t\tidx * HNS3_TQP_REG_SIZE);\n@@ -2352,7 +2378,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,\n \t * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should\n \t * be added to the position close to the IP header when PVID is enabled.\n \t */\n-\tif (!txq->pvid_state && ol_flags & (PKT_TX_VLAN_PKT |\n+\tif (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |\n \t\t\t\tPKT_TX_QINQ_PKT)) {\n \t\tdesc->tx.ol_type_vlan_len_msec |=\n \t\t\t\trte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));\n@@ -2365,7 +2391,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,\n \t}\n \n \tif (ol_flags & PKT_TX_QINQ_PKT ||\n-\t ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_state)) {\n+\t ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {\n \t\tdesc->tx.type_cs_vlan_tso_len |=\n \t\t\t\t\trte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));\n \t\tdesc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);\n@@ -2791,7 +2817,7 @@ hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)\n \tstruct rte_ether_hdr *eh;\n \tstruct rte_vlan_hdr *vh;\n \n-\tif (!txq->pvid_state)\n+\tif (!txq->pvid_sw_shift_en)\n \t\treturn 0;\n \n \t/*\ndiff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex 27041ab..476cfc2 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -273,7 +273,6 @@ struct hns3_rx_queue {\n \tuint64_t rx_ring_phys_addr; /* RX ring DMA address */\n \tconst struct rte_memzone *mz;\n \tstruct hns3_entry *sw_ring;\n-\n \tstruct rte_mbuf *pkt_first_seg;\n \tstruct rte_mbuf *pkt_last_seg;\n \n@@ -290,17 +289,24 @@ struct hns3_rx_queue {\n \tuint16_t rx_free_hold; /* num of BDs waited to passed to hardware */\n \tuint16_t rx_rearm_start; /* index of BD that driver re-arming from */\n \tuint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */\n-\t/*\n-\t * port based vlan configuration state.\n-\t * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE\n-\t */\n-\tuint16_t pvid_state;\n \n \t/* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */\n \tuint8_t crc_len;\n \n \tbool rx_deferred_start; /* don't start this queue in dev start */\n \tbool configured; /* indicate if rx queue has been configured */\n+\t/*\n+\t * Indicate whether ignore the outer VLAN field in the Rx BD reported\n+\t * by the Hardware. Because the outer VLAN is the PVID if the PVID is\n+\t * set for some version of hardware network engine whose vlan mode is\n+\t * HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920. And this VLAN\n+\t * should not be transitted to the upper-layer application. For hardware\n+\t * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,\n+\t * such as kunpeng 930, PVID will not be reported to the BDs. So, PMD\n+\t * driver does not need to perform PVID-related operation in Rx. At this\n+\t * point, the pvid_sw_discard_en will be false.\n+\t */\n+\tbool pvid_sw_discard_en;\n \n \tuint64_t l2_errors;\n \tuint64_t pkt_len_errors;\n@@ -361,12 +367,6 @@ struct hns3_tx_queue {\n \tstruct rte_mbuf **free;\n \n \t/*\n-\t * port based vlan configuration state.\n-\t * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE\n-\t */\n-\tuint16_t pvid_state;\n-\n-\t/*\n \t * The minimum length of the packet supported by hardware in the Tx\n \t * direction.\n \t */\n@@ -374,6 +374,19 @@ struct hns3_tx_queue {\n \n \tbool tx_deferred_start; /* don't start this queue in dev start */\n \tbool configured; /* indicate if tx queue has been configured */\n+\t/*\n+\t * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field\n+\t * of Tx BD. Because the outer VLAN will always be the PVID when the\n+\t * PVID is set and for some version of hardware network engine whose\n+\t * vlan mode is HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920, the\n+\t * PVID will overwrite the outer VLAN field of Tx BD. For the hardware\n+\t * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,\n+\t * such as kunpeng 930, if the PVID is set, the hardware will shift the\n+\t * VLAN field automatically. So, PMD driver does not need to do\n+\t * PVID-related operations in Tx. And pvid_sw_shift_en will be false at\n+\t * this point.\n+\t */\n+\tbool pvid_sw_shift_en;\n \n \t/*\n \t * The following items are used for the abnormal errors statistics in\n@@ -620,7 +633,7 @@ int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,\n \t\t\t\t uint16_t nb_tx_q);\n int hns3_config_gro(struct hns3_hw *hw, bool en);\n int hns3_restore_gro_conf(struct hns3_hw *hw);\n-void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);\n+void hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw);\n void hns3_rx_scattered_reset(struct rte_eth_dev *dev);\n void hns3_rx_scattered_calc(struct rte_eth_dev *dev);\n int hns3_rx_check_vec_support(struct rte_eth_dev *dev);\n", "prefixes": [ "01/17" ] }