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GET /api/patches/78306/?format=api
{ "id": 78306, "url": "http://patches.dpdk.org/api/patches/78306/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-58-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600764594-14752-58-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600764594-14752-58-git-send-email-arybchenko@solarflare.com", "date": "2020-09-22T08:49:51", "name": "[57/60] common/sfc_efx/base: poll extended width event queues", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "df77150e59b74e40be32ad7ed917dd99e9d8d5c3", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-58-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12400, "url": "http://patches.dpdk.org/api/series/12400/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12400", "date": "2020-09-22T08:48:59", "name": "common/sfc_efx: support Riverhead NIC family", "version": 1, "mbox": "http://patches.dpdk.org/series/12400/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/78306/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/78306/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 49517A04E1;\n\tTue, 22 Sep 2020 11:00:20 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1C6B21DC08;\n\tTue, 22 Sep 2020 10:51:36 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 2F6881D8CE\n for <dev@dpdk.org>; Tue, 22 Sep 2020 10:50:25 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.144])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n D1CA820074 for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:24 +0000 (UTC)", "from us4-mdac16-52.at1.mdlocal (unknown [10.110.48.101])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id D1556800A4\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:24 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.7])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 7099A40070\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:24 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 391E54C005B\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:24 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 22 Sep 2020 09:50:12 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 22 Sep 2020 09:50:12 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08M8oCBs004848;\n Tue, 22 Sep 2020 09:50:12 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 33A651613CB;\n Tue, 22 Sep 2020 09:50:12 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@xilinx.com>", "Date": "Tue, 22 Sep 2020 09:49:51 +0100", "Message-ID": "<1600764594-14752-58-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-4.197500-8.000000-10", "X-TMASE-MatchedRID": "zZSWqN8v4xXm8Tq/Qity6m0lh85vSrk7AKbvziCwm7j82ks92f+Gmki5\n 7L1pIMlU4f0uNTtAwnss/31GzKkTsX8f69f8DWLaPwKTD1v8YV5MkOX0UoduufdG7cmuMnEoeKa\n jvO6uWnBgS8jnMi9jc4O9WUy4j2mWTj/OlUrKzKxbUzvsaHW6BuqhuTPUDQDthNrreBB7zJkU+5\n qF9ri1FdgjUjMlWxbFFFGVHCK0F0mpmFGiu41fIwdc+KHUCr/8BGvINcfHqheuiyJNZGE/if+Mw\n M4d0pxTD1xtEq6z2nVwdMejP5s0hcMlA9qlu+4CB89GKHo03naZ2scyRQcerx53XUX0iwoUBrP/\n oSIO7kFvgkneme+Cc+PaI7IZzuYes3GguTHcJA66iJsmkdGsWX0tCKdnhB589yM15V5aWpj6C0e\n Ps7A07Vg3wwZ5miMr1UZUc1O2FAcJZu4ZrytgUQo2x7DGF8tgy4tJ9hRKx3IDbonMZy4dIGa8I+\n y3KVONCKEifWOBCqNwEYLvEvgQN763IuBi/qGJ2kC7SwvGlKhDwb7Jglhh1lFkOwaJdCKgviPEq\n cclEtzAvpLE+mvX8g==", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--4.197500-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600764624-KrgVkJfUSpxV", "Subject": "[dpdk-dev] [PATCH 57/60] common/sfc_efx/base: poll extended width\n\tevent queues", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@xilinx.com>\n\nExtended width queues use a different layout and so require\na different polling loop.\n\nSigned-off-by: Andy Moreton <amoreton@xilinx.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/common/sfc_efx/base/rhead_ev.c | 155 ++++++++++++++++++++++++-\n 1 file changed, 154 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/rhead_ev.c b/drivers/common/sfc_efx/base/rhead_ev.c\nindex 49d7c3f69d..0458104c64 100644\n--- a/drivers/common/sfc_efx/base/rhead_ev.c\n+++ b/drivers/common/sfc_efx/base/rhead_ev.c\n@@ -30,7 +30,6 @@ rhead_ev_tx_completion(\n \t__in\t\tconst efx_ev_callbacks_t *eecp,\n \t__in_opt\tvoid *arg);\n \n-\n static\t__checkReturn\tboolean_t\n rhead_ev_mcdi(\n \t__in\t\tefx_evq_t *eep,\n@@ -38,6 +37,22 @@ rhead_ev_mcdi(\n \t__in\t\tconst efx_ev_callbacks_t *eecp,\n \t__in_opt\tvoid *arg);\n \n+#if EFSYS_OPT_EV_EXTENDED_WIDTH\n+static\t\t\tboolean_t\n+rhead_ev_ew_dispatch(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tefx_xword_t *eventp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg);\n+\n+static\t\t\tvoid\n+rhead_ev_ew_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg);\n+#endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */\n+\n \n \t__checkReturn\tefx_rc_t\n rhead_ev_init(\n@@ -200,6 +215,13 @@ rhead_ev_qpoll(\n \tunsigned int index;\n \tsize_t offset;\n \n+#if EFSYS_OPT_EV_EXTENDED_WIDTH\n+\tif (eep->ee_flags & EFX_EVQ_FLAGS_EXTENDED_WIDTH) {\n+\t\trhead_ev_ew_qpoll(eep, countp, eecp, arg);\n+\t\treturn;\n+\t}\n+#endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */\n+\n \tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n \tEFSYS_ASSERT(countp != NULL);\n \tEFSYS_ASSERT(eecp != NULL);\n@@ -285,6 +307,137 @@ rhead_ev_qpoll(\n \t*countp = count;\n }\n \n+#if EFSYS_OPT_EV_EXTENDED_WIDTH\n+static\t\t\tboolean_t\n+rhead_ev_ew_dispatch(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tefx_xword_t *eventp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg)\n+{\n+\tboolean_t should_abort;\n+\tuint32_t code;\n+\n+\tEFSYS_ASSERT((eep->ee_flags & EFX_EVQ_FLAGS_EXTENDED_WIDTH) != 0);\n+\n+\tcode = EFX_XWORD_FIELD(*eventp, ESF_GZ_EV_256_EV32_TYPE);\n+\tswitch (code) {\n+\tdefault:\n+\t\t/* Omit currently unused reserved bits from the probe. */\n+\t\tEFSYS_PROBE7(ew_bad_event, unsigned int, eep->ee_index,\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_7),\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_4),\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_3),\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_2),\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_1),\n+\t\t uint32_t, EFX_XWORD_FIELD(*eventp, EFX_DWORD_0));\n+\n+\t\tEFSYS_ASSERT(eecp->eec_exception != NULL);\n+\t\t(void) eecp->eec_exception(arg, EFX_EXCEPTION_EV_ERROR, code);\n+\t\tshould_abort = B_TRUE;\n+\t}\n+\n+\treturn (should_abort);\n+}\n+\n+/*\n+ * Poll extended width event queue. Size of the batch is equal to cache line\n+ * size divided by event size.\n+ */\n+#define\tEF100_EV_EW_BATCH\t2\n+\n+/*\n+ * Check if event is present.\n+ *\n+ * Riverhead EvQs use a phase bit to indicate the presence of valid events,\n+ * by flipping the phase bit on each wrap of the write index.\n+ */\n+#define\tEF100_EV_EW_PRESENT(_xword, _phase_bit)\t\t\t\t\\\n+\t(EFX_XWORD_FIELD((_xword), ESF_GZ_EV_256_EV32_PHASE) == (_phase_bit))\n+\n+static\t\t\tvoid\n+rhead_ev_ew_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg)\n+{\n+\tefx_xword_t ev[EF100_EV_EW_BATCH];\n+\tunsigned int batch;\n+\tunsigned int phase_bit;\n+\tunsigned int total;\n+\tunsigned int count;\n+\tunsigned int index;\n+\tsize_t offset;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\tEFSYS_ASSERT((eep->ee_flags & EFX_EVQ_FLAGS_EXTENDED_WIDTH) != 0);\n+\tEFSYS_ASSERT(countp != NULL);\n+\tEFSYS_ASSERT(eecp != NULL);\n+\n+\tcount = *countp;\n+\tdo {\n+\t\t/* Read up until the end of the batch period */\n+\t\tbatch = EF100_EV_EW_BATCH - (count & (EF100_EV_EW_BATCH - 1));\n+\t\tphase_bit = (count & (eep->ee_mask + 1)) != 0;\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_xword_t);\n+\t\tfor (total = 0; total < batch; ++total) {\n+\t\t\tEFSYS_MEM_READX(eep->ee_esmp, offset, &(ev[total]));\n+\n+\t\t\tif (!EF100_EV_EW_PRESENT(ev[total], phase_bit))\n+\t\t\t\tbreak;\n+\n+\t\t\t/* Omit unused reserved bits from the probe. */\n+\t\t\tEFSYS_PROBE7(ew_event, unsigned int, eep->ee_index,\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_7),\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_4),\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_3),\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_2),\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_1),\n+\t\t\t uint32_t, EFX_XWORD_FIELD(ev[total], EFX_DWORD_0));\n+\n+\t\t\toffset += sizeof (efx_xword_t);\n+\t\t}\n+\n+\t\t/* Process the batch of events */\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tboolean_t should_abort;\n+\n+\t\t\tEFX_EV_QSTAT_INCR(eep, EV_ALL);\n+\n+\t\t\tshould_abort =\n+\t\t\t rhead_ev_ew_dispatch(eep, &(ev[index]), eecp, arg);\n+\n+\t\t\tif (should_abort) {\n+\t\t\t\t/* Ignore subsequent events */\n+\t\t\t\ttotal = index + 1;\n+\n+\t\t\t\t/*\n+\t\t\t\t * Poison batch to ensure the outer\n+\t\t\t\t * loop is broken out of.\n+\t\t\t\t */\n+\t\t\t\tEFSYS_ASSERT(batch <= EF100_EV_EW_BATCH);\n+\t\t\t\tbatch += (EF100_EV_EW_BATCH << 1);\n+\t\t\t\tEFSYS_ASSERT(total != batch);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * There is no necessity to clear processed events since\n+\t\t * phase bit which is flipping on each write index wrap\n+\t\t * is used for event presence indication.\n+\t\t */\n+\n+\t\tcount += total;\n+\n+\t} while (total == batch);\n+\n+\t*countp = count;\n+}\n+#endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */\n+\n+\n \t__checkReturn\tefx_rc_t\n rhead_ev_qmoderate(\n \t__in\t\tefx_evq_t *eep,\n", "prefixes": [ "57/60" ] }