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GET /api/patches/78269/?format=api
{ "id": 78269, "url": "http://patches.dpdk.org/api/patches/78269/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-15-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600764594-14752-15-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600764594-14752-15-git-send-email-arybchenko@solarflare.com", "date": "2020-09-22T08:49:08", "name": "[14/60] common/sfc_efx/base: add Riverhead support to NIC module", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "101c2465a11228416c99641cc1087714c2777d33", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-15-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12400, "url": "http://patches.dpdk.org/api/series/12400/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12400", "date": "2020-09-22T08:48:59", "name": "common/sfc_efx: support Riverhead NIC family", "version": 1, "mbox": "http://patches.dpdk.org/series/12400/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/78269/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/78269/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C9F4CA04E1;\n\tTue, 22 Sep 2020 10:53:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 494F71DAF5;\n\tTue, 22 Sep 2020 10:50:51 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id D33261D70C\n for <dev@dpdk.org>; Tue, 22 Sep 2020 10:50:18 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.143])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 7F87820051 for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:18 +0000 (UTC)", "from us4-mdac16-59.at1.mdlocal (unknown [10.110.50.152])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 7ED8B8009B\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:18 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.12])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id E640240072\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 82BEE4005B\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 22 Sep 2020 09:50:09 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 22 Sep 2020 09:50:09 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08M8o9C1004638\n for <dev@dpdk.org>; Tue, 22 Sep 2020 09:50:09 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id A07321613A9\n for <dev@dpdk.org>; Tue, 22 Sep 2020 09:50:09 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Tue, 22 Sep 2020 09:49:08 +0100", "Message-ID": "<1600764594-14752-15-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-20.260100-8.000000-10", "X-TMASE-MatchedRID": "Q+PCvE2fENvabBVcqlDcF2wTEruL9ObTP6Tki+9nU39XiLrvhpKLfEAc\n 6DyoS2rIqQ4DH3i/D96tmhK3i1SK3y5Ara2x6EWazfqlpbtmcWhHcT14gBzqVg6QlBHhBZuwrvF\n YQ6ItqCik8KUgXucz7APVs5ktLr8djGILeNCFU/miAZ3zAhQYgo7P8sslRxoe4uxAgOavdLnSJJ\n cbp1Y+W278DSzaDuLBC2AKz19Qy/SlSstbEunVIAfC4JY9IggAxEksT8U2vYNHZg0gWH5yUcA3U\n eFsJzySaonT5WkIBWAPkyd+0GAinzTkUDpmb5dU4jnQTqD4CzQ4eGohd7gjNpiQXtm0V8JTJzlo\n WWMvKh20STX07mgcBcAANTVLSQFz3qZ3A4FG8d1ff79rzPd1mEewdu9S21aifkiy7TTogYYVLGI\n PVP4OQb/YkCk00rZtilCnnNoI9t0vmfQHDKJ1l4lLa95lbECYWC0RiLhMMl+dzjX37VUcWt+zQy\n BPDfsFgjygCLh5uNM6kswMLieVlEozHx70qoh4U9ht8cPjV47J5SXtoJPLyP/zPz0A8BuVD2VMA\n 3hbGfEnvY93EdQxLMlv9UbTsgXrbUDm/Odva3nO0WfNhCnjXF0DithooYrCd3XtjqAaoMIsWXnB\n f/Tq0qCQFlbvrjaOpdHaghyrHZTecSkNT7l/2Z8bz5uL7/e88boZEVitthhUJnGNRkHyM9O6Q5c\n VbfMni1DLgYIPUP6NXA6IRCXBU5pzYJ7huWQgPja3w1ExF8QF/7WGX+q/8NEsTITobgNEbasOqx\n HBOjdFQ7qCGsajLlsBNccCwHdvPFrxOr//W2KeAiCmPx4NwJuJ+Pb8n/VxMhmTylWIkjEqtq5d3\n cxkNQP90fJP9eHt", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--20.260100-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600764618-nnCrk_BIjiXu", "Subject": "[dpdk-dev] [PATCH 14/60] common/sfc_efx/base: add Riverhead support\n\tto NIC module", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Define basic NIC features and limitations.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\nReviewed-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>\n---\n drivers/common/sfc_efx/base/ef10_impl.h | 25 ++\n drivers/common/sfc_efx/base/ef10_nic.c | 52 ++-\n drivers/common/sfc_efx/base/efx_impl.h | 8 +-\n drivers/common/sfc_efx/base/efx_mcdi.c | 4 +-\n drivers/common/sfc_efx/base/efx_nic.c | 34 ++\n drivers/common/sfc_efx/base/meson.build | 3 +-\n drivers/common/sfc_efx/base/rhead_impl.h | 105 +++++\n drivers/common/sfc_efx/base/rhead_nic.c | 500 +++++++++++++++++++++++\n 8 files changed, 716 insertions(+), 15 deletions(-)\n create mode 100644 drivers/common/sfc_efx/base/rhead_impl.h\n create mode 100644 drivers/common/sfc_efx/base/rhead_nic.c", "diff": "diff --git a/drivers/common/sfc_efx/base/ef10_impl.h b/drivers/common/sfc_efx/base/ef10_impl.h\nindex da0ec7fab5..e933d88135 100644\n--- a/drivers/common/sfc_efx/base/ef10_impl.h\n+++ b/drivers/common/sfc_efx/base/ef10_impl.h\n@@ -1422,12 +1422,37 @@ efx_mcdi_get_vector_cfg(\n \t__out_opt\tuint32_t *pf_nvecp,\n \t__out_opt\tuint32_t *vf_nvecp);\n \n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+efx_mcdi_alloc_vis(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t min_vi_count,\n+\t__in\t\tuint32_t max_vi_count,\n+\t__out\t\tuint32_t *vi_basep,\n+\t__out\t\tuint32_t *vi_countp,\n+\t__out\t\tuint32_t *vi_shiftp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+efx_mcdi_free_vis(\n+\t__in\t\tefx_nic_t *enp);\n+\n LIBEFX_INTERNAL\n extern\t__checkReturn\t\tefx_rc_t\n ef10_get_privilege_mask(\n \t__in\t\t\tefx_nic_t *enp,\n \t__out\t\t\tuint32_t *maskp);\n \n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+efx_mcdi_nic_board_cfg(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+efx_mcdi_entity_reset(\n+\t__in\t\tefx_nic_t *enp);\n+\n #if EFSYS_OPT_FW_SUBVARIANT_AWARE\n \n LIBEFX_INTERNAL\ndiff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c\nindex c5990f16cc..80dc99aed5 100644\n--- a/drivers/common/sfc_efx/base/ef10_nic.c\n+++ b/drivers/common/sfc_efx/base/ef10_nic.c\n@@ -10,7 +10,7 @@\n #include \"mcdi_mon.h\"\n #endif\n \n-#if EFX_OPTS_EF10()\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n \n #include \"ef10_tlv_layout.h\"\n \n@@ -24,7 +24,7 @@ efx_mcdi_get_port_assignment(\n \t\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);\n \tefx_rc_t rc;\n \n-\tEFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));\n \n \treq.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;\n \treq.emr_in_buf = payload;\n@@ -68,7 +68,7 @@ efx_mcdi_get_port_modes(\n \t\tMC_CMD_GET_PORT_MODES_OUT_LEN);\n \tefx_rc_t rc;\n \n-\tEFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));\n \n \treq.emr_cmd = MC_CMD_GET_PORT_MODES;\n \treq.emr_in_buf = payload;\n@@ -223,6 +223,10 @@ ef10_nic_get_port_mode_bandwidth(\n \treturn (rc);\n }\n \n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n+\n+#if EFX_OPTS_EF10()\n+\n \t__checkReturn\t\tefx_rc_t\n efx_mcdi_vadaptor_alloc(\n \t__in\t\t\tefx_nic_t *enp,\n@@ -292,6 +296,10 @@ efx_mcdi_vadaptor_free(\n \treturn (rc);\n }\n \n+#endif\t/* EFX_OPTS_EF10() */\n+\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n+\n \t__checkReturn\tefx_rc_t\n efx_mcdi_get_mac_address_pf(\n \t__in\t\t\tefx_nic_t *enp,\n@@ -302,7 +310,7 @@ efx_mcdi_get_mac_address_pf(\n \t\tMC_CMD_GET_MAC_ADDRESSES_OUT_LEN);\n \tefx_rc_t rc;\n \n-\tEFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));\n \n \treq.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;\n \treq.emr_in_buf = payload;\n@@ -358,7 +366,7 @@ efx_mcdi_get_mac_address_vf(\n \t\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);\n \tefx_rc_t rc;\n \n-\tEFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));\n \n \treq.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;\n \treq.emr_in_buf = payload;\n@@ -420,7 +428,7 @@ efx_mcdi_get_clock(\n \t\tMC_CMD_GET_CLOCK_OUT_LEN);\n \tefx_rc_t rc;\n \n-\tEFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));\n \n \treq.emr_cmd = MC_CMD_GET_CLOCK;\n \treq.emr_in_buf = payload;\n@@ -569,7 +577,7 @@ efx_mcdi_get_vector_cfg(\n \treturn (rc);\n }\n \n-static\t__checkReturn\tefx_rc_t\n+\t__checkReturn\tefx_rc_t\n efx_mcdi_alloc_vis(\n \t__in\t\tefx_nic_t *enp,\n \t__in\t\tuint32_t min_vi_count,\n@@ -631,7 +639,7 @@ efx_mcdi_alloc_vis(\n }\n \n \n-static\t__checkReturn\tefx_rc_t\n+\t__checkReturn\tefx_rc_t\n efx_mcdi_free_vis(\n \t__in\t\tefx_nic_t *enp)\n {\n@@ -663,6 +671,9 @@ efx_mcdi_free_vis(\n \treturn (rc);\n }\n \n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n+\n+#if EFX_OPTS_EF10()\n \n static\t__checkReturn\tefx_rc_t\n efx_mcdi_alloc_piobuf(\n@@ -978,6 +989,10 @@ ef10_nic_pio_unlink(\n \treturn (efx_mcdi_unlink_piobuf(enp, vi_index));\n }\n \n+#endif\t/* EFX_OPTS_EF10() */\n+\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n+\n static\t__checkReturn\tefx_rc_t\n ef10_mcdi_get_pf_count(\n \t__in\t\tefx_nic_t *enp,\n@@ -1667,6 +1682,19 @@ static struct ef10_external_port_map_s {\n \t\t(1U << TLV_PORT_MODE_NA_2x2),\t\t\t/* mode 14 */\n \t\t{ EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n+\t/*\n+\t * Modes that on Riverhead allocate each port number to a separate\n+\t * cage.\n+\t *\tport 0 -> cage 1\n+\t *\tport 1 -> cage 2\n+\t */\n+\t{\n+\t\tEFX_FAMILY_RIVERHEAD,\n+\t\t(1U << TLV_PORT_MODE_1x1_NA) |\t\t\t/* mode 0 */\n+\t\t(1U << TLV_PORT_MODE_1x4_NA) |\t\t\t/* mode 1 */\n+\t\t(1U << TLV_PORT_MODE_1x1_1x1),\t\t\t/* mode 2 */\n+\t\t{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n+\t},\n };\n \n static\t__checkReturn\tefx_rc_t\n@@ -1757,7 +1785,7 @@ ef10_external_port_mapping(\n \treturn (rc);\n }\n \n-static\t__checkReturn\tefx_rc_t\n+\t__checkReturn\tefx_rc_t\n efx_mcdi_nic_board_cfg(\n \t__in\t\tefx_nic_t *enp)\n {\n@@ -1921,7 +1949,7 @@ efx_mcdi_nic_board_cfg(\n \treturn (rc);\n }\n \n-static\t__checkReturn\tefx_rc_t\n+\t__checkReturn\tefx_rc_t\n efx_mcdi_entity_reset(\n \t__in\t\tefx_nic_t *enp)\n {\n@@ -1954,6 +1982,10 @@ efx_mcdi_entity_reset(\n \treturn (rc);\n }\n \n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n+\n+#if EFX_OPTS_EF10()\n+\n static\t__checkReturn\tefx_rc_t\n ef10_set_workaround_bug26807(\n \t__in\t\tefx_nic_t *enp)\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex c7edeaa000..b41b0e5dea 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -41,6 +41,10 @@\n #include \"ef10_impl.h\"\n #endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n \n+#if EFSYS_OPT_RIVERHEAD\n+#include \"rhead_impl.h\"\n+#endif\t/* EFSYS_OPT_RIVERHEAD */\n+\n #ifdef\t__cplusplus\n extern \"C\" {\n #endif\n@@ -835,7 +839,7 @@ struct efx_nic_s {\n #endif\t/* EFSYS_OPT_SIENA */\n \t\tint\tenu_unused;\n \t} en_u;\n-#if EFX_OPTS_EF10()\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n \tunion en_arch {\n \t\tstruct {\n \t\t\tint\t\t\tena_vi_base;\n@@ -856,7 +860,7 @@ struct efx_nic_s {\n \t\t\tsize_t\t\t\tena_wc_mem_map_size;\n \t\t} ef10;\n \t} en_arch;\n-#endif\t/* EFX_OPTS_EF10() */\n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n #if EFSYS_OPT_EVB\n \tconst efx_evb_ops_t\t*en_eeop;\n \tstruct efx_vswitch_s *en_vswitchp;\ndiff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c\nindex dec3a170a7..ade7f7fed4 100644\n--- a/drivers/common/sfc_efx/base/efx_mcdi.c\n+++ b/drivers/common/sfc_efx/base/efx_mcdi.c\n@@ -2032,7 +2032,7 @@ efx_mcdi_mac_stats_periodic(\n \n #endif\t/* EFSYS_OPT_MAC_STATS */\n \n-#if EFX_OPTS_EF10()\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n \n /*\n * This function returns the pf and vf number of a function. If it is a pf the\n@@ -2129,7 +2129,7 @@ efx_mcdi_privilege_mask(\n \treturn (rc);\n }\n \n-#endif /* EFX_OPTS_EF10() */\n+#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n \n \t__checkReturn\t\tefx_rc_t\n efx_mcdi_set_workaround(\ndiff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c\nindex 9d6961e2ff..465e2c7a36 100644\n--- a/drivers/common/sfc_efx/base/efx_nic.c\n+++ b/drivers/common/sfc_efx/base/efx_nic.c\n@@ -188,6 +188,27 @@ static const efx_nic_ops_t\t__efx_nic_medford2_ops = {\n \n #endif\t/* EFSYS_OPT_MEDFORD2 */\n \n+#if EFSYS_OPT_RIVERHEAD\n+\n+static const efx_nic_ops_t\t__efx_nic_riverhead_ops = {\n+\trhead_nic_probe,\t\t/* eno_probe */\n+\trhead_board_cfg,\t\t/* eno_board_cfg */\n+\trhead_nic_set_drv_limits,\t/* eno_set_drv_limits */\n+\trhead_nic_reset,\t\t/* eno_reset */\n+\trhead_nic_init,\t\t\t/* eno_init */\n+\trhead_nic_get_vi_pool,\t\t/* eno_get_vi_pool */\n+\trhead_nic_get_bar_region,\t/* eno_get_bar_region */\n+\trhead_nic_hw_unavailable,\t/* eno_hw_unavailable */\n+\trhead_nic_set_hw_unavailable,\t/* eno_set_hw_unavailable */\n+#if EFSYS_OPT_DIAG\n+\trhead_nic_register_test,\t/* eno_register_test */\n+#endif\t/* EFSYS_OPT_DIAG */\n+\trhead_nic_fini,\t\t\t/* eno_fini */\n+\trhead_nic_unprobe,\t\t/* eno_unprobe */\n+};\n+\n+#endif\t/* EFSYS_OPT_RIVERHEAD */\n+\n \n \t__checkReturn\tefx_rc_t\n efx_nic_create(\n@@ -285,6 +306,19 @@ efx_nic_create(\n \t\tbreak;\n #endif\t/* EFSYS_OPT_MEDFORD2 */\n \n+#if EFSYS_OPT_RIVERHEAD\n+\tcase EFX_FAMILY_RIVERHEAD:\n+\t\tenp->en_enop = &__efx_nic_riverhead_ops;\n+\t\tenp->en_features =\n+\t\t EFX_FEATURE_IPV6 |\n+\t\t EFX_FEATURE_LINK_EVENTS |\n+\t\t EFX_FEATURE_PERIODIC_MAC_STATS |\n+\t\t EFX_FEATURE_MCDI |\n+\t\t EFX_FEATURE_MAC_HEADER_FILTERS |\n+\t\t EFX_FEATURE_MCDI_DMA;\n+\t\tbreak;\n+#endif\t/* EFSYS_OPT_RIVERHEAD */\n+\n \tdefault:\n \t\trc = ENOTSUP;\n \t\tgoto fail2;\ndiff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build\nindex 8909525c34..6ca5b57023 100644\n--- a/drivers/common/sfc_efx/base/meson.build\n+++ b/drivers/common/sfc_efx/base/meson.build\n@@ -51,7 +51,8 @@ sources = [\n \t'ef10_vpd.c',\n \t'hunt_nic.c',\n \t'medford_nic.c',\n-\t'medford2_nic.c'\n+\t'medford2_nic.c',\n+\t'rhead_nic.c',\n ]\n \n extra_flags = [\ndiff --git a/drivers/common/sfc_efx/base/rhead_impl.h b/drivers/common/sfc_efx/base/rhead_impl.h\nnew file mode 100644\nindex 0000000000..e25a871cb3\n--- /dev/null\n+++ b/drivers/common/sfc_efx/base/rhead_impl.h\n@@ -0,0 +1,105 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2018-2019 Solarflare Communications Inc.\n+ */\n+\n+#ifndef\t_SYS_RHEAD_IMPL_H\n+#define\t_SYS_RHEAD_IMPL_H\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+\n+#define\tRHEAD_EVQ_MAXNEVS\t16384\n+#define\tRHEAD_EVQ_MINNEVS\t256\n+\n+#define\tRHEAD_RXQ_MAXNDESCS\t16384\n+#define\tRHEAD_RXQ_MINNDESCS\t256\n+\n+#define\tRHEAD_TXQ_MAXNDESCS\t16384\n+#define\tRHEAD_TXQ_MINNDESCS\t256\n+\n+#define\tRHEAD_EVQ_DESC_SIZE\t(sizeof (efx_qword_t))\n+#define\tRHEAD_RXQ_DESC_SIZE\t(sizeof (efx_qword_t))\n+#define\tRHEAD_TXQ_DESC_SIZE\t(sizeof (efx_oword_t))\n+\n+\n+/* NIC */\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_board_cfg(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_probe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_set_drv_limits(\n+\t__inout\t\tefx_nic_t *enp,\n+\t__in\t\tefx_drv_limits_t *edlp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_get_vi_pool(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *vi_countp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_get_bar_region(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_nic_region_t region,\n+\t__out\t\tuint32_t *offsetp,\n+\t__out\t\tsize_t *sizep);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_reset(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tboolean_t\n+rhead_nic_hw_unavailable(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_nic_set_hw_unavailable(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#if EFSYS_OPT_DIAG\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_nic_register_test(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_nic_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_nic_unprobe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t/* _SYS_RHEAD_IMPL_H */\ndiff --git a/drivers/common/sfc_efx/base/rhead_nic.c b/drivers/common/sfc_efx/base/rhead_nic.c\nnew file mode 100644\nindex 0000000000..c83d18e6ab\n--- /dev/null\n+++ b/drivers/common/sfc_efx/base/rhead_nic.c\n@@ -0,0 +1,500 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2018-2019 Solarflare Communications Inc.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\n+#if EFSYS_OPT_RIVERHEAD\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_board_cfg(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tuint32_t end_padding;\n+\tuint32_t bandwidth;\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\tencp->enc_clk_mult = 1; /* not used for Riverhead */\n+\n+\t/*\n+\t * FIXME There are TxSend and TxSeg descriptors on Riverhead.\n+\t * TxSeg is bigger than TxSend.\n+\t */\n+\tencp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_GZ_TX_SEND_LEN);\n+\t/* No boundary crossing limits */\n+\tencp->enc_tx_dma_desc_boundary = 0;\n+\n+\t/*\n+\t * Maximum number of bytes into the frame the TCP header can start for\n+\t * firmware assisted TSO to work.\n+\t * FIXME Get from design parameter DP_TSO_MAX_HDR_LEN.\n+\t */\n+\tencp->enc_tx_tso_tcp_header_offset_limit = 0;\n+\n+\t/*\n+\t * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use\n+\t * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available\n+\t * resources (allocated to this PCIe function), which is zero until\n+\t * after we have allocated VIs.\n+\t */\n+\tencp->enc_evq_limit = 1024;\n+\tencp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;\n+\tencp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;\n+\n+\tencp->enc_buftbl_limit = UINT32_MAX;\n+\n+\t/*\n+\t * Enable firmware workarounds for hardware errata.\n+\t * Expected responses are:\n+\t * - 0 (zero):\n+\t *\tSuccess: workaround enabled or disabled as requested.\n+\t * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):\n+\t *\tFirmware does not support the MC_CMD_WORKAROUND request.\n+\t *\t(assume that the workaround is not supported).\n+\t * - MC_CMD_ERR_ENOENT (reported as ENOENT):\n+\t *\tFirmware does not support the requested workaround.\n+\t * - MC_CMD_ERR_EPERM (reported as EACCES):\n+\t *\tUnprivileged function cannot enable/disable workarounds.\n+\t *\n+\t * See efx_mcdi_request_errcode() for MCDI error translations.\n+\t */\n+\n+\t/*\n+\t * Replay engine on Riverhead should suppress duplicate packets\n+\t * (e.g. because of exact multicast and all-multicast filters\n+\t * match) to the same RxQ.\n+\t */\n+\tencp->enc_bug26807_workaround = B_FALSE;\n+\n+\t/*\n+\t * Checksums for TSO sends should always be correct on Riverhead.\n+\t * FIXME: revisit when TSO support is implemented.\n+\t */\n+\tencp->enc_bug61297_workaround = B_FALSE;\n+\n+\tencp->enc_evq_max_nevs = RHEAD_EVQ_MAXNEVS;\n+\tencp->enc_evq_min_nevs = RHEAD_EVQ_MINNEVS;\n+\tencp->enc_rxq_max_ndescs = RHEAD_RXQ_MAXNDESCS;\n+\tencp->enc_rxq_min_ndescs = RHEAD_RXQ_MINNDESCS;\n+\tencp->enc_txq_max_ndescs = RHEAD_TXQ_MAXNDESCS;\n+\tencp->enc_txq_min_ndescs = RHEAD_TXQ_MINNDESCS;\n+\n+\t/* Riverhead FW does not support event queue timers yet. */\n+\tencp->enc_evq_timer_quantum_ns = 0;\n+\tencp->enc_evq_timer_max_us = 0;\n+\n+\tencp->enc_ev_desc_size = RHEAD_EVQ_DESC_SIZE;\n+\tencp->enc_rx_desc_size = RHEAD_RXQ_DESC_SIZE;\n+\tencp->enc_tx_desc_size = RHEAD_TXQ_DESC_SIZE;\n+\n+\t/* No required alignment for WPTR updates */\n+\tencp->enc_rx_push_align = 1;\n+\n+\t/* Riverhead supports a single Rx prefix size. */\n+\tencp->enc_rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN;\n+\n+\t/* Alignment for receive packet DMA buffers. */\n+\tencp->enc_rx_buf_align_start = 1;\n+\n+\t/* Get the RX DMA end padding alignment configuration. */\n+\tif ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {\n+\t\tif (rc != EACCES)\n+\t\t\tgoto fail2;\n+\n+\t\t/* Assume largest tail padding size supported by hardware. */\n+\t\tend_padding = 128;\n+\t}\n+\tencp->enc_rx_buf_align_end = end_padding;\n+\n+\t/*\n+\t * Riverhead stores a single global copy of VPD, not per-PF as on\n+\t * Huntington.\n+\t */\n+\tencp->enc_vpd_is_global = B_TRUE;\n+\n+\trc = ef10_nic_get_port_mode_bandwidth(enp, &bandwidth);\n+\tif (rc != 0)\n+\t\tgoto fail3;\n+\tencp->enc_required_pcie_bandwidth_mbps = bandwidth;\n+\tencp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_probe(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tefx_drv_cfg_t *edcp = &(enp->en_drv_cfg);\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));\n+\n+\t/* Read and clear any assertion state */\n+\tif ((rc = efx_mcdi_read_assertion(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\t/* Exit the assertion handler */\n+\tif ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)\n+\t\tif (rc != EACCES)\n+\t\t\tgoto fail2;\n+\n+\tif ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)\n+\t\tgoto fail3;\n+\n+\t/* Get remaining controller-specific board config */\n+\tif ((rc = enop->eno_board_cfg(enp)) != 0)\n+\t\tgoto fail4;\n+\n+\t/*\n+\t * Set default driver config limits (based on board config).\n+\t *\n+\t * FIXME: For now allocate a fixed number of VIs which is likely to be\n+\t * sufficient and small enough to allow multiple functions on the same\n+\t * port.\n+\t */\n+\tedcp->edc_min_vi_count = edcp->edc_max_vi_count =\n+\t MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));\n+\n+\t/*\n+\t * The client driver must configure and enable PIO buffer support,\n+\t * but there is no PIO support on Riverhead anyway.\n+\t */\n+\tedcp->edc_max_piobuf_count = 0;\n+\tedcp->edc_pio_alloc_size = 0;\n+\n+#if EFSYS_OPT_MAC_STATS\n+\t/* Wipe the MAC statistics */\n+\tif ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)\n+\t\tgoto fail5;\n+#endif\n+\n+#if EFSYS_OPT_LOOPBACK\n+\tif ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)\n+\t\tgoto fail6;\n+#endif\n+\n+\treturn (0);\n+\n+#if EFSYS_OPT_LOOPBACK\n+fail6:\n+\tEFSYS_PROBE(fail6);\n+#endif\n+#if EFSYS_OPT_MAC_STATS\n+fail5:\n+\tEFSYS_PROBE(fail5);\n+#endif\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_set_drv_limits(\n+\t__inout\t\tefx_nic_t *enp,\n+\t__in\t\tefx_drv_limits_t *edlp)\n+{\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n+\tefx_drv_cfg_t *edcp = &(enp->en_drv_cfg);\n+\tuint32_t min_evq_count, max_evq_count;\n+\tuint32_t min_rxq_count, max_rxq_count;\n+\tuint32_t min_txq_count, max_txq_count;\n+\tefx_rc_t rc;\n+\n+\tif (edlp == NULL) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\t/* Get minimum required and maximum usable VI limits */\n+\tmin_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);\n+\tmin_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);\n+\tmin_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);\n+\n+\tedcp->edc_min_vi_count =\n+\t MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));\n+\n+\tmax_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);\n+\tmax_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);\n+\tmax_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);\n+\n+\tedcp->edc_max_vi_count =\n+\t MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));\n+\n+\t/* There is no PIO support on Riverhead */\n+\tedcp->edc_max_piobuf_count = 0;\n+\tedcp->edc_pio_alloc_size = 0;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_reset(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_rc_t rc;\n+\n+\t/* ef10_nic_reset() is called to recover from BADASSERT failures. */\n+\tif ((rc = efx_mcdi_read_assertion(enp)) != 0)\n+\t\tgoto fail1;\n+\tif ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\tif ((rc = efx_mcdi_entity_reset(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\t/* Clear RX/TX DMA queue errors */\n+\tenp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);\n+\tuint32_t min_vi_count, max_vi_count;\n+\tuint32_t vi_count, vi_base, vi_shift;\n+\tuint32_t vi_window_size;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));\n+\tEFSYS_ASSERT3U(edcp->edc_max_piobuf_count, ==, 0);\n+\n+\t/* Enable reporting of some events (e.g. link change) */\n+\tif ((rc = efx_mcdi_log_ctrl(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\tmin_vi_count = edcp->edc_min_vi_count;\n+\tmax_vi_count = edcp->edc_max_vi_count;\n+\n+\t/* Ensure that the previously attached driver's VIs are freed */\n+\tif ((rc = efx_mcdi_free_vis(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\t/*\n+\t * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this\n+\t * fails then retrying the request for fewer VI resources may succeed.\n+\t */\n+\tvi_count = 0;\n+\tif ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,\n+\t\t &vi_base, &vi_count, &vi_shift)) != 0)\n+\t\tgoto fail3;\n+\n+\tEFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);\n+\n+\tif (vi_count < min_vi_count) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail4;\n+\t}\n+\n+\tenp->en_arch.ef10.ena_vi_base = vi_base;\n+\tenp->en_arch.ef10.ena_vi_count = vi_count;\n+\tenp->en_arch.ef10.ena_vi_shift = vi_shift;\n+\n+\tEFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,\n+\t EFX_VI_WINDOW_SHIFT_INVALID);\n+\tEFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,\n+\t EFX_VI_WINDOW_SHIFT_64K);\n+\tvi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;\n+\n+\t/* Save UC memory mapping details */\n+\tenp->en_arch.ef10.ena_uc_mem_map_offset = 0;\n+\tenp->en_arch.ef10.ena_uc_mem_map_size =\n+\t vi_window_size * enp->en_arch.ef10.ena_vi_count;\n+\n+\t/* No WC memory mapping since PIO is not supported */\n+\tenp->en_arch.ef10.ena_pio_write_vi_base = 0;\n+\tenp->en_arch.ef10.ena_wc_mem_map_offset = 0;\n+\tenp->en_arch.ef10.ena_wc_mem_map_size = 0;\n+\n+\tenp->en_vport_id = EVB_PORT_ID_NULL;\n+\n+\tenp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;\n+\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+\n+\t(void) efx_mcdi_free_vis(enp);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_get_vi_pool(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *vi_countp)\n+{\n+\t/*\n+\t * Report VIs that the client driver can use.\n+\t * Do not include VIs used for PIO buffer writes.\n+\t */\n+\t*vi_countp = enp->en_arch.ef10.ena_vi_count;\n+\n+\treturn (0);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_get_bar_region(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_nic_region_t region,\n+\t__out\t\tuint32_t *offsetp,\n+\t__out\t\tsize_t *sizep)\n+{\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));\n+\n+\t/*\n+\t * TODO: Specify host memory mapping alignment and granularity\n+\t * in efx_drv_limits_t so that they can be taken into account\n+\t * when allocating extra VIs for PIO writes.\n+\t */\n+\tswitch (region) {\n+\tcase EFX_REGION_VI:\n+\t\t/* UC mapped memory BAR region for VI registers */\n+\t\t*offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;\n+\t\t*sizep = enp->en_arch.ef10.ena_uc_mem_map_size;\n+\t\tbreak;\n+\n+\tcase EFX_REGION_PIO_WRITE_VI:\n+\t\t/* WC mapped memory BAR region for piobuf writes */\n+\t\t*offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;\n+\t\t*sizep = enp->en_arch.ef10.ena_wc_mem_map_size;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tboolean_t\n+rhead_nic_hw_unavailable(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_dword_t dword;\n+\n+\tif (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)\n+\t\treturn (B_TRUE);\n+\n+\tEFX_BAR_READD(enp, ER_GZ_MC_SFT_STATUS, &dword, B_FALSE);\n+\tif (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)\n+\t\tgoto unavail;\n+\n+\treturn (B_FALSE);\n+\n+unavail:\n+\trhead_nic_set_hw_unavailable(enp);\n+\n+\treturn (B_TRUE);\n+}\n+\n+\t\t\tvoid\n+rhead_nic_set_hw_unavailable(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tEFSYS_PROBE(hw_unavail);\n+\tenp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;\n+}\n+\n+\t\t\tvoid\n+rhead_nic_fini(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\t(void) efx_mcdi_free_vis(enp);\n+\tenp->en_arch.ef10.ena_vi_count = 0;\n+}\n+\n+\t\t\tvoid\n+rhead_nic_unprobe(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\t(void) efx_mcdi_drv_attach(enp, B_FALSE);\n+}\n+\n+#if EFSYS_OPT_DIAG\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_nic_register_test(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_rc_t rc;\n+\n+\t/* FIXME */\n+\t_NOTE(ARGUNUSED(enp))\n+\t_NOTE(CONSTANTCONDITION)\n+\tif (B_FALSE) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\t/* FIXME */\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n+#endif\t/* EFSYS_OPT_RIVERHEAD */\n", "prefixes": [ "14/60" ] }