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GET /api/patches/78265/?format=api
{ "id": 78265, "url": "http://patches.dpdk.org/api/patches/78265/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-23-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600764594-14752-23-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600764594-14752-23-git-send-email-arybchenko@solarflare.com", "date": "2020-09-22T08:49:16", "name": "[22/60] common/sfc_efx/base: merge versions of init EvQ wrappers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "759754e2287e22d17c9b9ca20ec79c2b7b5f4da0", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1600764594-14752-23-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12400, "url": "http://patches.dpdk.org/api/series/12400/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12400", "date": "2020-09-22T08:48:59", "name": "common/sfc_efx: support Riverhead NIC family", "version": 1, "mbox": "http://patches.dpdk.org/series/12400/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/78265/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/78265/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A3045A04E1;\n\tTue, 22 Sep 2020 10:52:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8E90C1DAD4;\n\tTue, 22 Sep 2020 10:50:45 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 0E4961D70C\n for <dev@dpdk.org>; Tue, 22 Sep 2020 10:50:18 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.150])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n ADBA520055 for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from us4-mdac16-60.at1.mdlocal (unknown [10.110.50.153])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id AD225800A3\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.110.50.8])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 3ABFD100052\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 036914C0059\n for <dev@dpdk.org>; Tue, 22 Sep 2020 08:50:17 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 22 Sep 2020 09:50:10 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 22 Sep 2020 09:50:10 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08M8oAgK004674\n for <dev@dpdk.org>; Tue, 22 Sep 2020 09:50:10 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 28F931613A9\n for <dev@dpdk.org>; Tue, 22 Sep 2020 09:50:10 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Tue, 22 Sep 2020 09:49:16 +0100", "Message-ID": "<1600764594-14752-23-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-9.884500-8.000000-10", "X-TMASE-MatchedRID": "mxPm4/rFDPQ40FQTvb+HBi8s/ULwMh463V4UShoTXadtw+n+iKWyyEeO\n 32NJTaee5KHYnTLjqLl8d8ZLFoVsqNpsFVyqUNwXbBMSu4v05tM/pOSL72dTfwdkFovAReUoLPJ\n tWpbJjY34tChzbbBKvF+bnK6VdutFKerAqZTShjM+NrfDUTEXxPG6GRFYrbYYQW6eCaGxKwKOJ3\n eQSEJmKs4M0wnt7LoDssHw+J0qGMkop8ZOkjgdUXL1TJ3FgoWZ1JP9NndNOkWEWB8iuyGqCfLwF\n Hrs2PUr1OYlw6XumHi35qHKWj7a5i7J3GddaS//HC7hAz/oKnJcaNB/u5yQqx53XUX0iwoUwv9A\n ibJlKnD5st7EvPbtNXqZ7YfJvYp/z5ey3IkHnU7bbgI4AuYpVzQAl7cHmp8GwzktBYXAF0rbWkH\n MATUzun2dcFgFzv71EtRm78gcrDGSsyjfsjrH/os/uwyVPuwc9/x+2nQH35JXiLrvhpKLfJ8eTN\n fYszv08a9FfTFXt2nHEfUJ5TpSVhID8IiUPlK/ngIgpj8eDcAZ1CdBJOsoY8RB0bsfrpPIqxB32\n o9eGck2pvMU9bFHY2Qz0gWJZun4JUAZABQE7mkYTBdVS3PYE7BLMjppLAcuVlxr1FJij9s=", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--9.884500-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600764617-B5gq6UzXnrCh", "Subject": "[dpdk-dev] [PATCH 22/60] common/sfc_efx/base: merge versions of\n\tinit EvQ wrappers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The decision on which version of the INIT_EVQ command to use may\nbe done inside the function itself. Caller should just provide\nenough information sufficient in both cases. It avoids code\nduplication and simplifies maintenance.\n\nIf v2 is not supported, keep decision about low-latency hint outside\nthe MCDI helper function since it will differ on Riverhead (there is\nno EVB yet, but still want merging for better throughput).\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/ef10_ev.c | 54 +++---\n drivers/common/sfc_efx/base/efx_impl.h | 11 --\n drivers/common/sfc_efx/base/efx_mcdi.c | 228 ++++++++-----------------\n 3 files changed, 95 insertions(+), 198 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/ef10_ev.c b/drivers/common/sfc_efx/base/ef10_ev.c\nindex 18f19e816d..e2b5c62d5d 100644\n--- a/drivers/common/sfc_efx/base/ef10_ev.c\n+++ b/drivers/common/sfc_efx/base/ef10_ev.c\n@@ -130,6 +130,7 @@ ef10_ev_qcreate(\n \tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n \tuint32_t irq;\n \tefx_rc_t rc;\n+\tboolean_t low_latency;\n \n \t_NOTE(ARGUNUSED(id))\t/* buftbl id managed by MC */\n \n@@ -175,42 +176,29 @@ ef10_ev_qcreate(\n \t * created. See bug58606.\n \t */\n \n-\tif (encp->enc_init_evq_v2_supported) {\n-\t\t/*\n-\t\t * On Medford the low latency license is required to enable RX\n-\t\t * and event cut through and to disable RX batching. If event\n-\t\t * queue type in flags is auto, we let the firmware decide the\n-\t\t * settings to use. If the adapter has a low latency license,\n-\t\t * it will choose the best settings for low latency, otherwise\n-\t\t * it will choose the best settings for throughput.\n-\t\t */\n-\t\trc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,\n-\t\t flags);\n-\t\tif (rc != 0)\n-\t\t\tgoto fail2;\n-\t} else {\n-\t\t/*\n-\t\t * On Huntington we need to specify the settings to use.\n-\t\t * If event queue type in flags is auto, we favour throughput\n-\t\t * if the adapter is running virtualization supporting firmware\n-\t\t * (i.e. the full featured firmware variant)\n-\t\t * and latency otherwise. The Ethernet Virtual Bridging\n-\t\t * capability is used to make this decision. (Note though that\n-\t\t * the low latency firmware variant is also best for\n-\t\t * throughput and corresponding type should be specified\n-\t\t * to choose it.)\n-\t\t */\n-\t\tboolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;\n-\t\trc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,\n-\t\t low_latency);\n-\t\tif (rc != 0)\n-\t\t\tgoto fail3;\n-\t}\n+\t/*\n+\t * On Huntington we need to specify the settings to use.\n+\t * If event queue type in flags is auto, we favour throughput\n+\t * if the adapter is running virtualization supporting firmware\n+\t * (i.e. the full featured firmware variant)\n+\t * and latency otherwise. The Ethernet Virtual Bridging\n+\t * capability is used to make this decision. (Note though that\n+\t * the low latency firmware variant is also best for\n+\t * throughput and corresponding type should be specified\n+\t * to choose it.)\n+\t *\n+\t * If FW supports EvQ types (e.g. on Medford and Medford2) the\n+\t * type which is specified in flags is passed to FW to make the\n+\t * decision and low_latency hint is ignored.\n+\t */\n+\tlow_latency = encp->enc_datapath_cap_evb ? 0 : 1;\n+\trc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,\n+\t low_latency);\n+\tif (rc != 0)\n+\t\tgoto fail2;\n \n \treturn (0);\n \n-fail3:\n-\tEFSYS_PROBE(fail3);\n fail2:\n \tEFSYS_PROBE(fail2);\n fail1:\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex bf1cfc49ca..47e4dcb01f 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -1422,17 +1422,6 @@ efx_mcdi_init_evq(\n \t__in\t\tuint32_t flags,\n \t__in\t\tboolean_t low_latency);\n \n-LIBEFX_INTERNAL\n-extern\t__checkReturn\tefx_rc_t\n-efx_mcdi_init_evq_v2(\n-\t__in\t\tefx_nic_t *enp,\n-\t__in\t\tunsigned int instance,\n-\t__in\t\tefsys_mem_t *esmp,\n-\t__in\t\tsize_t nevs,\n-\t__in\t\tuint32_t irq,\n-\t__in\t\tuint32_t us,\n-\t__in\t\tuint32_t flags);\n-\n LIBEFX_INTERNAL\n extern\t__checkReturn\tefx_rc_t\n efx_mcdi_fini_evq(\ndiff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c\nindex 50d723ecb4..69d2327839 100644\n--- a/drivers/common/sfc_efx/base/efx_mcdi.c\n+++ b/drivers/common/sfc_efx/base/efx_mcdi.c\n@@ -2456,146 +2456,14 @@ efx_mcdi_init_evq(\n \t__in\t\tuint32_t flags,\n \t__in\t\tboolean_t low_latency)\n {\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n \tefx_mcdi_req_t req;\n \tEFX_MCDI_DECLARE_BUF(payload,\n \t\tMC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),\n \t\tMC_CMD_INIT_EVQ_V2_OUT_LEN);\n-\tefx_qword_t *dma_addr;\n-\tuint64_t addr;\n-\tint npages;\n-\tint i;\n \tboolean_t interrupting;\n \tint ev_cut_through;\n-\tefx_rc_t rc;\n-\n-\tnpages = efx_evq_nbufs(enp, nevs);\n-\tif (npages > EF10_EVQ_MAXNBUFS) {\n-\t\trc = EINVAL;\n-\t\tgoto fail1;\n-\t}\n-\n-\treq.emr_cmd = MC_CMD_INIT_EVQ;\n-\treq.emr_in_buf = payload;\n-\treq.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);\n-\treq.emr_out_buf = payload;\n-\treq.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;\n-\n-\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);\n-\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);\n-\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);\n-\n-\tinterrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==\n-\t EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);\n-\n-\t/*\n-\t * On Huntington RX and TX event batching can only be requested together\n-\t * (even if the datapath firmware doesn't actually support RX\n-\t * batching). If event cut through is enabled no RX batching will occur.\n-\t *\n-\t * So always enable RX and TX event batching, and enable event cut\n-\t * through if we want low latency operation.\n-\t */\n-\tswitch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {\n-\tcase EFX_EVQ_FLAGS_TYPE_AUTO:\n-\t\tev_cut_through = low_latency ? 1 : 0;\n-\t\tbreak;\n-\tcase EFX_EVQ_FLAGS_TYPE_THROUGHPUT:\n-\t\tev_cut_through = 0;\n-\t\tbreak;\n-\tcase EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:\n-\t\tev_cut_through = 1;\n-\t\tbreak;\n-\tdefault:\n-\t\trc = EINVAL;\n-\t\tgoto fail2;\n-\t}\n-\tMCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_V2_IN_FLAGS,\n-\t INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,\n-\t INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,\n-\t INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,\n-\t INIT_EVQ_V2_IN_FLAG_CUT_THRU, ev_cut_through,\n-\t INIT_EVQ_V2_IN_FLAG_RX_MERGE, 1,\n-\t INIT_EVQ_V2_IN_FLAG_TX_MERGE, 1);\n-\n-\t/* If the value is zero then disable the timer */\n-\tif (us == 0) {\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,\n-\t\t MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);\n-\t} else {\n-\t\tunsigned int ticks;\n-\n-\t\tif ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)\n-\t\t\tgoto fail3;\n-\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,\n-\t\t MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);\n-\t\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);\n-\t}\n-\n-\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,\n-\t MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);\n-\tMCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);\n-\n-\tdma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);\n-\taddr = EFSYS_MEM_ADDR(esmp);\n-\n-\tfor (i = 0; i < npages; i++) {\n-\t\tEFX_POPULATE_QWORD_2(*dma_addr,\n-\t\t EFX_DWORD_1, (uint32_t)(addr >> 32),\n-\t\t EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));\n-\n-\t\tdma_addr++;\n-\t\taddr += EFX_BUF_SIZE;\n-\t}\n-\n-\tefx_mcdi_execute(enp, &req);\n-\n-\tif (req.emr_rc != 0) {\n-\t\trc = req.emr_rc;\n-\t\tgoto fail4;\n-\t}\n-\n-\tif (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {\n-\t\trc = EMSGSIZE;\n-\t\tgoto fail5;\n-\t}\n-\n-\t/* NOTE: ignore the returned IRQ param as firmware does not set it. */\n-\n-\treturn (0);\n-\n-fail5:\n-\tEFSYS_PROBE(fail5);\n-fail4:\n-\tEFSYS_PROBE(fail4);\n-fail3:\n-\tEFSYS_PROBE(fail3);\n-fail2:\n-\tEFSYS_PROBE(fail2);\n-fail1:\n-\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n-\n-\treturn (rc);\n-}\n-\n-\t__checkReturn\tefx_rc_t\n-efx_mcdi_init_evq_v2(\n-\t__in\t\tefx_nic_t *enp,\n-\t__in\t\tunsigned int instance,\n-\t__in\t\tefsys_mem_t *esmp,\n-\t__in\t\tsize_t nevs,\n-\t__in\t\tuint32_t irq,\n-\t__in\t\tuint32_t us,\n-\t__in\t\tuint32_t flags)\n-{\n-\tefx_mcdi_req_t req;\n-\tEFX_MCDI_DECLARE_BUF(payload,\n-\t\tMC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),\n-\t\tMC_CMD_INIT_EVQ_V2_OUT_LEN);\n-\tboolean_t interrupting;\n+\tint ev_merge;\n \tunsigned int evq_type;\n \tefx_qword_t *dma_addr;\n \tuint64_t addr;\n@@ -2622,24 +2490,68 @@ efx_mcdi_init_evq_v2(\n \tinterrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==\n \t EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);\n \n-\tswitch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {\n-\tcase EFX_EVQ_FLAGS_TYPE_AUTO:\n-\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;\n-\t\tbreak;\n-\tcase EFX_EVQ_FLAGS_TYPE_THROUGHPUT:\n-\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;\n-\t\tbreak;\n-\tcase EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:\n-\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;\n-\t\tbreak;\n-\tdefault:\n-\t\trc = EINVAL;\n-\t\tgoto fail2;\n+\tif (encp->enc_init_evq_v2_supported) {\n+\t\t/*\n+\t\t * On Medford the low latency license is required to enable RX\n+\t\t * and event cut through and to disable RX batching. If event\n+\t\t * queue type in flags is auto, we let the firmware decide the\n+\t\t * settings to use. If the adapter has a low latency license,\n+\t\t * it will choose the best settings for low latency, otherwise\n+\t\t * it will choose the best settings for throughput.\n+\t\t */\n+\t\tswitch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {\n+\t\tcase EFX_EVQ_FLAGS_TYPE_AUTO:\n+\t\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;\n+\t\t\tbreak;\n+\t\tcase EFX_EVQ_FLAGS_TYPE_THROUGHPUT:\n+\t\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;\n+\t\t\tbreak;\n+\t\tcase EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:\n+\t\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trc = EINVAL;\n+\t\t\tgoto fail2;\n+\t\t}\n+\t\t/* EvQ type controls merging, no manual settings */\n+\t\tev_merge = 0;\n+\t\tev_cut_through = 0;\n+\t} else {\n+\t\t/* EvQ types other than manual are not supported */\n+\t\tevq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL;\n+\t\t/*\n+\t\t * On Huntington RX and TX event batching can only be requested\n+\t\t * together (even if the datapath firmware doesn't actually\n+\t\t * support RX batching). If event cut through is enabled no RX\n+\t\t * batching will occur.\n+\t\t *\n+\t\t * So always enable RX and TX event batching, and enable event\n+\t\t * cut through if we want low latency operation.\n+\t\t */\n+\t\tev_merge = 1;\n+\t\tswitch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {\n+\t\tcase EFX_EVQ_FLAGS_TYPE_AUTO:\n+\t\t\tev_cut_through = low_latency ? 1 : 0;\n+\t\t\tbreak;\n+\t\tcase EFX_EVQ_FLAGS_TYPE_THROUGHPUT:\n+\t\t\tev_cut_through = 0;\n+\t\t\tbreak;\n+\t\tcase EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:\n+\t\t\tev_cut_through = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trc = EINVAL;\n+\t\t\tgoto fail2;\n+\t\t}\n \t}\n-\tMCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,\n+\n+\tMCDI_IN_POPULATE_DWORD_7(req, INIT_EVQ_V2_IN_FLAGS,\n \t INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,\n \t INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,\n \t INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,\n+\t INIT_EVQ_V2_IN_FLAG_CUT_THRU, ev_cut_through,\n+\t INIT_EVQ_V2_IN_FLAG_RX_MERGE, ev_merge,\n+\t INIT_EVQ_V2_IN_FLAG_TX_MERGE, ev_merge,\n \t INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);\n \n \t/* If the value is zero then disable the timer */\n@@ -2683,18 +2595,26 @@ efx_mcdi_init_evq_v2(\n \t\tgoto fail4;\n \t}\n \n-\tif (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {\n-\t\trc = EMSGSIZE;\n-\t\tgoto fail5;\n+\tif (encp->enc_init_evq_v2_supported) {\n+\t\tif (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {\n+\t\t\trc = EMSGSIZE;\n+\t\t\tgoto fail5;\n+\t\t}\n+\t\tEFSYS_PROBE1(mcdi_evq_flags, uint32_t,\n+\t\t\t MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));\n+\t} else {\n+\t\tif (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {\n+\t\t\trc = EMSGSIZE;\n+\t\t\tgoto fail6;\n+\t\t}\n \t}\n \n \t/* NOTE: ignore the returned IRQ param as firmware does not set it. */\n \n-\tEFSYS_PROBE1(mcdi_evq_flags, uint32_t,\n-\t\t MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));\n-\n \treturn (0);\n \n+fail6:\n+\tEFSYS_PROBE(fail6);\n fail5:\n \tEFSYS_PROBE(fail5);\n fail4:\n", "prefixes": [ "22/60" ] }