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GET /api/patches/77636/?format=api
{ "id": 77636, "url": "http://patches.dpdk.org/api/patches/77636/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200914161801.572174-4-thomas@monjalon.net/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200914161801.572174-4-thomas@monjalon.net>", "list_archive_url": "https://inbox.dpdk.org/dev/20200914161801.572174-4-thomas@monjalon.net", "date": "2020-09-14T16:17:59", "name": "[3/4] mbuf: remove deprecated function and macro aliases", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5066e7ba0baad5d0720d62a9bbf425b93c3d819b", "submitter": { "id": 685, "url": "http://patches.dpdk.org/api/people/685/?format=api", "name": "Thomas Monjalon", "email": "thomas@monjalon.net" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200914161801.572174-4-thomas@monjalon.net/mbox/", "series": [ { "id": 12203, "url": "http://patches.dpdk.org/api/series/12203/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12203", "date": "2020-09-14T16:17:56", "name": "remove aliases replaced with IOVA", "version": 1, "mbox": "http://patches.dpdk.org/series/12203/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77636/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77636/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 691A5A04C7;\n\tMon, 14 Sep 2020 18:18:41 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2C6141C0CE;\n\tMon, 14 Sep 2020 18:18:28 +0200 (CEST)", "from new3-smtp.messagingengine.com (new3-smtp.messagingengine.com\n [66.111.4.229]) by dpdk.org (Postfix) with ESMTP id 5E2841BFC4\n for <dev@dpdk.org>; Mon, 14 Sep 2020 18:18:26 +0200 (CEST)", "from compute7.internal (compute7.nyi.internal [10.202.2.47])\n by mailnew.nyi.internal (Postfix) with ESMTP id C2E4C580218;\n Mon, 14 Sep 2020 12:18:25 -0400 (EDT)", "from mailfrontend1 ([10.202.2.162])\n by compute7.internal (MEProxy); Mon, 14 Sep 2020 12:18:25 -0400", "from xps.monjalon.net (184.203.134.77.rev.sfr.net [77.134.203.184])\n by mail.messagingengine.com (Postfix) with ESMTPA id 044D4328005A;\n Mon, 14 Sep 2020 12:18:22 -0400 (EDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding; s=fm2; bh=FCQTk3WhhWy0e\n tO3MLaMSLvd9MXL7hyJZNcew3PBJAA=; b=J+nnFaA9fxq0KduEd4d21vOmPFp/D\n 0EyZ3ibo8XmccG+UhiGIAX/Nqv/L2H1TbBH6TcVsBkKCr/u0Jfv1Bg/Ve0zn3tSa\n agAweWWvkSlgRleQHoUkuZkj6Dj7ywVy/gLIIS7/OLYKMIMdcUKQjgr9uruyEGcT\n 6063p1WL70NV4cLFrBmDo+qOFmV6UjR9FP8qaxUrX393OBbZn84sXefKy5A6Ob7J\n w6Nccfk2IRwaap1gTmtoW47KxwTVRXbD1iHQA/vay1OO/ZUD42+AlpZ10Ha0Z4bN\n ZrFEhff23pFxi2HiG8Ke9ZtyEJhIj85Mey/IUtYQ5qs984sDcy1m6h7Fw==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n messagingengine.com; h=cc:content-transfer-encoding:date:from\n :in-reply-to:message-id:mime-version:references:subject:to\n :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=\n fm3; bh=FCQTk3WhhWy0etO3MLaMSLvd9MXL7hyJZNcew3PBJAA=; b=fq6948nN\n VsdlvEoZLruw5bfKkHJmH9oTEeE5oZn5ZgmQXLkTAZrmHSBM0uoAHz02iG5mKCZq\n cr2dWF/fT3ekMH2F5DVoQ4xRsaHE8bUmm70NRXziY8/NgZCPjDo2gUX2NPQYow8e\n h7HTKFyekAv+Vk3jd/65rTflKIN8dSwFPp+VCGNgQSaT1Vv69+p6FxVj9VcHpBxe\n naXR8lDhJVoNWehQUr5hsR/V2kVWs24+hjwqNHBwHnzgansEP//axfMX/IYNJLvv\n I0cXNC5VxC+ab0TtULkF/nf9RF/bhBoLx/sztcjH4njsorUWYiGLWDcvfsfQUQq+\n BrO6mSoo+eb1eg==" ], "X-ME-Sender": "<xms:0ZdfX2pQTuhA_hWsjtInjxncB6mS9FPChLsXQBINHiac0nTlsqGmmA>\n <xme:0ZdfX0qVRZsqYGHGlFpN-AZ4hYQmAZfQR1jycCicGEvSTYuQxPRqwmKmw7sKIHHej\n R1QQjSthrabMZIM5g>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgeduiedrudeiiedguddtudcutefuodetggdotefrod\n ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh\n necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd\n enucfjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepvfhhohhm\n rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc\n ggtffrrghtthgvrhhnpedukeduhfffjeevjedvhfdvgffhtdevveefheffjeelfedvhedv\n teehjeduhffgueenucffohhmrghinhepughighgvshhtrdgurghtrgenucfkphepjeejrd\n dufeegrddvtdefrddukeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehm\n rghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth", "X-ME-Proxy": "<xmx:0ZdfX7NkWWSAHEVEcBqyabkWuUpyZct6rBHRYrgqp2oCZDlavIRRMA>\n <xmx:0ZdfX14ecF4sX9KI_tn2pFmZymlVxUDRuKoN_kClR8IBMXWcniHong>\n <xmx:0ZdfX14m8a_sXmcWnWIAngQj_bROd_qO7b4QeiOVte8sWQeT2U7_gg>\n <xmx:0ZdfX-Tonciq1NCHqVWnd-7Sn_7DgchGHqnkwdkNivWC0qsDyof5yA>", "From": "Thomas Monjalon <thomas@monjalon.net>", "To": "dev@dpdk.org", "Cc": "mdr@ashroe.eu, david.marchand@redhat.com,\n Nicolas Chautru <nicolas.chautru@intel.com>,\n Anoob Joseph <anoobj@marvell.com>, Fiona Trahe <fiona.trahe@intel.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Somalapuram Amaranath <asomalap@amd.com>,\n Akhil Goyal <akhil.goyal@nxp.com>, Hemant Agrawal <hemant.agrawal@nxp.com>,\n Nagadheeraj Rottela <rnagadheeraj@marvell.com>,\n Srikanth Jampala <jsrikanth@marvell.com>,\n Jay Zhou <jianjay.zhou@huawei.com>, Jerin Jacob <jerinj@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Marko Kovacevic <marko.kovacevic@intel.com>, Ori Kam <orika@mellanox.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Radu Nicolau <radu.nicolau@intel.com>,\n Tomasz Kantecki <tomasz.kantecki@intel.com>,\n Sunil Kumar Kori <skori@marvell.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Olivier Matz <olivier.matz@6wind.com>", "Date": "Mon, 14 Sep 2020 18:17:59 +0200", "Message-Id": "<20200914161801.572174-4-thomas@monjalon.net>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20200914161801.572174-1-thomas@monjalon.net>", "References": "<20200914161801.572174-1-thomas@monjalon.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 3/4] mbuf: remove deprecated function and macro\n\taliases", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove the deprecated functions\n\t- rte_mbuf_data_dma_addr\n\t- rte_mbuf_data_dma_addr_default\nwhich aliased the more recent functions\n\t- rte_mbuf_data_iova\n\t- rte_mbuf_data_iova_default\n\nRemove the deprecated macros\n\t- rte_pktmbuf_mtophys\n\t- rte_pktmbuf_mtophys_offset\nwhich aliased the more recent macros\n\t- rte_pktmbuf_iova\n\t- rte_pktmbuf_iova_offset\n\nSigned-off-by: Thomas Monjalon <thomas@monjalon.net>\n---\n .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 16 +++----\n drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 16 +++----\n drivers/common/cpt/cpt_ucode.h | 12 +++---\n drivers/compress/qat/qat_comp.c | 4 +-\n drivers/crypto/ccp/ccp_crypto.c | 22 +++++-----\n drivers/crypto/dpaa_sec/dpaa_sec.c | 42 +++++++++----------\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 6 +--\n drivers/crypto/virtio/virtio_rxtx.c | 6 +--\n drivers/net/axgbe/axgbe_rxtx.c | 4 +-\n drivers/net/octeontx2/otx2_ethdev_sec_tx.h | 2 +-\n examples/fips_validation/main.c | 4 +-\n lib/librte_mbuf/rte_mbuf.h | 21 ----------\n 12 files changed, 67 insertions(+), 88 deletions(-)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 930718cd47..61f9c04ba2 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -950,14 +950,14 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n \tdesc->num_null = op->ldpc_enc.n_filler;\n \t/* Set inbound data buffer address */\n \tdesc->in_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset));\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset));\n \n \tdesc->out_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset));\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset));\n \t/* Save software context needed for dequeue */\n \tdesc->op_addr = op;\n \t/* Set total number of CBs in an op */\n@@ -998,9 +998,9 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \tdesc->error = 0;\n \t/* Set inbound data buffer address */\n \tdesc->in_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset));\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset));\n \tdesc->rm_e = op->ldpc_dec.cb_params.e;\n \tdesc->harq_input_length = harq_in_length;\n \tdesc->et_dis = !check_bit(op->ldpc_dec.op_flags,\n@@ -1021,9 +1021,9 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \tdesc->max_iter = op->ldpc_dec.iter_max;\n \tdesc->qm_idx = op->ldpc_dec.q_m / 2;\n \tdesc->out_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset));\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset));\n \t/* Save software context needed for dequeue */\n \tdesc->op_addr = op;\n \t/* Set total number of CBs in an op */\ndiff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\nindex 6be9131e72..37018b9c7f 100644\n--- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\n+++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\n@@ -1251,14 +1251,14 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n \tdesc->offset = desc_offset;\n \t/* Set inbound data buffer address */\n \tdesc->in_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset));\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset));\n \n \tdesc->out_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset));\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset));\n \n \t/* Save software context needed for dequeue */\n \tdesc->op_addr = op;\n@@ -1302,9 +1302,9 @@ fpga_dma_desc_td_fill(struct rte_bbdev_dec_op *op,\n \tdesc->done = 0;\n \t/* Set inbound data buffer address */\n \tdesc->in_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset) >> 32);\n \tdesc->in_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(input, in_offset));\n+\t\t\trte_pktmbuf_iova_offset(input, in_offset));\n \tdesc->in_len = in_length;\n \tdesc->k = k;\n \tdesc->crc_type = !check_bit(op->turbo_dec.op_flags,\n@@ -1316,9 +1316,9 @@ fpga_dma_desc_td_fill(struct rte_bbdev_dec_op *op,\n \tdesc->max_iter = op->turbo_dec.iter_max * 2;\n \tdesc->offset = desc_offset;\n \tdesc->out_addr_hi = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset) >> 32);\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset) >> 32);\n \tdesc->out_addr_lw = (uint32_t)(\n-\t\t\trte_pktmbuf_mtophys_offset(output, out_offset));\n+\t\t\trte_pktmbuf_iova_offset(output, out_offset));\n \n \t/* Save software context needed for dequeue */\n \tdesc->op_addr = op;\ndiff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex 44067cf1b1..4e79fbf7a5 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -2918,7 +2918,7 @@ prepare_iov_from_pkt(struct rte_mbuf *pkt,\n \n \tif (!start_offset) {\n \t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n-\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_phys = rte_pktmbuf_iova(pkt);\n \t\tseg_size = pkt->data_len;\n \t} else {\n \t\twhile (start_offset >= pkt->data_len) {\n@@ -2927,7 +2927,7 @@ prepare_iov_from_pkt(struct rte_mbuf *pkt,\n \t\t}\n \n \t\tseg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);\n-\t\tseg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);\n+\t\tseg_phys = rte_pktmbuf_iova_offset(pkt, start_offset);\n \t\tseg_size = pkt->data_len - start_offset;\n \t\tif (!seg_size)\n \t\t\treturn 1;\n@@ -2942,7 +2942,7 @@ prepare_iov_from_pkt(struct rte_mbuf *pkt,\n \n \twhile (unlikely(pkt != NULL)) {\n \t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n-\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_phys = rte_pktmbuf_iova(pkt);\n \t\tseg_size = pkt->data_len;\n \t\tif (!seg_size)\n \t\t\tbreak;\n@@ -2972,7 +2972,7 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n \tiov_ptr_t *iovec;\n \n \tseg_data = rte_pktmbuf_mtod(pkt, void *);\n-\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\tseg_phys = rte_pktmbuf_iova(pkt);\n \tseg_size = pkt->data_len;\n \n \t/* first seg */\n@@ -3001,7 +3001,7 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n \n \twhile (unlikely(pkt != NULL)) {\n \t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n-\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_phys = rte_pktmbuf_iova(pkt);\n \t\tseg_size = pkt->data_len;\n \n \t\tif (!seg_size)\n@@ -3463,7 +3463,7 @@ fill_digest_params(struct rte_crypto_op *cop,\n \t\t\tparams.mac_buf.vaddr =\n \t\t\t\trte_pktmbuf_mtod_offset(m_dst, void *, off);\n \t\t\tparams.mac_buf.dma_addr =\n-\t\t\t\trte_pktmbuf_mtophys_offset(m_dst, off);\n+\t\t\t\trte_pktmbuf_iova_offset(m_dst, off);\n \t\t\tparams.mac_buf.size = mac_len;\n \t\t}\n \t} else {\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex 335fd63b98..3a064ec3b2 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -305,9 +305,9 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t\tcomp_req->comp_pars.out_buffer_sz;\n \n \t\tcomp_req->comn_mid.src_data_addr =\n-\t\t rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);\n+\t\t rte_pktmbuf_iova_offset(op->m_src, op->src.offset);\n \t\tcomp_req->comn_mid.dest_data_addr =\n-\t\t rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);\n+\t\t rte_pktmbuf_iova_offset(op->m_dst, op->dst.offset);\n \t}\n \n \tif (unlikely(rte_pktmbuf_pkt_len(op->m_dst) < QAT_MIN_OUT_BUF_SIZE)) {\ndiff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c\nindex 4256734d16..db3fb6eff8 100644\n--- a/drivers/crypto/ccp/ccp_crypto.c\n+++ b/drivers/crypto/ccp/ccp_crypto.c\n@@ -1571,7 +1571,7 @@ ccp_perform_hmac(struct rte_crypto_op *op,\n \t\t\t\t\t ccp_cryptodev_driver_id);\n \taddr = session->auth.pre_compute;\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n \tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n@@ -1743,7 +1743,7 @@ ccp_perform_sha(struct rte_crypto_op *op,\n \t\t\t\t\t op->sym->session,\n \t\t\t\t\tccp_cryptodev_driver_id);\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n \n \tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n@@ -1832,7 +1832,7 @@ ccp_perform_sha3_hmac(struct rte_crypto_op *op,\n \t\t\t\t\t op->sym->session,\n \t\t\t\t\tccp_cryptodev_driver_id);\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n \tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n@@ -1972,7 +1972,7 @@ ccp_perform_sha3(struct rte_crypto_op *op,\n \t\t\t\t\t op->sym->session,\n \t\t\t\t\tccp_cryptodev_driver_id);\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n \tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n@@ -2041,7 +2041,7 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op,\n \t\t\t\t\tccp_cryptodev_driver_id);\n \tkey_addr = rte_mem_virt2phy(session->auth.key_ccp);\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n \tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n@@ -2221,10 +2221,10 @@ ccp_perform_aes(struct rte_crypto_op *op,\n \n \tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->cipher.data.offset);\n \tif (likely(op->sym->m_dst != NULL))\n-\t\tdest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\tdest_addr = rte_pktmbuf_iova_offset(op->sym->m_dst,\n \t\t\t\t\t\top->sym->cipher.data.offset);\n \telse\n \t\tdest_addr = src_addr;\n@@ -2303,11 +2303,11 @@ ccp_perform_3des(struct rte_crypto_op *op,\n \t\treturn -ENOTSUP;\n \t}\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->cipher.data.offset);\n \tif (unlikely(op->sym->m_dst != NULL))\n \t\tdest_addr =\n-\t\t\trte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\t\trte_pktmbuf_iova_offset(op->sym->m_dst,\n \t\t\t\t\t\t op->sym->cipher.data.offset);\n \telse\n \t\tdest_addr = src_addr;\n@@ -2385,10 +2385,10 @@ ccp_perform_aes_gcm(struct rte_crypto_op *op, struct ccp_queue *cmd_q)\n \tiv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset);\n \tkey_addr = session->cipher.key_phys;\n \n-\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->aead.data.offset);\n \tif (unlikely(op->sym->m_dst != NULL))\n-\t\tdest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\tdest_addr = rte_pktmbuf_iova_offset(op->sym->m_dst,\n \t\t\t\t\t\top->sym->aead.data.offset);\n \telse\n \t\tdest_addr = src_addr;\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c\nindex c4339336de..97002170b0 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.c\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c\n@@ -748,7 +748,7 @@ build_auth_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \t\tsg++;\n \t}\n \n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->offset = data_offset;\n \n \tif (data_len <= (mbuf->data_len - data_offset)) {\n@@ -761,7 +761,7 @@ build_auth_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \t\t (mbuf = mbuf->next)) {\n \t\t\tcpu_to_hw_sg(sg);\n \t\t\tsg++;\n-\t\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\t\tif (data_len > mbuf->data_len)\n \t\t\t\tsg->length = mbuf->data_len;\n \t\t\telse\n@@ -866,7 +866,7 @@ build_auth_only(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \t\tsg++;\n \t}\n \n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->offset = data_offset;\n \tsg->length = data_len;\n \n@@ -946,7 +946,7 @@ build_cipher_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \n \t/* 1st seg */\n \tsg = &cf->sg[2];\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - data_offset;\n \tsg->offset = data_offset;\n \n@@ -955,7 +955,7 @@ build_cipher_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -980,7 +980,7 @@ build_cipher_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \n \t/* 1st seg */\n \tsg++;\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - data_offset;\n \tsg->offset = data_offset;\n \n@@ -989,7 +989,7 @@ build_cipher_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1121,7 +1121,7 @@ build_cipher_auth_gcm_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tcpu_to_hw_sg(out_sg);\n \n \t/* 1st seg */\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - sym->aead.data.offset;\n \tsg->offset = sym->aead.data.offset;\n \n@@ -1130,7 +1130,7 @@ build_cipher_auth_gcm_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1178,7 +1178,7 @@ build_cipher_auth_gcm_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \n \t/* 3rd seg */\n \tsg++;\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - sym->aead.data.offset;\n \tsg->offset = sym->aead.data.offset;\n \n@@ -1187,7 +1187,7 @@ build_cipher_auth_gcm_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1367,7 +1367,7 @@ build_cipher_auth_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tcpu_to_hw_sg(out_sg);\n \n \t/* 1st seg */\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - sym->auth.data.offset;\n \tsg->offset = sym->auth.data.offset;\n \n@@ -1376,7 +1376,7 @@ build_cipher_auth_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1415,7 +1415,7 @@ build_cipher_auth_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \n \t/* 2nd seg */\n \tsg++;\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len - sym->auth.data.offset;\n \tsg->offset = sym->auth.data.offset;\n \n@@ -1424,7 +1424,7 @@ build_cipher_auth_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1555,10 +1555,10 @@ build_proto(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tcf = &ctx->job;\n \tctx->op = op;\n \n-\tsrc_start_addr = rte_pktmbuf_mtophys(sym->m_src);\n+\tsrc_start_addr = rte_pktmbuf_iova(sym->m_src);\n \n \tif (sym->m_dst)\n-\t\tdst_start_addr = rte_pktmbuf_mtophys(sym->m_dst);\n+\t\tdst_start_addr = rte_pktmbuf_iova(sym->m_dst);\n \telse\n \t\tdst_start_addr = src_start_addr;\n \n@@ -1614,7 +1614,7 @@ build_proto_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \n \t/* 1st seg */\n \tsg = &cf->sg[2];\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->offset = 0;\n \n \t/* Successive segs */\n@@ -1624,7 +1624,7 @@ build_proto_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \t\tmbuf = mbuf->next;\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->offset = 0;\n \t}\n \tsg->length = mbuf->buf_len - mbuf->data_off;\n@@ -1646,7 +1646,7 @@ build_proto_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tqm_sg_entry_set64(in_sg, rte_dpaa_mem_vtop(sg));\n \n \t/* 1st seg */\n-\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \tsg->length = mbuf->data_len;\n \tsg->offset = 0;\n \n@@ -1655,7 +1655,7 @@ build_proto_sg(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \twhile (mbuf) {\n \t\tcpu_to_hw_sg(sg);\n \t\tsg++;\n-\t\tqm_sg_entry_set64(sg, rte_pktmbuf_mtophys(mbuf));\n+\t\tqm_sg_entry_set64(sg, rte_pktmbuf_iova(mbuf));\n \t\tsg->length = mbuf->data_len;\n \t\tsg->offset = 0;\n \t\tin_len += sg->length;\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nindex d9b4267764..4492247801 100644\n--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -269,7 +269,7 @@ extract_cipher_auth_digest(struct nitrox_softreq *sr,\n \t op->sym->auth.data.length + digest->len))\n \t\treturn -EINVAL;\n \n-\tdigest->iova = rte_pktmbuf_mtophys_offset(mdst,\n+\tdigest->iova = rte_pktmbuf_iova_offset(mdst,\n \t\t\t\t\top->sym->auth.data.offset +\n \t\t\t\t\top->sym->auth.data.length);\n \tdigest->virt = rte_pktmbuf_mtod_offset(mdst, uint8_t *,\n@@ -318,7 +318,7 @@ create_sglist_from_mbuf(struct nitrox_sgtable *sgtbl, struct rte_mbuf *mbuf,\n \tif (datalen <= mlen)\n \t\tmlen = datalen;\n \tsglist[cnt].len = mlen;\n-\tsglist[cnt].iova = rte_pktmbuf_mtophys_offset(m, off);\n+\tsglist[cnt].iova = rte_pktmbuf_iova_offset(m, off);\n \tsglist[cnt].virt = rte_pktmbuf_mtod_offset(m, uint8_t *, off);\n \tsgtbl->total_bytes += mlen;\n \tcnt++;\n@@ -327,7 +327,7 @@ create_sglist_from_mbuf(struct nitrox_sgtable *sgtbl, struct rte_mbuf *mbuf,\n \t\tmlen = rte_pktmbuf_data_len(m) < datalen ?\n \t\t\trte_pktmbuf_data_len(m) : datalen;\n \t\tsglist[cnt].len = mlen;\n-\t\tsglist[cnt].iova = rte_pktmbuf_mtophys(m);\n+\t\tsglist[cnt].iova = rte_pktmbuf_iova(m);\n \t\tsglist[cnt].virt = rte_pktmbuf_mtod(m, uint8_t *);\n \t\tsgtbl->total_bytes += mlen;\n \t\tcnt++;\ndiff --git a/drivers/crypto/virtio/virtio_rxtx.c b/drivers/crypto/virtio/virtio_rxtx.c\nindex e9a63cb5a0..e1cb4ad104 100644\n--- a/drivers/crypto/virtio/virtio_rxtx.c\n+++ b/drivers/crypto/virtio/virtio_rxtx.c\n@@ -284,18 +284,18 @@ virtqueue_crypto_sym_enqueue_xmit(\n \t}\n \n \t/* indirect vring: src data */\n-\tdesc[idx].addr = rte_pktmbuf_mtophys_offset(sym_op->m_src, 0);\n+\tdesc[idx].addr = rte_pktmbuf_iova_offset(sym_op->m_src, 0);\n \tdesc[idx].len = (sym_op->cipher.data.offset\n \t\t+ sym_op->cipher.data.length);\n \tdesc[idx++].flags = VRING_DESC_F_NEXT;\n \n \t/* indirect vring: dst data */\n \tif (sym_op->m_dst) {\n-\t\tdesc[idx].addr = rte_pktmbuf_mtophys_offset(sym_op->m_dst, 0);\n+\t\tdesc[idx].addr = rte_pktmbuf_iova_offset(sym_op->m_dst, 0);\n \t\tdesc[idx].len = (sym_op->cipher.data.offset\n \t\t\t+ sym_op->cipher.data.length);\n \t} else {\n-\t\tdesc[idx].addr = rte_pktmbuf_mtophys_offset(sym_op->m_src, 0);\n+\t\tdesc[idx].addr = rte_pktmbuf_iova_offset(sym_op->m_src, 0);\n \t\tdesc[idx].len = (sym_op->cipher.data.offset\n \t\t\t+ sym_op->cipher.data.length);\n \t}\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c\nindex 30c467db71..da3a9822b8 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.c\n+++ b/drivers/net/axgbe/axgbe_rxtx.c\n@@ -95,7 +95,7 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\taxgbe_rx_queue_release(rxq);\n \t\treturn -ENOMEM;\n \t}\n-\trxq->ring_phys_addr = (uint64_t)dma->phys_addr;\n+\trxq->ring_phys_addr = (uint64_t)dma->iova;\n \trxq->desc = (volatile union axgbe_rx_desc *)dma->addr;\n \tmemset((void *)rxq->desc, 0, size);\n \t/* Allocate software ring */\n@@ -530,7 +530,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\treturn -ENOMEM;\n \t}\n \tmemset(tz->addr, 0, tsize);\n-\ttxq->ring_phys_addr = (uint64_t)tz->phys_addr;\n+\ttxq->ring_phys_addr = (uint64_t)tz->iova;\n \ttxq->desc = tz->addr;\n \ttxq->queue_id = queue_idx;\n \ttxq->port_id = dev->data->port_id;\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h b/drivers/net/octeontx2/otx2_ethdev_sec_tx.h\nindex f8130ca624..15122b4154 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h\n+++ b/drivers/net/octeontx2/otx2_ethdev_sec_tx.h\n@@ -87,7 +87,7 @@ otx2_sec_event_tx(struct otx2_ssogws *ws, struct rte_event *ev,\n \t */\n \trte_pktmbuf_append(m, extend_tail);\n \tdata = rte_pktmbuf_prepend(m, extend_head);\n-\tdata_addr = rte_pktmbuf_mtophys(m);\n+\tdata_addr = rte_pktmbuf_iova(m);\n \n \t/*\n \t * Move the Ethernet header, to insert otx2_ipsec_fp_out_hdr prior\ndiff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c\nindex efd32a86a5..0a1c8b568c 100644\n--- a/examples/fips_validation/main.c\n+++ b/examples/fips_validation/main.c\n@@ -531,7 +531,7 @@ prepare_auth_op(void)\n \n \tsym->auth.data.length = vec.pt.len;\n \tsym->auth.digest.data = pt + vec.pt.len;\n-\tsym->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset(\n+\tsym->auth.digest.phys_addr = rte_pktmbuf_iova_offset(\n \t\t\tenv.mbuf, vec.pt.len);\n \n \tmemcpy(pt, vec.pt.val, vec.pt.len);\n@@ -584,7 +584,7 @@ prepare_aead_op(void)\n \t\tmemcpy(pt, vec.pt.val, vec.pt.len);\n \t\tsym->aead.data.length = vec.pt.len;\n \t\tsym->aead.digest.data = pt + vec.pt.len;\n-\t\tsym->aead.digest.phys_addr = rte_pktmbuf_mtophys_offset(\n+\t\tsym->aead.digest.phys_addr = rte_pktmbuf_iova_offset(\n \t\t\t\tenv.mbuf, vec.pt.len);\n \t} else {\n \t\tuint8_t *ct;\ndiff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h\nindex 7259575a77..a1414ed7cd 100644\n--- a/lib/librte_mbuf/rte_mbuf.h\n+++ b/lib/librte_mbuf/rte_mbuf.h\n@@ -151,13 +151,6 @@ rte_mbuf_data_iova(const struct rte_mbuf *mb)\n \treturn mb->buf_iova + mb->data_off;\n }\n \n-__rte_deprecated\n-static inline phys_addr_t\n-rte_mbuf_data_dma_addr(const struct rte_mbuf *mb)\n-{\n-\treturn rte_mbuf_data_iova(mb);\n-}\n-\n /**\n * Return the default IO address of the beginning of the mbuf data\n *\n@@ -176,13 +169,6 @@ rte_mbuf_data_iova_default(const struct rte_mbuf *mb)\n \treturn mb->buf_iova + RTE_PKTMBUF_HEADROOM;\n }\n \n-__rte_deprecated\n-static inline phys_addr_t\n-rte_mbuf_data_dma_addr_default(const struct rte_mbuf *mb)\n-{\n-\treturn rte_mbuf_data_iova_default(mb);\n-}\n-\n /**\n * Return the mbuf owning the data buffer address of an indirect mbuf.\n *\n@@ -1537,13 +1523,6 @@ static inline struct rte_mbuf *rte_pktmbuf_lastseg(struct rte_mbuf *m)\n \treturn m;\n }\n \n-/* deprecated */\n-#define rte_pktmbuf_mtophys_offset(m, o) \\\n-\trte_pktmbuf_iova_offset(m, o)\n-\n-/* deprecated */\n-#define rte_pktmbuf_mtophys(m) rte_pktmbuf_iova(m)\n-\n /**\n * A macro that returns the length of the packet.\n *\n", "prefixes": [ "3/4" ] }