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{
    "id": 77514,
    "url": "http://patches.dpdk.org/api/patches/77514/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-7-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599855987-25976-7-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599855987-25976-7-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2020-09-11T20:26:11",
    "name": "[06/22] event/dlb2: add probe",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e43e240077cca9d0c02c076ee4b8b15a545ccb8e",
    "submitter": {
        "id": 826,
        "url": "http://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-7-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 12164,
            "url": "http://patches.dpdk.org/api/series/12164/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12164",
            "date": "2020-09-11T20:26:05",
            "name": "Add DLB2 PMD",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/12164/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77514/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/77514/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EAE32A04C1;\n\tFri, 11 Sep 2020 22:31:30 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 018941C1E7;\n\tFri, 11 Sep 2020 22:30:29 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id D8B1E1C126\n for <dev@dpdk.org>; Fri, 11 Sep 2020 22:29:58 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 13:29:56 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga005.jf.intel.com with ESMTP; 11 Sep 2020 13:29:54 -0700"
        ],
        "IronPort-SDR": [
            "\n CkwbBZHmDU6aJBYuDUVL1Hm+CEsv5ISfAz7lhlc3/bYdKiHTcmcqtVHBEQk+byZU16+yGL+AJs\n 665Pd6oTc9Ww==",
            "\n wj6LChxj7AzLo2lwV4iGK/XFeNaUWqeDTHodtNsYVynnsBN0KSIdrFyZjlTdMjr53MS4bWUNLU\n O5FshHnIxSbQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9741\"; a=\"156244348\"",
            "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"156244348\"",
            "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"481453525\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "Anatoly Burakov <anatoly.burakov@intel.com>",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com",
        "Date": "Fri, 11 Sep 2020 15:26:11 -0500",
        "Message-Id": "<1599855987-25976-7-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 06/22] event/dlb2: add probe",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The DLB2 hardware is a PCI device. This commit adds\nsupport for probe and other initialization. The\ndlb2_iface.[ch] files implement a flexible interface\nthat supports both the PF PMD and the bifurcated PMD.\nThe bifurcated PMD will be released in a future\npatch set. Note that the flexible interface is only\nused for configuration, and is not used in the data\npath. The shared code is added in pf/base.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c                      |  557 ++++++\n drivers/event/dlb2/dlb2_iface.c                |   42 +\n drivers/event/dlb2/dlb2_iface.h                |   29 +\n drivers/event/dlb2/dlb2_priv.h                 |    5 +\n drivers/event/dlb2/meson.build                 |    6 +-\n drivers/event/dlb2/pf/base/dlb2_hw_types.h     |  367 ++++\n drivers/event/dlb2/pf/base/dlb2_mbox.h         |  596 ++++++\n drivers/event/dlb2/pf/base/dlb2_osdep.h        |  248 +++\n drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h |  447 +++++\n drivers/event/dlb2/pf/base/dlb2_osdep_list.h   |  131 ++\n drivers/event/dlb2/pf/base/dlb2_osdep_types.h  |   31 +\n drivers/event/dlb2/pf/base/dlb2_regs.h         | 2527 ++++++++++++++++++++++++\n drivers/event/dlb2/pf/base/dlb2_resource.c     |  274 +++\n drivers/event/dlb2/pf/base/dlb2_resource.h     | 1913 ++++++++++++++++++\n drivers/event/dlb2/pf/dlb2_main.c              |  620 ++++++\n drivers/event/dlb2/pf/dlb2_main.h              |  107 +\n drivers/event/dlb2/pf/dlb2_pf.c                |  251 +++\n 17 files changed, 8150 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/dlb2/dlb2.c\n create mode 100644 drivers/event/dlb2/dlb2_iface.c\n create mode 100644 drivers/event/dlb2/dlb2_iface.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_mbox.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_list.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_osdep_types.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_regs.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.c\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.h\n create mode 100644 drivers/event/dlb2/pf/dlb2_main.c\n create mode 100644 drivers/event/dlb2/pf/dlb2_main.h\n create mode 100644 drivers/event/dlb2/pf/dlb2_pf.c",
    "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nnew file mode 100644\nindex 0000000..7ff7dac\n--- /dev/null\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -0,0 +1,557 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <assert.h>\n+#include <errno.h>\n+#include <nmmintrin.h>\n+#include <pthread.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <sys/fcntl.h>\n+\n+#include <rte_common.h>\n+#include <rte_config.h>\n+#include <rte_cycles.h>\n+#include <rte_debug.h>\n+#include <rte_dev.h>\n+#include <rte_errno.h>\n+#include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+#include <rte_kvargs.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+#include <rte_mbuf.h>\n+#include <rte_prefetch.h>\n+#include <rte_ring.h>\n+#include <rte_string_fns.h>\n+\n+#include \"dlb2_priv.h\"\n+#include \"dlb2_iface.h\"\n+#include \"dlb2_inline_fns.h\"\n+\n+#if !defined RTE_ARCH_X86_64\n+#error \"This implementation only supports RTE_ARCH_X86_64 architecture.\"\n+#endif\n+\n+/*\n+ * Resources exposed to eventdev. Some values overridden at runtime using\n+ * values returned by the DLB kernel driver.\n+ */\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)\n+#error \"RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member max_event_queues\"\n+#endif\n+static struct rte_event_dev_info evdev_dlb2_default_info = {\n+\t.driver_name = \"\", /* probe will set */\n+\t.min_dequeue_timeout_ns = DLB2_MIN_DEQUEUE_TIMEOUT_NS,\n+\t.max_dequeue_timeout_ns = DLB2_MAX_DEQUEUE_TIMEOUT_NS,\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB2_MAX_NUM_LDB_QUEUES)\n+\t.max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,\n+#else\n+\t.max_event_queues = DLB2_MAX_NUM_LDB_QUEUES,\n+#endif\n+\t.max_event_queue_flows = DLB2_MAX_NUM_FLOWS,\n+\t.max_event_queue_priority_levels = DLB2_QID_PRIORITIES,\n+\t.max_event_priority_levels = DLB2_QID_PRIORITIES,\n+\t.max_event_ports = DLB2_MAX_NUM_LDB_PORTS,\n+\t.max_event_port_dequeue_depth = DLB2_MAX_CQ_DEPTH,\n+\t.max_event_port_enqueue_depth = DLB2_MAX_ENQUEUE_DEPTH,\n+\t.max_event_port_links = DLB2_MAX_NUM_QIDS_PER_LDB_CQ,\n+\t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n+\t.max_single_link_event_port_queue_pairs = DLB2_MAX_NUM_DIR_PORTS,\n+\t.event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |\n+\t\t\t  RTE_EVENT_DEV_CAP_EVENT_QOS |\n+\t\t\t  RTE_EVENT_DEV_CAP_BURST_MODE |\n+\t\t\t  RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |\n+\t\t\t  RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |\n+\t\t\t  RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),\n+};\n+\n+/* These functions will vary based on processor capabilities */\n+static struct dlb2_port_low_level_io_functions qm_mmio_fns;\n+\n+struct process_local_port_data\n+dlb2_port[DLB2_MAX_NUM_PORTS][DLB2_NUM_PORT_TYPES];\n+\n+/* override defaults with value(s) provided on command line */\n+static void\n+dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,\n+\t\t\t\t int *qid_depth_thresholds)\n+{\n+\tint q;\n+\n+\tfor (q = 0; q < DLB2_MAX_NUM_QUEUES; q++) {\n+\t\tif (qid_depth_thresholds[q] != 0)\n+\t\t\tdlb2->ev_queues[q].depth_threshold =\n+\t\t\t\tqid_depth_thresholds[q];\n+\t}\n+}\n+\n+static int\n+dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)\n+{\n+\tstruct dlb2_hw_dev *handle = &dlb2->qm_instance;\n+\tstruct dlb2_hw_resource_info *dlb2_info = &handle->info;\n+\tint ret;\n+\n+\t/* Query driver resources provisioned for this VF */\n+\n+\tret = dlb2_iface_get_num_resources(handle,\n+\t\t\t\t\t   &dlb2->hw_rsrc_query_results);\n+\tif (ret) {\n+\t\tDLB2_LOG_ERR(\"ioctl get dlb2 num resources, err=%d\\n\",\n+\t\t\t     ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Complete filling in device resource info returned to evdev app,\n+\t * overriding any default values.\n+\t * The capabilities (CAPs) were set at compile time.\n+\t */\n+\n+\tevdev_dlb2_default_info.max_event_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues;\n+\n+\tevdev_dlb2_default_info.max_event_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_ports;\n+\n+\tevdev_dlb2_default_info.max_num_events =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\n+\t/* Save off values used when creating the scheduling domain. */\n+\n+\thandle->info.num_sched_domains =\n+\t\tdlb2->hw_rsrc_query_results.num_sched_domains;\n+\n+\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\n+\thandle->info.hw_rsrc_max.num_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues +\n+\t\tdlb2->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_ports;\n+\n+\thandle->info.hw_rsrc_max.num_dir_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.reorder_window_size =\n+\t\tdlb2->hw_rsrc_query_results.num_hist_list_entries;\n+\n+\trte_memcpy(dlb2_info, &handle->info.hw_rsrc_max, sizeof(*dlb2_info));\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_qm_mmio_fn_init(void)\n+{\n+\t/* Process-local function pointers for performing low level port i/o */\n+\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIR64B))\n+\t\tqm_mmio_fns.pp_enqueue_four = dlb2_movdir64b;\n+\telse\n+\t\tqm_mmio_fns.pp_enqueue_four = dlb2_movntdq;\n+}\n+\n+#define RTE_BASE_10 10\n+\n+int dlb2_string_to_int(int *result, const char *str)\n+{\n+\tlong ret;\n+\n+\tif (str == NULL || result == NULL)\n+\t\treturn -EINVAL;\n+\n+\terrno = 0;\n+\tret = strtol(str, NULL, RTE_BASE_10);\n+\tif (errno)\n+\t\treturn -errno;\n+\n+\t/* long int and int may be different width for some architectures */\n+\tif (ret < INT_MIN || ret > INT_MAX)\n+\t\treturn -EINVAL;\n+\n+\t*result = ret;\n+\treturn 0;\n+}\n+\n+static int\n+set_numa_node(const char *key __rte_unused, const char *value, void *opaque)\n+{\n+\tint *socket_id = opaque;\n+\tint ret;\n+\n+\tret = dlb2_string_to_int(socket_id, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*socket_id > RTE_MAX_NUMA_NODES)\n+\t\treturn -EINVAL;\n+\treturn 0;\n+}\n+\n+static int\n+set_max_num_events(const char *key __rte_unused,\n+\t\t   const char *value,\n+\t\t   void *opaque)\n+{\n+\tint *max_num_events = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(max_num_events, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\n+\tif (*max_num_events < 0 || *max_num_events >\n+\t\t\tDLB2_MAX_NUM_LDB_CREDITS) {\n+\t\tDLB2_LOG_ERR(\"dlb2: max_num_events must be between 0 and %d\\n\",\n+\t\t\t     DLB2_MAX_NUM_LDB_CREDITS);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_num_dir_credits(const char *key __rte_unused,\n+\t\t    const char *value,\n+\t\t    void *opaque)\n+{\n+\tint *num_dir_credits = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(num_dir_credits, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*num_dir_credits < 0 ||\n+\t    *num_dir_credits > DLB2_MAX_NUM_DIR_CREDITS) {\n+\t\tDLB2_LOG_ERR(\"dlb2: num_dir_credits must be between 0 and %d\\n\",\n+\t\t\t     DLB2_MAX_NUM_DIR_CREDITS);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_dev_id(const char *key __rte_unused,\n+\t   const char *value,\n+\t   void *opaque)\n+{\n+\tint *dev_id = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(dev_id, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_cos(const char *key __rte_unused,\n+\tconst char *value,\n+\tvoid *opaque)\n+{\n+\tenum dlb2_cos *cos_id = opaque;\n+\tint x = 0;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(&x, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (x != DLB2_COS_DEFAULT && (x < DLB2_COS_0 || x > DLB2_COS_3)) {\n+\t\tDLB2_LOG_ERR(\"COS %d out of range, must be 0-3\\n\", x);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*cos_id = x;\n+\n+\treturn 0;\n+}\n+\n+\n+static int\n+set_qid_depth_thresh(const char *key __rte_unused,\n+\t\t     const char *value,\n+\t\t     void *opaque)\n+{\n+\tstruct dlb2_qid_depth_thresholds *qid_thresh = opaque;\n+\tint first, last, thresh, i;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* command line override may take one of the following 3 forms:\n+\t * qid_depth_thresh=all:<threshold_value> ... all queues\n+\t * qid_depth_thresh=qidA-qidB:<threshold_value> ... a range of queues\n+\t * qid_depth_thresh=qid:<threshold_value> ... just one queue\n+\t */\n+\tif (sscanf(value, \"all:%d\", &thresh) == 1) {\n+\t\tfirst = 0;\n+\t\tlast = DLB2_MAX_NUM_QUEUES - 1;\n+\t} else if (sscanf(value, \"%d-%d:%d\", &first, &last, &thresh) == 3) {\n+\t\t/* we have everything we need */\n+\t} else if (sscanf(value, \"%d:%d\", &first, &thresh) == 2) {\n+\t\tlast = first;\n+\t} else {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth vdev arg. Should be all:val, qid-qid:val, or qid:val\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (first > last || first < 0 || last >= DLB2_MAX_NUM_QUEUES) {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth vdev arg, invalid qid value\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (thresh < 0 || thresh > DLB2_MAX_QUEUE_DEPTH_THRESHOLD) {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth vdev arg, threshold > %d\\n\",\n+\t\t\t     DLB2_MAX_QUEUE_DEPTH_THRESHOLD);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = first; i <= last; i++)\n+\t\tqid_thresh->val[i] = thresh; /* indexed by qid */\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_entry_points_init(struct rte_eventdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\t/* Eventdev PMD entry points */\n+}\n+\n+int\n+dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t    const char *name,\n+\t\t\t    struct dlb2_devargs *dlb2_args)\n+{\n+\tstruct dlb2_eventdev *dlb2;\n+\tint err, i;\n+\n+\tdlb2 = dev->data->dev_private;\n+\n+\tdlb2->event_dev = dev; /* backlink */\n+\n+\tevdev_dlb2_default_info.driver_name = name;\n+\n+\tdlb2->max_num_events_override = dlb2_args->max_num_events;\n+\tdlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;\n+\tdlb2->qm_instance.device_path_id = dlb2_args->dev_id;\n+\tdlb2->qm_instance.cos_id = dlb2_args->cos_id;\n+\n+\t/* Open the interface.\n+\t * For vdev mode, this means open the dlb2 kernel module.\n+\t */\n+\terr = dlb2_iface_open(&dlb2->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t     err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_iface_get_device_version(&dlb2->qm_instance,\n+\t\t\t\t\t    &dlb2->revision);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2: failed to get the device version, err=%d\\n\",\n+\t\t\t     err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_hw_query_resources(dlb2);\n+\tif (err) {\n+\t\tDLB2_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t     err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb2_iface_hardware_init(&dlb2->qm_instance);\n+\n+\terr = dlb2_iface_get_cq_poll_mode(&dlb2->qm_instance, &dlb2->poll_mode);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2: failed to get the poll mode, err=%d\\n\",\n+\t\t\t     err);\n+\t\treturn err;\n+\t}\n+\n+\t/* Initialize each port's token pop mode */\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++)\n+\t\tdlb2->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;\n+\n+\trte_spinlock_init(&dlb2->qm_instance.resource_lock);\n+\n+\tdlb2_qm_mmio_fn_init();\n+\n+\tdlb2_iface_low_level_io_init();\n+\n+\tdlb2_entry_points_init(dev);\n+\n+\tdlb2_init_queue_depth_thresholds(dlb2,\n+\t\t\t\t\t dlb2_args->qid_depth_thresholds.val);\n+\n+\treturn 0;\n+}\n+\n+int\n+dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t      const char *name)\n+{\n+\tstruct dlb2_eventdev *dlb2;\n+\tint err;\n+\n+\tdlb2 = dev->data->dev_private;\n+\n+\tevdev_dlb2_default_info.driver_name = name;\n+\n+\terr = dlb2_iface_open(&dlb2->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t     err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_hw_query_resources(dlb2);\n+\tif (err) {\n+\t\tDLB2_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t     err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb2_qm_mmio_fn_init();\n+\n+\tdlb2_iface_low_level_io_init();\n+\n+\tdlb2_entry_points_init(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+dlb2_parse_params(const char *params,\n+\t\t  const char *name,\n+\t\t  struct dlb2_devargs *dlb2_args)\n+{\n+\tint ret = 0;\n+\tstatic const char * const args[] = { NUMA_NODE_ARG,\n+\t\t\t\t      DLB2_MAX_NUM_EVENTS,\n+\t\t\t\t      DLB2_NUM_DIR_CREDITS,\n+\t\t\t\t      DEV_ID_ARG,\n+\t\t\t\t      DLB2_QID_DEPTH_THRESH_ARG,\n+\t\t\t\t      DLB2_COS_ARG,\n+\t\t\t\t      NULL };\n+\n+\tif (params != NULL && params[0] != '\\0') {\n+\t\tstruct rte_kvargs *kvlist = rte_kvargs_parse(params, args);\n+\n+\t\tif (!kvlist) {\n+\t\t\tRTE_LOG(INFO, PMD,\n+\t\t\t\t\"Ignoring unsupported parameters when creating device '%s'\\n\",\n+\t\t\t\tname);\n+\t\t} else {\n+\t\t\tint ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,\n+\t\t\t\t\t\t     set_numa_node,\n+\t\t\t\t\t\t     &dlb2_args->socket_id);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing numa node parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_MAX_NUM_EVENTS,\n+\t\t\t\t\t\t set_max_num_events,\n+\t\t\t\t\t\t &dlb2_args->max_num_events);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing max_num_events parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\tDLB2_NUM_DIR_CREDITS,\n+\t\t\t\t\tset_num_dir_credits,\n+\t\t\t\t\t&dlb2_args->num_dir_credits_override);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing num_dir_credits parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DEV_ID_ARG,\n+\t\t\t\t\t\t set_dev_id,\n+\t\t\t\t\t\t &dlb2_args->dev_id);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing dev_id parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(\n+\t\t\t\t\tkvlist,\n+\t\t\t\t\tDLB2_QID_DEPTH_THRESH_ARG,\n+\t\t\t\t\tset_qid_depth_thresh,\n+\t\t\t\t\t&dlb2_args->qid_depth_thresholds);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing qid_depth_thresh parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_COS_ARG,\n+\t\t\t\t\t\t set_cos,\n+\t\t\t\t\t\t &dlb2_args->cos_id);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing cos parameter\",\n+\t\t\t\t\t     name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\trte_kvargs_free(kvlist);\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+RTE_LOG_REGISTER(eventdev_dlb2_log_level, pmd.event.dlb2, NOTICE);\n+\ndiff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c\nnew file mode 100644\nindex 0000000..fefdf78\n--- /dev/null\n+++ b/drivers/event/dlb2/dlb2_iface.c\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <rte_debug.h>\n+#include <rte_bus_pci.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_mbuf.h>\n+#include <rte_ring.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+#include <rte_malloc.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+\n+#include \"dlb2_priv.h\"\n+\n+/* DLB2 PMD Internal interface function pointers.\n+ * If VDEV (bifurcated PMD),  these will resolve to functions that issue ioctls\n+ * serviced by DLB kernel module.\n+ * If PCI (PF PMD),  these will be implemented locally in user mode.\n+ */\n+\n+void (*dlb2_iface_low_level_io_init)(void);\n+\n+int (*dlb2_iface_open)(struct dlb2_hw_dev *handle, const char *name);\n+\n+int (*dlb2_iface_get_device_version)(struct dlb2_hw_dev *handle,\n+\t\t\t\t     uint8_t *revision);\n+\n+void (*dlb2_iface_hardware_init)(struct dlb2_hw_dev *handle);\n+\n+int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,\n+\t\t\t\t   enum dlb2_cq_poll_modes *mode);\n+\n+int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,\n+\t\t\t\t    struct dlb2_get_num_resources_args *rsrcs);\ndiff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h\nnew file mode 100644\nindex 0000000..4fb416e\n--- /dev/null\n+++ b/drivers/event/dlb2/dlb2_iface.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef _DLB2_IFACE_H_\n+#define _DLB2_IFACE_H_\n+\n+/* DLB2 PMD Internal interface function pointers.\n+ * If VDEV (bifurcated PMD),  these will resolve to functions that issue ioctls\n+ * serviced by DLB kernel module.\n+ * If PCI (PF PMD),  these will be implemented locally in user mode.\n+ */\n+\n+extern void (*dlb2_iface_low_level_io_init)(void);\n+\n+extern int (*dlb2_iface_open)(struct dlb2_hw_dev *handle, const char *name);\n+\n+extern int (*dlb2_iface_get_device_version)(struct dlb2_hw_dev *handle,\n+\t\t\t\t\t    uint8_t *revision);\n+\n+extern void (*dlb2_iface_hardware_init)(struct dlb2_hw_dev *handle);\n+\n+extern int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,\n+\t\t\t\t\t  enum dlb2_cq_poll_modes *mode);\n+\n+extern int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,\n+\t\t\t\tstruct dlb2_get_num_resources_args *rsrcs);\n+\n+#endif /* _DLB2_IFACE_H_ */\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 7bec835..68cab92 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -611,4 +611,9 @@ int dlb2_parse_params(const char *params,\n \t\t      struct dlb2_devargs *dlb2_args);\n \n int dlb2_string_to_int(int *result, const char *str);\n+\n+/* Extern globals */\n+\n+extern struct process_local_port_data dlb2_port[][DLB2_NUM_PORT_TYPES];\n+\n #endif\t/* _DLB2_PRIV_H_ */\ndiff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build\nindex d4fd39f..557e3b4 100644\n--- a/drivers/event/dlb2/meson.build\n+++ b/drivers/event/dlb2/meson.build\n@@ -1,7 +1,11 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2019-2020 Intel Corporation\n \n-sources = files(\n+sources = files('dlb2.c',\n+\t\t'dlb2_iface.c',\n+\t\t'pf/dlb2_main.c',\n+\t\t'pf/dlb2_pf.c',\n+\t\t'pf/base/dlb2_resource.c'\n )\n \n deps += ['mbuf', 'mempool', 'ring', 'bus_vdev', 'pci', 'bus_pci']\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nnew file mode 100644\nindex 0000000..428a5e8\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -0,0 +1,367 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_HW_TYPES_H\n+#define __DLB2_HW_TYPES_H\n+\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_osdep_list.h\"\n+#include \"dlb2_osdep_types.h\"\n+\n+#define DLB2_MAX_NUM_VDEVS\t\t\t16\n+#define DLB2_MAX_NUM_DOMAINS\t\t\t32\n+#define DLB2_MAX_NUM_LDB_QUEUES\t\t\t32 /* LDB == load-balanced */\n+#define DLB2_MAX_NUM_DIR_QUEUES\t\t\t64 /* DIR == directed */\n+#define DLB2_MAX_NUM_LDB_PORTS\t\t\t64\n+#define DLB2_MAX_NUM_DIR_PORTS\t\t\t64\n+#define DLB2_MAX_NUM_LDB_CREDITS\t\t(8 * 1024)\n+#define DLB2_MAX_NUM_DIR_CREDITS\t\t(2 * 1024)\n+#define DLB2_MAX_NUM_HIST_LIST_ENTRIES\t\t2048\n+#define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n+#define DLB2_MAX_NUM_QIDS_PER_LDB_CQ\t\t8\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n+#define DLB2_QID_PRIORITIES\t\t\t8\n+#define DLB2_NUM_ARB_WEIGHTS\t\t\t8\n+#define DLB2_MAX_WEIGHT\t\t\t\t255\n+#define DLB2_NUM_COS_DOMAINS\t\t\t4\n+#define DLB2_MAX_CQ_COMP_CHECK_LOOPS\t\t409600\n+#define DLB2_MAX_QID_EMPTY_CHECK_LOOPS\t\t(32 * 64 * 1024 * (800 / 30))\n+#ifdef FPGA\n+#define DLB2_HZ\t\t\t\t\t2000000\n+#else\n+#define DLB2_HZ\t\t\t\t\t800000000\n+#endif\n+\n+#define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710\n+#define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711\n+\n+/* Interrupt related macros */\n+#define DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n+#define DLB2_PF_NUM_CQ_INTERRUPT_VECTORS     64\n+#define DLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS \\\n+\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n+\t DLB2_PF_NUM_CQ_INTERRUPT_VECTORS)\n+#define DLB2_PF_NUM_COMPRESSED_MODE_VECTORS \\\n+\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + 1)\n+#define DLB2_PF_NUM_PACKED_MODE_VECTORS \\\n+\tDLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS\n+#define DLB2_PF_COMPRESSED_MODE_CQ_VECTOR_ID \\\n+\tDLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS\n+\n+/* DLB non-CQ interrupts (alarm, mailbox, WDT) */\n+#define DLB2_INT_NON_CQ 0\n+\n+#define DLB2_ALARM_HW_SOURCE_SYS 0\n+#define DLB2_ALARM_HW_SOURCE_DLB 1\n+\n+#define DLB2_ALARM_HW_UNIT_CHP 4\n+\n+#define DLB2_ALARM_SYS_AID_ILLEGAL_QID\t\t3\n+#define DLB2_ALARM_SYS_AID_DISABLED_QID\t\t4\n+#define DLB2_ALARM_SYS_AID_ILLEGAL_HCW\t\t5\n+#define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ\t1\n+#define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2\n+\n+#define DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n+#define DLB2_VF_NUM_CQ_INTERRUPT_VECTORS     31\n+#define DLB2_VF_BASE_CQ_VECTOR_ID\t     0\n+#define DLB2_VF_LAST_CQ_VECTOR_ID\t     30\n+#define DLB2_VF_MBOX_VECTOR_ID\t\t     31\n+#define DLB2_VF_TOTAL_NUM_INTERRUPT_VECTORS \\\n+\t(DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n+\t DLB2_VF_NUM_CQ_INTERRUPT_VECTORS)\n+\n+#define DLB2_VDEV_MAX_NUM_INTERRUPT_VECTORS (DLB2_MAX_NUM_LDB_PORTS + \\\n+\t\t\t\t\t     DLB2_MAX_NUM_DIR_PORTS + 1)\n+\n+/*\n+ * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by\n+ * the PF driver.\n+ */\n+#define DLB2_DRV_LDB_PP_BASE   0x2300000\n+#define DLB2_DRV_LDB_PP_STRIDE 0x1000\n+#define DLB2_DRV_LDB_PP_BOUND  (DLB2_DRV_LDB_PP_BASE + \\\n+\t\t\t\tDLB2_DRV_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_DRV_DIR_PP_BASE   0x2200000\n+#define DLB2_DRV_DIR_PP_STRIDE 0x1000\n+#define DLB2_DRV_DIR_PP_BOUND  (DLB2_DRV_DIR_PP_BASE + \\\n+\t\t\t\tDLB2_DRV_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)\n+#define DLB2_LDB_PP_BASE       0x2100000\n+#define DLB2_LDB_PP_STRIDE     0x1000\n+#define DLB2_LDB_PP_BOUND      (DLB2_LDB_PP_BASE + \\\n+\t\t\t\tDLB2_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_LDB_PP_OFFS(id)   (DLB2_LDB_PP_BASE + (id) * DLB2_PP_SIZE)\n+#define DLB2_DIR_PP_BASE       0x2000000\n+#define DLB2_DIR_PP_STRIDE     0x1000\n+#define DLB2_DIR_PP_BOUND      (DLB2_DIR_PP_BASE + \\\n+\t\t\t\tDLB2_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)\n+#define DLB2_DIR_PP_OFFS(id)   (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)\n+\n+struct dlb2_resource_id {\n+\tu32 phys_id;\n+\tu32 virt_id;\n+\tu8 vdev_owned;\n+\tu8 vdev_id;\n+};\n+\n+struct dlb2_freelist {\n+\tu32 base;\n+\tu32 bound;\n+\tu32 offset;\n+};\n+\n+static inline u32 dlb2_freelist_count(struct dlb2_freelist *list)\n+{\n+\treturn list->bound - list->base - list->offset;\n+}\n+\n+struct dlb2_hcw {\n+\tu64 data;\n+\t/* Word 3 */\n+\tu16 opaque;\n+\tu8 qid;\n+\tu8 sched_type:2;\n+\tu8 priority:3;\n+\tu8 msg_type:3;\n+\t/* Word 4 */\n+\tu16 lock_id;\n+\tu8 ts_flag:1;\n+\tu8 rsvd1:2;\n+\tu8 no_dec:1;\n+\tu8 cmp_id:4;\n+\tu8 cq_token:1;\n+\tu8 qe_comp:1;\n+\tu8 qe_frag:1;\n+\tu8 qe_valid:1;\n+\tu8 int_arm:1;\n+\tu8 error:1;\n+\tu8 rsvd:2;\n+};\n+\n+struct dlb2_ldb_queue {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\tu32 num_qid_inflights;\n+\tu32 aqed_limit;\n+\tu32 sn_group; /* sn == sequence number */\n+\tu32 sn_slot;\n+\tu32 num_mappings;\n+\tu8 sn_cfg_valid;\n+\tu8 num_pending_additions;\n+\tu8 owned;\n+\tu8 configured;\n+};\n+\n+/*\n+ * Directed ports and queues are paired by nature, so the driver tracks them\n+ * with a single data structure.\n+ */\n+struct dlb2_dir_pq_pair {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\tu32 ref_cnt;\n+\tu8 init_tkn_cnt;\n+\tu8 queue_configured;\n+\tu8 port_configured;\n+\tu8 owned;\n+\tu8 enabled;\n+};\n+\n+enum dlb2_qid_map_state {\n+\t/* The slot doesn't contain a valid queue mapping */\n+\tDLB2_QUEUE_UNMAPPED,\n+\t/* The slot contains a valid queue mapping */\n+\tDLB2_QUEUE_MAPPED,\n+\t/* The driver is mapping a queue into this slot */\n+\tDLB2_QUEUE_MAP_IN_PROG,\n+\t/* The driver is unmapping a queue from this slot */\n+\tDLB2_QUEUE_UNMAP_IN_PROG,\n+\t/*\n+\t * The driver is unmapping a queue from this slot, and once complete\n+\t * will replace it with another mapping.\n+\t */\n+\tDLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP,\n+};\n+\n+struct dlb2_ldb_port_qid_map {\n+\tenum dlb2_qid_map_state state;\n+\tu16 qid;\n+\tu16 pending_qid;\n+\tu8 priority;\n+\tu8 pending_priority;\n+};\n+\n+struct dlb2_ldb_port {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\t/* The qid_map represents the hardware QID mapping state. */\n+\tstruct dlb2_ldb_port_qid_map qid_map[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_limit;\n+\tu32 ref_cnt;\n+\tu8 init_tkn_cnt;\n+\tu8 num_pending_removals;\n+\tu8 num_mappings;\n+\tu8 owned;\n+\tu8 enabled;\n+\tu8 configured;\n+};\n+\n+struct dlb2_sn_group {\n+\tu32 mode;\n+\tu32 sequence_numbers_per_queue;\n+\tu32 slot_use_bitmap;\n+\tu32 id;\n+};\n+\n+static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)\n+{\n+\tu32 mask[] = {\n+\t\t0x0000ffff,  /* 64 SNs per queue */\n+\t\t0x000000ff,  /* 128 SNs per queue */\n+\t\t0x0000000f,  /* 256 SNs per queue */\n+\t\t0x00000003,  /* 512 SNs per queue */\n+\t\t0x00000001}; /* 1024 SNs per queue */\n+\n+\treturn group->slot_use_bitmap == mask[group->mode];\n+}\n+\n+static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)\n+{\n+\tu32 bound[6] = {16, 8, 4, 2, 1};\n+\tu32 i;\n+\n+\tfor (i = 0; i < bound[group->mode]; i++) {\n+\t\tif (!(group->slot_use_bitmap & (1 << i))) {\n+\t\t\tgroup->slot_use_bitmap |= 1 << i;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static inline void\n+dlb2_sn_group_free_slot(struct dlb2_sn_group *group, int slot)\n+{\n+\tgroup->slot_use_bitmap &= ~(1 << slot);\n+}\n+\n+static inline int dlb2_sn_group_used_slots(struct dlb2_sn_group *group)\n+{\n+\tint i, cnt = 0;\n+\n+\tfor (i = 0; i < 32; i++)\n+\t\tcnt += !!(group->slot_use_bitmap & (1 << i));\n+\n+\treturn cnt;\n+}\n+\n+struct dlb2_hw_domain {\n+\tstruct dlb2_function_resources *parent_func;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_list_head used_ldb_queues;\n+\tstruct dlb2_list_head used_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head used_dir_pq_pairs;\n+\tstruct dlb2_list_head avail_ldb_queues;\n+\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head avail_dir_pq_pairs;\n+\tu32 total_hist_list_entries;\n+\tu32 avail_hist_list_entries;\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_offset;\n+\tu32 num_ldb_credits;\n+\tu32 num_dir_credits;\n+\tu32 num_avail_aqed_entries;\n+\tu32 num_used_aqed_entries;\n+\tstruct dlb2_resource_id id;\n+\tint num_pending_removals;\n+\tint num_pending_additions;\n+\tu8 configured;\n+\tu8 started;\n+};\n+\n+struct dlb2_bitmap;\n+\n+struct dlb2_function_resources {\n+\tstruct dlb2_list_head avail_domains;\n+\tstruct dlb2_list_head used_domains;\n+\tstruct dlb2_list_head avail_ldb_queues;\n+\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head avail_dir_pq_pairs;\n+\tstruct dlb2_bitmap *avail_hist_list_entries;\n+\tu32 num_avail_domains;\n+\tu32 num_avail_ldb_queues;\n+\tu32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tu32 num_avail_dir_pq_pairs;\n+\tu32 num_avail_qed_entries;\n+\tu32 num_avail_dqed_entries;\n+\tu32 num_avail_aqed_entries;\n+\tu8 locked; /* (VDEV only) */\n+};\n+\n+/*\n+ * After initialization, each resource in dlb2_hw_resources is located in one\n+ * of the following lists:\n+ * -- The PF's available resources list. These are unconfigured resources owned\n+ *\tby the PF and not allocated to a dlb2 scheduling domain.\n+ * -- A VDEV's available resources list. These are VDEV-owned unconfigured\n+ *\tresources not allocated to a dlb2 scheduling domain.\n+ * -- A domain's available resources list. These are domain-owned unconfigured\n+ *\tresources.\n+ * -- A domain's used resources list. These are are domain-owned configured\n+ *\tresources.\n+ *\n+ * A resource moves to a new list when a VDEV or domain is created or destroyed,\n+ * or when the resource is configured.\n+ */\n+struct dlb2_hw_resources {\n+\tstruct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];\n+\tstruct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];\n+\tstruct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS];\n+\tstruct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];\n+};\n+\n+struct dlb2_mbox {\n+\tu32 *mbox;\n+\tu32 *isr_in_progress;\n+};\n+\n+struct dlb2_sw_mbox {\n+\tstruct dlb2_mbox vdev_to_pf;\n+\tstruct dlb2_mbox pf_to_vdev;\n+\tvoid (*pf_to_vdev_inject)(void *arg);\n+\tvoid *pf_to_vdev_inject_arg;\n+};\n+\n+struct dlb2_hw {\n+\t/* BAR 0 address */\n+\tvoid  *csr_kva;\n+\tunsigned long csr_phys_addr;\n+\t/* BAR 2 address */\n+\tvoid  *func_kva;\n+\tunsigned long func_phys_addr;\n+\n+\t/* Resource tracking */\n+\tstruct dlb2_hw_resources rsrcs;\n+\tstruct dlb2_function_resources pf;\n+\tstruct dlb2_function_resources vdev[DLB2_MAX_NUM_VDEVS];\n+\tstruct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS];\n+\tu8 cos_reservation[DLB2_NUM_COS_DOMAINS];\n+\n+\t/* Virtualization */\n+\tint virt_mode;\n+\tstruct dlb2_sw_mbox mbox[DLB2_MAX_NUM_VDEVS];\n+\tunsigned int pasid[DLB2_MAX_NUM_VDEVS];\n+};\n+\n+#endif /* __DLB2_HW_TYPES_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_mbox.h b/drivers/event/dlb2/pf/base/dlb2_mbox.h\nnew file mode 100644\nindex 0000000..ce462c0\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_mbox.h\n@@ -0,0 +1,596 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_BASE_DLB2_MBOX_H\n+#define __DLB2_BASE_DLB2_MBOX_H\n+\n+#include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs.h\"\n+\n+#define DLB2_MBOX_INTERFACE_VERSION 1\n+\n+/*\n+ * The PF uses its PF->VF mailbox to send responses to VF requests, as well as\n+ * to send requests of its own (e.g. notifying a VF of an impending FLR).\n+ * To avoid communication race conditions, e.g. the PF sends a response and then\n+ * sends a request before the VF reads the response, the PF->VF mailbox is\n+ * divided into two sections:\n+ * - Bytes 0-47: PF responses\n+ * - Bytes 48-63: PF requests\n+ *\n+ * Partitioning the PF->VF mailbox allows responses and requests to occupy the\n+ * mailbox simultaneously.\n+ */\n+#define DLB2_PF2VF_RESP_BYTES\t  48\n+#define DLB2_PF2VF_RESP_BASE\t  0\n+#define DLB2_PF2VF_RESP_BASE_WORD (DLB2_PF2VF_RESP_BASE / 4)\n+\n+#define DLB2_PF2VF_REQ_BYTES\t  16\n+#define DLB2_PF2VF_REQ_BASE\t  (DLB2_PF2VF_RESP_BASE + DLB2_PF2VF_RESP_BYTES)\n+#define DLB2_PF2VF_REQ_BASE_WORD  (DLB2_PF2VF_REQ_BASE / 4)\n+\n+/*\n+ * Similarly, the VF->PF mailbox is divided into two sections:\n+ * - Bytes 0-239: VF requests\n+ * -- (Bytes 0-3 are unused due to a hardware errata)\n+ * - Bytes 240-255: VF responses\n+ */\n+#define DLB2_VF2PF_REQ_BYTES\t 236\n+#define DLB2_VF2PF_REQ_BASE\t 4\n+#define DLB2_VF2PF_REQ_BASE_WORD (DLB2_VF2PF_REQ_BASE / 4)\n+\n+#define DLB2_VF2PF_RESP_BYTES\t  16\n+#define DLB2_VF2PF_RESP_BASE\t  (DLB2_VF2PF_REQ_BASE + DLB2_VF2PF_REQ_BYTES)\n+#define DLB2_VF2PF_RESP_BASE_WORD (DLB2_VF2PF_RESP_BASE / 4)\n+\n+/* VF-initiated commands */\n+enum dlb2_mbox_cmd_type {\n+\tDLB2_MBOX_CMD_REGISTER,\n+\tDLB2_MBOX_CMD_UNREGISTER,\n+\tDLB2_MBOX_CMD_GET_NUM_RESOURCES,\n+\tDLB2_MBOX_CMD_CREATE_SCHED_DOMAIN,\n+\tDLB2_MBOX_CMD_RESET_SCHED_DOMAIN,\n+\tDLB2_MBOX_CMD_CREATE_LDB_QUEUE,\n+\tDLB2_MBOX_CMD_CREATE_DIR_QUEUE,\n+\tDLB2_MBOX_CMD_CREATE_LDB_PORT,\n+\tDLB2_MBOX_CMD_CREATE_DIR_PORT,\n+\tDLB2_MBOX_CMD_ENABLE_LDB_PORT,\n+\tDLB2_MBOX_CMD_DISABLE_LDB_PORT,\n+\tDLB2_MBOX_CMD_ENABLE_DIR_PORT,\n+\tDLB2_MBOX_CMD_DISABLE_DIR_PORT,\n+\tDLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN,\n+\tDLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN,\n+\tDLB2_MBOX_CMD_MAP_QID,\n+\tDLB2_MBOX_CMD_UNMAP_QID,\n+\tDLB2_MBOX_CMD_START_DOMAIN,\n+\tDLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR,\n+\tDLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR,\n+\tDLB2_MBOX_CMD_ARM_CQ_INTR,\n+\tDLB2_MBOX_CMD_GET_NUM_USED_RESOURCES,\n+\tDLB2_MBOX_CMD_GET_SN_ALLOCATION,\n+\tDLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH,\n+\tDLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH,\n+\tDLB2_MBOX_CMD_PENDING_PORT_UNMAPS,\n+\tDLB2_MBOX_CMD_GET_COS_BW,\n+\tDLB2_MBOX_CMD_GET_SN_OCCUPANCY,\n+\tDLB2_MBOX_CMD_QUERY_CQ_POLL_MODE,\n+\n+\t/* NUM_QE_CMD_TYPES must be last */\n+\tNUM_DLB2_MBOX_CMD_TYPES,\n+};\n+\n+static const char dlb2_mbox_cmd_type_strings[][128] = {\n+\t\"DLB2_MBOX_CMD_REGISTER\",\n+\t\"DLB2_MBOX_CMD_UNREGISTER\",\n+\t\"DLB2_MBOX_CMD_GET_NUM_RESOURCES\",\n+\t\"DLB2_MBOX_CMD_CREATE_SCHED_DOMAIN\",\n+\t\"DLB2_MBOX_CMD_RESET_SCHED_DOMAIN\",\n+\t\"DLB2_MBOX_CMD_CREATE_LDB_QUEUE\",\n+\t\"DLB2_MBOX_CMD_CREATE_DIR_QUEUE\",\n+\t\"DLB2_MBOX_CMD_CREATE_LDB_PORT\",\n+\t\"DLB2_MBOX_CMD_CREATE_DIR_PORT\",\n+\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT\",\n+\t\"DLB2_MBOX_CMD_DISABLE_LDB_PORT\",\n+\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT\",\n+\t\"DLB2_MBOX_CMD_DISABLE_DIR_PORT\",\n+\t\"DLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN\",\n+\t\"DLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN\",\n+\t\"DLB2_MBOX_CMD_MAP_QID\",\n+\t\"DLB2_MBOX_CMD_UNMAP_QID\",\n+\t\"DLB2_MBOX_CMD_START_DOMAIN\",\n+\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR\",\n+\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR\",\n+\t\"DLB2_MBOX_CMD_ARM_CQ_INTR\",\n+\t\"DLB2_MBOX_CMD_GET_NUM_USED_RESOURCES\",\n+\t\"DLB2_MBOX_CMD_GET_SN_ALLOCATION\",\n+\t\"DLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH\",\n+\t\"DLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH\",\n+\t\"DLB2_MBOX_CMD_PENDING_PORT_UNMAPS\",\n+\t\"DLB2_MBOX_CMD_GET_COS_BW\",\n+\t\"DLB2_MBOX_CMD_GET_SN_OCCUPANCY\",\n+\t\"DLB2_MBOX_CMD_QUERY_CQ_POLL_MODE\",\n+};\n+\n+/* PF-initiated commands */\n+enum dlb2_mbox_vf_cmd_type {\n+\tDLB2_MBOX_VF_CMD_DOMAIN_ALERT,\n+\tDLB2_MBOX_VF_CMD_NOTIFICATION,\n+\tDLB2_MBOX_VF_CMD_IN_USE,\n+\n+\t/* NUM_DLB2_MBOX_VF_CMD_TYPES must be last */\n+\tNUM_DLB2_MBOX_VF_CMD_TYPES,\n+};\n+\n+static const char dlb2_mbox_vf_cmd_type_strings[][128] = {\n+\t\"DLB2_MBOX_VF_CMD_DOMAIN_ALERT\",\n+\t\"DLB2_MBOX_VF_CMD_NOTIFICATION\",\n+\t\"DLB2_MBOX_VF_CMD_IN_USE\",\n+};\n+\n+#define DLB2_MBOX_CMD_TYPE(hdr) \\\n+\t(((struct dlb2_mbox_req_hdr *)hdr)->type)\n+#define DLB2_MBOX_CMD_STRING(hdr) \\\n+\tdlb2_mbox_cmd_type_strings[DLB2_MBOX_CMD_TYPE(hdr)]\n+\n+enum dlb2_mbox_status_type {\n+\tDLB2_MBOX_ST_SUCCESS,\n+\tDLB2_MBOX_ST_INVALID_CMD_TYPE,\n+\tDLB2_MBOX_ST_VERSION_MISMATCH,\n+\tDLB2_MBOX_ST_INVALID_OWNER_VF,\n+};\n+\n+static const char dlb2_mbox_status_type_strings[][128] = {\n+\t\"DLB2_MBOX_ST_SUCCESS\",\n+\t\"DLB2_MBOX_ST_INVALID_CMD_TYPE\",\n+\t\"DLB2_MBOX_ST_VERSION_MISMATCH\",\n+\t\"DLB2_MBOX_ST_INVALID_OWNER_VF\",\n+};\n+\n+#define DLB2_MBOX_ST_TYPE(hdr) \\\n+\t(((struct dlb2_mbox_resp_hdr *)hdr)->status)\n+#define DLB2_MBOX_ST_STRING(hdr) \\\n+\tdlb2_mbox_status_type_strings[DLB2_MBOX_ST_TYPE(hdr)]\n+\n+/* This structure is always the first field in a request structure */\n+struct dlb2_mbox_req_hdr {\n+\tu32 type;\n+};\n+\n+/* This structure is always the first field in a response structure */\n+struct dlb2_mbox_resp_hdr {\n+\tu32 status;\n+};\n+\n+struct dlb2_mbox_register_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu16 min_interface_version;\n+\tu16 max_interface_version;\n+};\n+\n+struct dlb2_mbox_register_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 interface_version;\n+\tu8 pf_id;\n+\tu8 vf_id;\n+\tu8 is_auxiliary_vf;\n+\tu8 primary_vf_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_unregister_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_unregister_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_get_num_resources_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_get_num_resources_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu16 num_sched_domains;\n+\tu16 num_ldb_queues;\n+\tu16 num_ldb_ports;\n+\tu16 num_cos_ldb_ports[4];\n+\tu16 num_dir_ports;\n+\tu32 num_atomic_inflights;\n+\tu32 num_hist_list_entries;\n+\tu32 max_contiguous_hist_list_entries;\n+\tu16 num_ldb_credits;\n+\tu16 num_dir_credits;\n+};\n+\n+struct dlb2_mbox_create_sched_domain_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 num_ldb_queues;\n+\tu32 num_ldb_ports;\n+\tu32 num_cos_ldb_ports[4];\n+\tu32 num_dir_ports;\n+\tu32 num_atomic_inflights;\n+\tu32 num_hist_list_entries;\n+\tu32 num_ldb_credits;\n+\tu32 num_dir_credits;\n+\tu8 cos_strict;\n+\tu8 padding0[3];\n+\tu32 padding1;\n+};\n+\n+struct dlb2_mbox_create_sched_domain_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_reset_sched_domain_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_reset_sched_domain_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+};\n+\n+struct dlb2_mbox_create_ldb_queue_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 num_sequence_numbers;\n+\tu32 num_qid_inflights;\n+\tu32 num_atomic_inflights;\n+\tu32 lock_id_comp_level;\n+\tu32 depth_threshold;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_create_ldb_queue_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_create_dir_queue_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 depth_threshold;\n+};\n+\n+struct dlb2_mbox_create_dir_queue_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_create_ldb_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu16 cq_depth;\n+\tu16 cq_history_list_size;\n+\tu8 cos_id;\n+\tu8 cos_strict;\n+\tu16 padding1;\n+\tu64 cq_base_address;\n+};\n+\n+struct dlb2_mbox_create_ldb_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_create_dir_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu64 cq_base_address;\n+\tu16 cq_depth;\n+\tu16 padding0;\n+\ts32 queue_id;\n+};\n+\n+struct dlb2_mbox_create_dir_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_enable_ldb_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_enable_ldb_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_disable_ldb_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_disable_ldb_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_enable_dir_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_enable_dir_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_disable_dir_port_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_disable_dir_port_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_ldb_port_owned_by_domain_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_ldb_port_owned_by_domain_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\ts32 owned;\n+};\n+\n+struct dlb2_mbox_dir_port_owned_by_domain_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_dir_port_owned_by_domain_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\ts32 owned;\n+};\n+\n+struct dlb2_mbox_map_qid_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 qid;\n+\tu32 priority;\n+\tu32 padding0;\n+};\n+\n+struct dlb2_mbox_map_qid_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 id;\n+};\n+\n+struct dlb2_mbox_unmap_qid_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 qid;\n+};\n+\n+struct dlb2_mbox_unmap_qid_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_start_domain_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+};\n+\n+struct dlb2_mbox_start_domain_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_enable_ldb_port_intr_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu16 port_id;\n+\tu16 thresh;\n+\tu16 vector;\n+\tu16 owner_vf;\n+\tu16 reserved[2];\n+};\n+\n+struct dlb2_mbox_enable_ldb_port_intr_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_enable_dir_port_intr_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu16 port_id;\n+\tu16 thresh;\n+\tu16 vector;\n+\tu16 owner_vf;\n+\tu16 reserved[2];\n+};\n+\n+struct dlb2_mbox_enable_dir_port_intr_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_arm_cq_intr_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 is_ldb;\n+};\n+\n+struct dlb2_mbox_arm_cq_intr_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 padding0;\n+};\n+\n+/*\n+ * The alert_id and aux_alert_data follows the format of the alerts defined in\n+ * dlb2_types.h. The alert id contains an enum dlb2_domain_alert_id value, and\n+ * the aux_alert_data value varies depending on the alert.\n+ */\n+struct dlb2_mbox_vf_alert_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 alert_id;\n+\tu32 aux_alert_data;\n+};\n+\n+enum dlb2_mbox_vf_notification_type {\n+\tDLB2_MBOX_VF_NOTIFICATION_PRE_RESET,\n+\tDLB2_MBOX_VF_NOTIFICATION_POST_RESET,\n+\n+\t/* NUM_DLB2_MBOX_VF_NOTIFICATION_TYPES must be last */\n+\tNUM_DLB2_MBOX_VF_NOTIFICATION_TYPES,\n+};\n+\n+struct dlb2_mbox_vf_notification_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 notification;\n+};\n+\n+struct dlb2_mbox_vf_in_use_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_vf_in_use_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 in_use;\n+};\n+\n+struct dlb2_mbox_get_sn_allocation_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 group_id;\n+};\n+\n+struct dlb2_mbox_get_sn_allocation_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 num;\n+};\n+\n+struct dlb2_mbox_get_ldb_queue_depth_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 queue_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_get_ldb_queue_depth_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 depth;\n+};\n+\n+struct dlb2_mbox_get_dir_queue_depth_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 queue_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_get_dir_queue_depth_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 depth;\n+};\n+\n+struct dlb2_mbox_pending_port_unmaps_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 domain_id;\n+\tu32 port_id;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_pending_port_unmaps_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 num;\n+};\n+\n+struct dlb2_mbox_get_cos_bw_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 cos_id;\n+};\n+\n+struct dlb2_mbox_get_cos_bw_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 num;\n+};\n+\n+struct dlb2_mbox_get_sn_occupancy_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 group_id;\n+};\n+\n+struct dlb2_mbox_get_sn_occupancy_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 num;\n+};\n+\n+struct dlb2_mbox_query_cq_poll_mode_cmd_req {\n+\tstruct dlb2_mbox_req_hdr hdr;\n+\tu32 padding;\n+};\n+\n+struct dlb2_mbox_query_cq_poll_mode_cmd_resp {\n+\tstruct dlb2_mbox_resp_hdr hdr;\n+\tu32 error_code;\n+\tu32 status;\n+\tu32 mode;\n+};\n+\n+#endif /* __DLB2_BASE_DLB2_MBOX_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep.h b/drivers/event/dlb2/pf/base/dlb2_osdep.h\nnew file mode 100644\nindex 0000000..c8d8d5b\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep.h\n@@ -0,0 +1,248 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_OSDEP_H\n+#define __DLB2_OSDEP_H\n+\n+#include <string.h>\n+#include <time.h>\n+#include <unistd.h>\n+#include <pthread.h>\n+\n+#include <rte_string_fns.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_spinlock.h>\n+#include \"../dlb2_main.h\"\n+#include \"dlb2_resource.h\"\n+#include \"../../dlb2_log.h\"\n+#include \"../../dlb2_user.h\"\n+\n+\n+#define DLB2_PCI_REG_READ(addr)        rte_read32((void *)addr)\n+#define DLB2_PCI_REG_WRITE(reg, value) rte_write32(value, (void *)reg)\n+\n+/* Read/write register 'reg' in the CSR BAR space */\n+#define DLB2_CSR_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->csr_kva + (reg)))\n+#define DLB2_CSR_RD(hw, reg) \\\n+\tDLB2_PCI_REG_READ(DLB2_CSR_REG_ADDR((hw), (reg)))\n+#define DLB2_CSR_WR(hw, reg, value) \\\n+\tDLB2_PCI_REG_WRITE(DLB2_CSR_REG_ADDR((hw), (reg)), (value))\n+\n+/* Read/write register 'reg' in the func BAR space */\n+#define DLB2_FUNC_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->func_kva + (reg)))\n+#define DLB2_FUNC_RD(hw, reg) \\\n+\tDLB2_PCI_REG_READ(DLB2_FUNC_REG_ADDR((hw), (reg)))\n+#define DLB2_FUNC_WR(hw, reg, value) \\\n+\tDLB2_PCI_REG_WRITE(DLB2_FUNC_REG_ADDR((hw), (reg)), (value))\n+\n+/* Map to PMDs logging interface */\n+#define DLB2_ERR(dev, fmt, args...) \\\n+\tDLB2_LOG_ERR(fmt, ## args)\n+\n+#define DLB2_INFO(dev, fmt, args...) \\\n+\tDLB2_LOG_INFO(fmt, ## args)\n+\n+#define DLB2_DEBUG(dev, fmt, args...) \\\n+\tDLB2_LOG_DBG(fmt, ## args)\n+\n+/**\n+ * os_udelay() - busy-wait for a number of microseconds\n+ * @usecs: delay duration.\n+ */\n+static inline void os_udelay(int usecs)\n+{\n+\trte_delay_us(usecs);\n+}\n+\n+/**\n+ * os_msleep() - sleep for a number of milliseconds\n+ * @usecs: delay duration.\n+ */\n+static inline void os_msleep(int msecs)\n+{\n+\trte_delay_ms(msecs);\n+}\n+\n+#define DLB2_PP_BASE(__is_ldb) \\\n+\t((__is_ldb) ? DLB2_LDB_PP_BASE : DLB2_DIR_PP_BASE)\n+\n+/**\n+ * os_map_producer_port() - map a producer port into the caller's address space\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: port ID\n+ * @is_ldb: true for load-balanced port, false for a directed port\n+ *\n+ * This function maps the requested producer port memory into the caller's\n+ * address space.\n+ *\n+ * Return:\n+ * Returns the base address at which the PP memory was mapped, else NULL.\n+ */\n+static inline void *os_map_producer_port(struct dlb2_hw *hw,\n+\t\t\t\t\t u8 port_id,\n+\t\t\t\t\t bool is_ldb)\n+{\n+\tuint64_t addr;\n+\tuint64_t pp_dma_base;\n+\n+\n+\tpp_dma_base = (uintptr_t)hw->func_kva + DLB2_PP_BASE(is_ldb);\n+\taddr = (pp_dma_base + (PAGE_SIZE * port_id));\n+\n+\treturn (void *)(uintptr_t)addr;\n+}\n+\n+/**\n+ * os_unmap_producer_port() - unmap a producer port\n+ * @addr: mapped producer port address\n+ *\n+ * This function undoes os_map_producer_port() by unmapping the producer port\n+ * memory from the caller's address space.\n+ *\n+ * Return:\n+ * Returns the base address at which the PP memory was mapped, else NULL.\n+ */\n+static inline void os_unmap_producer_port(struct dlb2_hw *hw, void *addr)\n+{\n+\tRTE_SET_USED(hw);\n+\tRTE_SET_USED(addr);\n+}\n+\n+/**\n+ * os_fence_hcw() - fence an HCW to ensure it arrives at the device\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @pp_addr: producer port address\n+ */\n+static inline void os_fence_hcw(struct dlb2_hw *hw, u64 *pp_addr)\n+{\n+\tRTE_SET_USED(hw);\n+\n+\t/* To ensure outstanding HCWs reach the device, read the PP address. IA\n+\t * memory ordering prevents reads from passing older writes, and the\n+\t * mfence also ensures this.\n+\t */\n+\trte_mb();\n+\n+\t*(volatile u64 *)pp_addr;\n+}\n+\n+/**\n+ * os_enqueue_four_hcws() - enqueue four HCWs to DLB\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @hcw: pointer to the 64B-aligned contiguous HCW memory\n+ * @addr: producer port address\n+ */\n+static inline void os_enqueue_four_hcws(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hcw *hcw,\n+\t\t\t\t\tvoid *addr)\n+{\n+\tstruct dlb2_dev *dlb2_dev;\n+\n+\tdlb2_dev = container_of(hw, struct dlb2_dev, hw);\n+\n+\tdlb2_dev->enqueue_four(hcw, addr);\n+}\n+\n+/**\n+ * DLB2_HW_ERR() - log an error message\n+ * @dlb2: dlb2_hw handle for a particular device.\n+ * @...: variable string args.\n+ */\n+#define DLB2_HW_ERR(dlb2, ...) do {\t\\\n+\tRTE_SET_USED(dlb2);\t\t\\\n+\tDLB2_ERR(dlb2, __VA_ARGS__);\t\\\n+} while (0)\n+\n+/**\n+ * DLB2_HW_DBG() - log an info message\n+ * @dlb2: dlb2_hw handle for a particular device.\n+ * @...: variable string args.\n+ */\n+#define DLB2_HW_DBG(dlb2, ...) do {\t\\\n+\tRTE_SET_USED(dlb2);\t\t\\\n+\tDLB2_DEBUG(dlb2, __VA_ARGS__);\t\\\n+} while (0)\n+\n+/* The callback runs until it completes all outstanding QID->CQ\n+ * map and unmap requests. To prevent deadlock, this function gives other\n+ * threads a chance to grab the resource mutex and configure hardware.\n+ */\n+static void *dlb2_complete_queue_map_unmap(void *__args)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)__args;\n+\tint ret;\n+\n+\twhile (1) {\n+\t\trte_spinlock_lock(&dlb2_dev->resource_mutex);\n+\n+\t\tret = dlb2_finish_unmap_qid_procedures(&dlb2_dev->hw);\n+\t\tret += dlb2_finish_map_qid_procedures(&dlb2_dev->hw);\n+\n+\t\tif (ret != 0) {\n+\t\t\trte_spinlock_unlock(&dlb2_dev->resource_mutex);\n+\t\t\t/* Relinquish the CPU so the application can process\n+\t\t\t * its CQs, so this function doesn't deadlock.\n+\t\t\t */\n+\t\t\tsched_yield();\n+\t\t} else {\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tdlb2_dev->worker_launched = false;\n+\n+\trte_spinlock_unlock(&dlb2_dev->resource_mutex);\n+\n+\treturn NULL;\n+}\n+\n+\n+/**\n+ * os_schedule_work() - launch a thread to process pending map and unmap work\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function launches a kernel thread that will run until all pending\n+ * map and unmap procedures are complete.\n+ */\n+static inline void os_schedule_work(struct dlb2_hw *hw)\n+{\n+\tstruct dlb2_dev *dlb2_dev;\n+\tpthread_t complete_queue_map_unmap_thread;\n+\tint ret;\n+\n+\tdlb2_dev = container_of(hw, struct dlb2_dev, hw);\n+\n+\tret = rte_ctrl_thread_create(&complete_queue_map_unmap_thread,\n+\t\t\t\t     \"dlb_queue_unmap_waiter\",\n+\t\t\t\t     NULL,\n+\t\t\t\t     dlb2_complete_queue_map_unmap,\n+\t\t\t\t     dlb2_dev);\n+\tif (ret)\n+\t\tDLB2_ERR(dlb2_dev,\n+\t\t\t \"Could not create queue complete map/unmap thread, err=%d\\n\",\n+\t\t\t ret);\n+\telse\n+\t\tdlb2_dev->worker_launched = true;\n+}\n+\n+/**\n+ * os_worker_active() - query whether the map/unmap worker thread is active\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function returns a boolean indicating whether a thread (launched by\n+ * os_schedule_work()) is active. This function is used to determine\n+ * whether or not to launch a worker thread.\n+ */\n+static inline bool os_worker_active(struct dlb2_hw *hw)\n+{\n+\tstruct dlb2_dev *dlb2_dev;\n+\n+\tdlb2_dev = container_of(hw, struct dlb2_dev, hw);\n+\n+\treturn dlb2_dev->worker_launched;\n+}\n+\n+#endif /*  __DLB2_OSDEP_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h b/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h\nnew file mode 100644\nindex 0000000..7e48878\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h\n@@ -0,0 +1,447 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_OSDEP_BITMAP_H\n+#define __DLB2_OSDEP_BITMAP_H\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <rte_bitmap.h>\n+#include <rte_string_fns.h>\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+#include \"../dlb2_main.h\"\n+\n+/*************************/\n+/*** Bitmap operations ***/\n+/*************************/\n+struct dlb2_bitmap {\n+\tstruct rte_bitmap *map;\n+\tunsigned int len;\n+};\n+\n+/**\n+ * dlb2_bitmap_alloc() - alloc a bitmap data structure\n+ * @bitmap: pointer to dlb2_bitmap structure pointer.\n+ * @len: number of entries in the bitmap.\n+ *\n+ * This function allocates a bitmap and initializes it with length @len. All\n+ * entries are initially zero.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or len is 0.\n+ * ENOMEM - could not allocate memory for the bitmap data structure.\n+ */\n+static inline int dlb2_bitmap_alloc(struct dlb2_bitmap **bitmap,\n+\t\t\t\t    unsigned int len)\n+{\n+\tstruct dlb2_bitmap *bm;\n+\tvoid *mem;\n+\tuint32_t alloc_size;\n+\tuint32_t nbits = (uint32_t)len;\n+\n+\tif (!bitmap || nbits == 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate DLB2 bitmap control struct */\n+\tbm = rte_malloc(\"DLB2_PF\",\n+\t\t\tsizeof(struct dlb2_bitmap),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\n+\tif (!bm)\n+\t\treturn -ENOMEM;\n+\n+\t/* Allocate bitmap memory */\n+\talloc_size = rte_bitmap_get_memory_footprint(nbits);\n+\tmem = rte_malloc(\"DLB2_PF_BITMAP\", alloc_size, RTE_CACHE_LINE_SIZE);\n+\tif (!mem) {\n+\t\trte_free(bm);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbm->map = rte_bitmap_init(len, mem, alloc_size);\n+\tif (!bm->map) {\n+\t\trte_free(mem);\n+\t\trte_free(bm);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbm->len = len;\n+\n+\t*bitmap = bm;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_free() - free a previously allocated bitmap data structure\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * This function frees a bitmap that was allocated with dlb2_bitmap_alloc().\n+ */\n+static inline void dlb2_bitmap_free(struct dlb2_bitmap *bitmap)\n+{\n+\tif (!bitmap)\n+\t\treturn;\n+\n+\trte_free(bitmap->map);\n+\trte_free(bitmap);\n+}\n+\n+/**\n+ * dlb2_bitmap_fill() - fill a bitmap with all 1s\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * This function sets all bitmap values to 1.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb2_bitmap_fill(struct dlb2_bitmap *bitmap)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != bitmap->len; i++)\n+\t\trte_bitmap_set(bitmap->map, i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_fill() - fill a bitmap with all 0s\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * This function sets all bitmap values to 0.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb2_bitmap_zero(struct dlb2_bitmap *bitmap)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_reset(bitmap->map);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_set() - set a bitmap entry\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ * @bit: bit index.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the\n+ *\t    bitmap length.\n+ */\n+static inline int dlb2_bitmap_set(struct dlb2_bitmap *bitmap,\n+\t\t\t\t  unsigned int bit)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_set(bitmap->map, bit);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_set_range() - set a range of bitmap entries\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ * @bit: starting bit index.\n+ * @len: length of the range.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the bitmap\n+ *\t    length.\n+ */\n+static inline int dlb2_bitmap_set_range(struct dlb2_bitmap *bitmap,\n+\t\t\t\t\tunsigned int bit,\n+\t\t\t\t\tunsigned int len)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != len; i++)\n+\t\trte_bitmap_set(bitmap->map, bit + i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_clear() - clear a bitmap entry\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ * @bit: bit index.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the\n+ *\t    bitmap length.\n+ */\n+static inline int dlb2_bitmap_clear(struct dlb2_bitmap *bitmap,\n+\t\t\t\t    unsigned int bit)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_clear(bitmap->map, bit);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_clear_range() - clear a range of bitmap entries\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ * @bit: starting bit index.\n+ * @len: length of the range.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the bitmap\n+ *\t    length.\n+ */\n+static inline int dlb2_bitmap_clear_range(struct dlb2_bitmap *bitmap,\n+\t\t\t\t\t  unsigned int bit,\n+\t\t\t\t\t  unsigned int len)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != len; i++)\n+\t\trte_bitmap_clear(bitmap->map, bit + i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_bitmap_find_set_bit_range() - find an range of set bits\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ * @len: length of the range.\n+ *\n+ * This function looks for a range of set bits of length @len.\n+ *\n+ * Return:\n+ * Returns the base bit index upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * ENOENT - unable to find a length *len* range of set bits.\n+ * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.\n+ */\n+static inline int dlb2_bitmap_find_set_bit_range(struct dlb2_bitmap *bitmap,\n+\t\t\t\t\t\t unsigned int len)\n+{\n+\tunsigned int i, j = 0;\n+\n+\tif (!bitmap || !bitmap->map || len == 0)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len < len)\n+\t\treturn -ENOENT;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i)) {\n+\t\t\tif (++j == len)\n+\t\t\t\treturn i - j + 1;\n+\t\t} else {\n+\t\t\tj = 0;\n+\t\t}\n+\t}\n+\n+\t/* No set bit range of length len? */\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * dlb2_bitmap_find_set_bit() - find an range of set bits\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * This function looks for a single set bit.\n+ *\n+ * Return:\n+ * Returns the base bit index upon success, -1 if not found, <-1 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.\n+ */\n+static inline int dlb2_bitmap_find_set_bit(struct dlb2_bitmap *bitmap)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i))\n+\t\t\treturn i;\n+\t}\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * dlb2_bitmap_count() - returns the number of set bits\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * This function looks for a single set bit.\n+ *\n+ * Return:\n+ * Returns the number of set bits upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb2_bitmap_count(struct dlb2_bitmap *bitmap)\n+{\n+\tint weight = 0;\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i))\n+\t\t\tweight++;\n+\t}\n+\treturn weight;\n+}\n+\n+/**\n+ * dlb2_bitmap_longest_set_range() - returns longest contiguous range of set\n+ *\t\t\t\t      bits\n+ * @bitmap: pointer to dlb2_bitmap structure.\n+ *\n+ * Return:\n+ * Returns the bitmap's longest contiguous range of of set bits upon success,\n+ * <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb2_bitmap_longest_set_range(struct dlb2_bitmap *bitmap)\n+{\n+\tint max_len = 0, len = 0;\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\t/* TODO - optimize */\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i)) {\n+\t\t\tlen++;\n+\t\t} else {\n+\t\t\tif (len > max_len)\n+\t\t\t\tmax_len = len;\n+\t\t\tlen = 0;\n+\t\t}\n+\t}\n+\n+\tif (len > max_len)\n+\t\tmax_len = len;\n+\n+\treturn max_len;\n+}\n+\n+/**\n+ * dlb2_bitmap_or() - store the logical 'or' of two bitmaps into a third\n+ * @dest: pointer to dlb2_bitmap structure, which will contain the results of\n+ *\t  the 'or' of src1 and src2.\n+ * @src1: pointer to dlb2_bitmap structure, will be 'or'ed with src2.\n+ * @src2: pointer to dlb2_bitmap structure, will be 'or'ed with src1.\n+ *\n+ * This function 'or's two bitmaps together and stores the result in a third\n+ * bitmap. The source and destination bitmaps can be the same.\n+ *\n+ * Return:\n+ * Returns the number of set bits upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - One of the bitmaps is NULL or is uninitialized.\n+ */\n+static inline int dlb2_bitmap_or(struct dlb2_bitmap *dest,\n+\t\t\t\t struct dlb2_bitmap *src1,\n+\t\t\t\t struct dlb2_bitmap *src2)\n+{\n+\tunsigned int i, min;\n+\tint numset = 0;\n+\n+\tif (!dest || !dest->map ||\n+\t    !src1 || !src1->map ||\n+\t    !src2 || !src2->map)\n+\t\treturn -EINVAL;\n+\n+\tmin = dest->len;\n+\tmin = (min > src1->len) ? src1->len : min;\n+\tmin = (min > src2->len) ? src2->len : min;\n+\n+\tfor (i = 0; i != min; i++) {\n+\t\tif  (rte_bitmap_get(src1->map, i) ||\n+\t\t     rte_bitmap_get(src2->map, i)) {\n+\t\t\trte_bitmap_set(dest->map, i);\n+\t\t\tnumset++;\n+\t\t} else {\n+\t\t\trte_bitmap_clear(dest->map, i);\n+\t\t}\n+\t}\n+\n+\treturn numset;\n+}\n+\n+#endif /*  __DLB2_OSDEP_BITMAP_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_list.h b/drivers/event/dlb2/pf/base/dlb2_osdep_list.h\nnew file mode 100644\nindex 0000000..5531739\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep_list.h\n@@ -0,0 +1,131 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_OSDEP_LIST_H\n+#define __DLB2_OSDEP_LIST_H\n+\n+#include <rte_tailq.h>\n+\n+struct dlb2_list_entry {\n+\tTAILQ_ENTRY(dlb2_list_entry) node;\n+};\n+\n+/* Dummy - just a struct definition */\n+TAILQ_HEAD(dlb2_list_head, dlb2_list_entry);\n+\n+/* =================\n+ * TAILQ Supplements\n+ * =================\n+ */\n+\n+#ifndef TAILQ_FOREACH_ENTRY\n+#define TAILQ_FOREACH_ENTRY(ptr, head, name, iter)\t\t\\\n+\tfor ((iter) = TAILQ_FIRST(&head);\t\t\t\\\n+\t    (iter)\t\t\t\t\t\t\\\n+\t\t&& (ptr = container_of(iter, typeof(*(ptr)), name)); \\\n+\t    (iter) = TAILQ_NEXT((iter), node))\n+#endif\n+\n+#ifndef TAILQ_FOREACH_ENTRY_SAFE\n+#define TAILQ_FOREACH_ENTRY_SAFE(ptr, head, name, iter, tvar)\t\\\n+\tfor ((iter) = TAILQ_FIRST(&head);\t\t\t\\\n+\t    (iter) &&\t\t\t\t\t\t\\\n+\t\t(ptr = container_of(iter, typeof(*(ptr)), name)) &&\\\n+\t\t((tvar) = TAILQ_NEXT((iter), node), 1);\t\\\n+\t    (iter) = (tvar))\n+#endif\n+\n+/***********************/\n+/*** List operations ***/\n+/***********************/\n+\n+/**\n+ * dlb2_list_init_head() - initialize the head of a list\n+ * @head: list head\n+ */\n+static inline void dlb2_list_init_head(struct dlb2_list_head *head)\n+{\n+\tTAILQ_INIT(head);\n+}\n+\n+/**\n+ * dlb2_list_add() - add an entry to a list\n+ * @head: list head\n+ * @entry: new list entry\n+ */\n+static inline void\n+dlb2_list_add(struct dlb2_list_head *head, struct dlb2_list_entry *entry)\n+{\n+\tTAILQ_INSERT_TAIL(head, entry, node);\n+}\n+\n+/**\n+ * dlb2_list_del() - delete an entry from a list\n+ * @entry: list entry\n+ * @head: list head\n+ */\n+static inline void dlb2_list_del(struct dlb2_list_head *head,\n+\t\t\t\t struct dlb2_list_entry *entry)\n+{\n+\tTAILQ_REMOVE(head, entry, node);\n+}\n+\n+/**\n+ * dlb2_list_empty() - check if a list is empty\n+ * @head: list head\n+ *\n+ * Return:\n+ * Returns 1 if empty, 0 if not.\n+ */\n+static inline int dlb2_list_empty(struct dlb2_list_head *head)\n+{\n+\treturn TAILQ_EMPTY(head);\n+}\n+\n+/**\n+ * dlb2_list_splice() - splice a list\n+ * @src_head: list to be added\n+ * @ head: where src_head will be inserted\n+ */\n+static inline void dlb2_list_splice(struct dlb2_list_head *src_head,\n+\t\t\t\t    struct dlb2_list_head *head)\n+{\n+\tTAILQ_CONCAT(head, src_head, node);\n+}\n+\n+/**\n+ * DLB2_LIST_HEAD() - retrieve the head of the list\n+ * @head: list head\n+ * @type: type of the list variable\n+ * @name: name of the list field within the containing struct\n+ */\n+#define DLB2_LIST_HEAD(head, type, name)                       \\\n+\t(TAILQ_FIRST(&head) ?\t\t\t\t\t\\\n+\t\tcontainer_of(TAILQ_FIRST(&head), type, name) :\t\\\n+\t\tNULL)\n+\n+/**\n+ * DLB2_LIST_FOR_EACH() - iterate over a list\n+ * @head: list head\n+ * @ptr: pointer to struct containing a struct list\n+ * @name: name of the list field within the containing struct\n+ * @iter: iterator variable\n+ */\n+#define DLB2_LIST_FOR_EACH(head, ptr, name, tmp_iter) \\\n+\tTAILQ_FOREACH_ENTRY(ptr, head, name, tmp_iter)\n+\n+/**\n+ * DLB2_LIST_FOR_EACH_SAFE() - iterate over a list. This loop works even if\n+ * an element is removed from the list while processing it.\n+ * @ptr: pointer to struct containing a struct list\n+ * @ptr_tmp: pointer to struct containing a struct list (temporary)\n+ * @head: list head\n+ * @name: name of the list field within the containing struct\n+ * @iter: iterator variable\n+ * @iter_tmp: iterator variable (temporary)\n+ */\n+#define DLB2_LIST_FOR_EACH_SAFE(head, ptr, ptr_tmp, name, tmp_iter, saf_itr) \\\n+\tTAILQ_FOREACH_ENTRY_SAFE(ptr, head, name, tmp_iter, saf_itr)\n+\n+#endif /*  __DLB2_OSDEP_LIST_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_types.h b/drivers/event/dlb2/pf/base/dlb2_osdep_types.h\nnew file mode 100644\nindex 0000000..0a48f7e\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep_types.h\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_OSDEP_TYPES_H\n+#define __DLB2_OSDEP_TYPES_H\n+\n+#include <linux/types.h>\n+\n+#include <inttypes.h>\n+#include <ctype.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <errno.h>\n+\n+/* Types for user mode PF PMD */\n+typedef uint8_t         u8;\n+typedef int8_t          s8;\n+typedef uint16_t        u16;\n+typedef int16_t         s16;\n+typedef uint32_t        u32;\n+typedef int32_t         s32;\n+typedef uint64_t        u64;\n+\n+#define __iomem\n+\n+/* END types for user mode PF PMD */\n+\n+#endif /* __DLB2_OSDEP_TYPES_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_regs.h b/drivers/event/dlb2/pf/base/dlb2_regs.h\nnew file mode 100644\nindex 0000000..43ecad4\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_regs.h\n@@ -0,0 +1,2527 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_REGS_H\n+#define __DLB2_REGS_H\n+\n+#include \"dlb2_osdep_types.h\"\n+\n+#define DLB2_FUNC_PF_VF2PF_MAILBOX_BYTES 256\n+#define DLB2_FUNC_PF_VF2PF_MAILBOX(vf_id, x) \\\n+\t(0x1000 + 0x4 * (x) + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_VF2PF_MAILBOX_RST 0x0\n+union dlb2_func_pf_vf2pf_mailbox {\n+\tstruct {\n+\t\tu32 msg : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR(vf_id) \\\n+\t(0x1f00 + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR_RST 0x0\n+union dlb2_func_pf_vf2pf_mailbox_isr {\n+\tstruct {\n+\t\tu32 vf0_isr : 1;\n+\t\tu32 vf1_isr : 1;\n+\t\tu32 vf2_isr : 1;\n+\t\tu32 vf3_isr : 1;\n+\t\tu32 vf4_isr : 1;\n+\t\tu32 vf5_isr : 1;\n+\t\tu32 vf6_isr : 1;\n+\t\tu32 vf7_isr : 1;\n+\t\tu32 vf8_isr : 1;\n+\t\tu32 vf9_isr : 1;\n+\t\tu32 vf10_isr : 1;\n+\t\tu32 vf11_isr : 1;\n+\t\tu32 vf12_isr : 1;\n+\t\tu32 vf13_isr : 1;\n+\t\tu32 vf14_isr : 1;\n+\t\tu32 vf15_isr : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_VF2PF_FLR_ISR(vf_id) \\\n+\t(0x1f04 + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_VF2PF_FLR_ISR_RST 0x0\n+union dlb2_func_pf_vf2pf_flr_isr {\n+\tstruct {\n+\t\tu32 vf0_isr : 1;\n+\t\tu32 vf1_isr : 1;\n+\t\tu32 vf2_isr : 1;\n+\t\tu32 vf3_isr : 1;\n+\t\tu32 vf4_isr : 1;\n+\t\tu32 vf5_isr : 1;\n+\t\tu32 vf6_isr : 1;\n+\t\tu32 vf7_isr : 1;\n+\t\tu32 vf8_isr : 1;\n+\t\tu32 vf9_isr : 1;\n+\t\tu32 vf10_isr : 1;\n+\t\tu32 vf11_isr : 1;\n+\t\tu32 vf12_isr : 1;\n+\t\tu32 vf13_isr : 1;\n+\t\tu32 vf14_isr : 1;\n+\t\tu32 vf15_isr : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_VF2PF_ISR_PEND(vf_id) \\\n+\t(0x1f10 + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_VF2PF_ISR_PEND_RST 0x0\n+union dlb2_func_pf_vf2pf_isr_pend {\n+\tstruct {\n+\t\tu32 isr_pend : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_PF2VF_MAILBOX_BYTES 64\n+#define DLB2_FUNC_PF_PF2VF_MAILBOX(vf_id, x) \\\n+\t(0x2000 + 0x4 * (x) + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_PF2VF_MAILBOX_RST 0x0\n+union dlb2_func_pf_pf2vf_mailbox {\n+\tstruct {\n+\t\tu32 msg : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR(vf_id) \\\n+\t(0x2f00 + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR_RST 0x0\n+union dlb2_func_pf_pf2vf_mailbox_isr {\n+\tstruct {\n+\t\tu32 vf0_isr : 1;\n+\t\tu32 vf1_isr : 1;\n+\t\tu32 vf2_isr : 1;\n+\t\tu32 vf3_isr : 1;\n+\t\tu32 vf4_isr : 1;\n+\t\tu32 vf5_isr : 1;\n+\t\tu32 vf6_isr : 1;\n+\t\tu32 vf7_isr : 1;\n+\t\tu32 vf8_isr : 1;\n+\t\tu32 vf9_isr : 1;\n+\t\tu32 vf10_isr : 1;\n+\t\tu32 vf11_isr : 1;\n+\t\tu32 vf12_isr : 1;\n+\t\tu32 vf13_isr : 1;\n+\t\tu32 vf14_isr : 1;\n+\t\tu32 vf15_isr : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS(vf_id) \\\n+\t(0x3000 + (vf_id) * 0x10000)\n+#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS_RST 0xffff\n+union dlb2_func_pf_vf_reset_in_progress {\n+\tstruct {\n+\t\tu32 vf0_reset_in_progress : 1;\n+\t\tu32 vf1_reset_in_progress : 1;\n+\t\tu32 vf2_reset_in_progress : 1;\n+\t\tu32 vf3_reset_in_progress : 1;\n+\t\tu32 vf4_reset_in_progress : 1;\n+\t\tu32 vf5_reset_in_progress : 1;\n+\t\tu32 vf6_reset_in_progress : 1;\n+\t\tu32 vf7_reset_in_progress : 1;\n+\t\tu32 vf8_reset_in_progress : 1;\n+\t\tu32 vf9_reset_in_progress : 1;\n+\t\tu32 vf10_reset_in_progress : 1;\n+\t\tu32 vf11_reset_in_progress : 1;\n+\t\tu32 vf12_reset_in_progress : 1;\n+\t\tu32 vf13_reset_in_progress : 1;\n+\t\tu32 vf14_reset_in_progress : 1;\n+\t\tu32 vf15_reset_in_progress : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_MSIX_MEM_VECTOR_CTRL(x) \\\n+\t(0x100000c + (x) * 0x10)\n+#define DLB2_MSIX_MEM_VECTOR_CTRL_RST 0x1\n+union dlb2_msix_mem_vector_ctrl {\n+\tstruct {\n+\t\tu32 vec_mask : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL(x) \\\n+\t(0x20 + (x) * 0x4)\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RST 0x0\n+union dlb2_iosf_func_vf_bar_dsbl {\n+\tstruct {\n+\t\tu32 func_vf_bar_dis : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_VAS 0x1000011c\n+#define DLB2_SYS_TOTAL_VAS_RST 0x20\n+union dlb2_sys_total_vas {\n+\tstruct {\n+\t\tu32 total_vas : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_DIR_PORTS 0x10000118\n+#define DLB2_SYS_TOTAL_DIR_PORTS_RST 0x40\n+union dlb2_sys_total_dir_ports {\n+\tstruct {\n+\t\tu32 total_dir_ports : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_LDB_PORTS 0x10000114\n+#define DLB2_SYS_TOTAL_LDB_PORTS_RST 0x40\n+union dlb2_sys_total_ldb_ports {\n+\tstruct {\n+\t\tu32 total_ldb_ports : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_DIR_QID 0x10000110\n+#define DLB2_SYS_TOTAL_DIR_QID_RST 0x40\n+union dlb2_sys_total_dir_qid {\n+\tstruct {\n+\t\tu32 total_dir_qid : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_LDB_QID 0x1000010c\n+#define DLB2_SYS_TOTAL_LDB_QID_RST 0x20\n+union dlb2_sys_total_ldb_qid {\n+\tstruct {\n+\t\tu32 total_ldb_qid : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_DIR_CRDS 0x10000108\n+#define DLB2_SYS_TOTAL_DIR_CRDS_RST 0x1000\n+union dlb2_sys_total_dir_crds {\n+\tstruct {\n+\t\tu32 total_dir_credits : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_TOTAL_LDB_CRDS 0x10000104\n+#define DLB2_SYS_TOTAL_LDB_CRDS_RST 0x2000\n+union dlb2_sys_total_ldb_crds {\n+\tstruct {\n+\t\tu32 total_ldb_credits : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_PF_SYND2 0x10000508\n+#define DLB2_SYS_ALARM_PF_SYND2_RST 0x0\n+union dlb2_sys_alarm_pf_synd2 {\n+\tstruct {\n+\t\tu32 lock_id : 16;\n+\t\tu32 meas : 1;\n+\t\tu32 debug : 7;\n+\t\tu32 cq_pop : 1;\n+\t\tu32 qe_uhl : 1;\n+\t\tu32 qe_orsp : 1;\n+\t\tu32 qe_valid : 1;\n+\t\tu32 cq_int_rearm : 1;\n+\t\tu32 dsi_error : 1;\n+\t\tu32 rsvd0 : 2;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_PF_SYND1 0x10000504\n+#define DLB2_SYS_ALARM_PF_SYND1_RST 0x0\n+union dlb2_sys_alarm_pf_synd1 {\n+\tstruct {\n+\t\tu32 dsi : 16;\n+\t\tu32 qid : 8;\n+\t\tu32 qtype : 2;\n+\t\tu32 qpri : 3;\n+\t\tu32 msg_type : 3;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_PF_SYND0 0x10000500\n+#define DLB2_SYS_ALARM_PF_SYND0_RST 0x0\n+union dlb2_sys_alarm_pf_synd0 {\n+\tstruct {\n+\t\tu32 syndrome : 8;\n+\t\tu32 rtype : 2;\n+\t\tu32 rsvd0 : 3;\n+\t\tu32 is_ldb : 1;\n+\t\tu32 cls : 2;\n+\t\tu32 aid : 6;\n+\t\tu32 unit : 4;\n+\t\tu32 source : 4;\n+\t\tu32 more : 1;\n+\t\tu32 valid : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_LDB_VPP_V(x) \\\n+\t(0x10000f00 + (x) * 0x1000)\n+#define DLB2_SYS_VF_LDB_VPP_V_RST 0x0\n+union dlb2_sys_vf_ldb_vpp_v {\n+\tstruct {\n+\t\tu32 vpp_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_LDB_VPP2PP(x) \\\n+\t(0x10000f04 + (x) * 0x1000)\n+#define DLB2_SYS_VF_LDB_VPP2PP_RST 0x0\n+union dlb2_sys_vf_ldb_vpp2pp {\n+\tstruct {\n+\t\tu32 pp : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_DIR_VPP_V(x) \\\n+\t(0x10000f08 + (x) * 0x1000)\n+#define DLB2_SYS_VF_DIR_VPP_V_RST 0x0\n+union dlb2_sys_vf_dir_vpp_v {\n+\tstruct {\n+\t\tu32 vpp_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_DIR_VPP2PP(x) \\\n+\t(0x10000f0c + (x) * 0x1000)\n+#define DLB2_SYS_VF_DIR_VPP2PP_RST 0x0\n+union dlb2_sys_vf_dir_vpp2pp {\n+\tstruct {\n+\t\tu32 pp : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_LDB_VQID_V(x) \\\n+\t(0x10000f10 + (x) * 0x1000)\n+#define DLB2_SYS_VF_LDB_VQID_V_RST 0x0\n+union dlb2_sys_vf_ldb_vqid_v {\n+\tstruct {\n+\t\tu32 vqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_LDB_VQID2QID(x) \\\n+\t(0x10000f14 + (x) * 0x1000)\n+#define DLB2_SYS_VF_LDB_VQID2QID_RST 0x0\n+union dlb2_sys_vf_ldb_vqid2qid {\n+\tstruct {\n+\t\tu32 qid : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_QID2VQID(x) \\\n+\t(0x10000f18 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_QID2VQID_RST 0x0\n+union dlb2_sys_ldb_qid2vqid {\n+\tstruct {\n+\t\tu32 vqid : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_DIR_VQID_V(x) \\\n+\t(0x10000f1c + (x) * 0x1000)\n+#define DLB2_SYS_VF_DIR_VQID_V_RST 0x0\n+union dlb2_sys_vf_dir_vqid_v {\n+\tstruct {\n+\t\tu32 vqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_VF_DIR_VQID2QID(x) \\\n+\t(0x10000f20 + (x) * 0x1000)\n+#define DLB2_SYS_VF_DIR_VQID2QID_RST 0x0\n+union dlb2_sys_vf_dir_vqid2qid {\n+\tstruct {\n+\t\tu32 qid : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_VASQID_V(x) \\\n+\t(0x10000f24 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_VASQID_V_RST 0x0\n+union dlb2_sys_ldb_vasqid_v {\n+\tstruct {\n+\t\tu32 vasqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_VASQID_V(x) \\\n+\t(0x10000f28 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_VASQID_V_RST 0x0\n+union dlb2_sys_dir_vasqid_v {\n+\tstruct {\n+\t\tu32 vasqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_VF_SYND2(x) \\\n+\t(0x10000f48 + (x) * 0x1000)\n+#define DLB2_SYS_ALARM_VF_SYND2_RST 0x0\n+union dlb2_sys_alarm_vf_synd2 {\n+\tstruct {\n+\t\tu32 lock_id : 16;\n+\t\tu32 debug : 8;\n+\t\tu32 cq_pop : 1;\n+\t\tu32 qe_uhl : 1;\n+\t\tu32 qe_orsp : 1;\n+\t\tu32 qe_valid : 1;\n+\t\tu32 isz : 1;\n+\t\tu32 dsi_error : 1;\n+\t\tu32 dlbrsvd : 2;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_VF_SYND1(x) \\\n+\t(0x10000f44 + (x) * 0x1000)\n+#define DLB2_SYS_ALARM_VF_SYND1_RST 0x0\n+union dlb2_sys_alarm_vf_synd1 {\n+\tstruct {\n+\t\tu32 dsi : 16;\n+\t\tu32 qid : 8;\n+\t\tu32 qtype : 2;\n+\t\tu32 qpri : 3;\n+\t\tu32 msg_type : 3;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_VF_SYND0(x) \\\n+\t(0x10000f40 + (x) * 0x1000)\n+#define DLB2_SYS_ALARM_VF_SYND0_RST 0x0\n+union dlb2_sys_alarm_vf_synd0 {\n+\tstruct {\n+\t\tu32 syndrome : 8;\n+\t\tu32 rtype : 2;\n+\t\tu32 vf_synd0_parity : 1;\n+\t\tu32 vf_synd1_parity : 1;\n+\t\tu32 vf_synd2_parity : 1;\n+\t\tu32 is_ldb : 1;\n+\t\tu32 cls : 2;\n+\t\tu32 aid : 6;\n+\t\tu32 unit : 4;\n+\t\tu32 source : 4;\n+\t\tu32 more : 1;\n+\t\tu32 valid : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_QID_CFG_V(x) \\\n+\t(0x10000f58 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_QID_CFG_V_RST 0x0\n+union dlb2_sys_ldb_qid_cfg_v {\n+\tstruct {\n+\t\tu32 sn_cfg_v : 1;\n+\t\tu32 fid_cfg_v : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_QID_ITS(x) \\\n+\t(0x10000f54 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_QID_ITS_RST 0x0\n+union dlb2_sys_ldb_qid_its {\n+\tstruct {\n+\t\tu32 qid_its : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_QID_V(x) \\\n+\t(0x10000f50 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_QID_V_RST 0x0\n+union dlb2_sys_ldb_qid_v {\n+\tstruct {\n+\t\tu32 qid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_QID_ITS(x) \\\n+\t(0x10000f64 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_QID_ITS_RST 0x0\n+union dlb2_sys_dir_qid_its {\n+\tstruct {\n+\t\tu32 qid_its : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_QID_V(x) \\\n+\t(0x10000f60 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_QID_V_RST 0x0\n+union dlb2_sys_dir_qid_v {\n+\tstruct {\n+\t\tu32 qid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_AI_DATA(x) \\\n+\t(0x10000fa8 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_AI_DATA_RST 0x0\n+union dlb2_sys_ldb_cq_ai_data {\n+\tstruct {\n+\t\tu32 cq_ai_data : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR(x) \\\n+\t(0x10000fa4 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_RST 0x0\n+union dlb2_sys_ldb_cq_ai_addr {\n+\tstruct {\n+\t\tu32 rsvd1 : 2;\n+\t\tu32 cq_ai_addr : 18;\n+\t\tu32 rsvd0 : 12;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_PASID(x) \\\n+\t(0x10000fa0 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_PASID_RST 0x0\n+union dlb2_sys_ldb_cq_pasid {\n+\tstruct {\n+\t\tu32 pasid : 20;\n+\t\tu32 exe_req : 1;\n+\t\tu32 priv_req : 1;\n+\t\tu32 fmt2 : 1;\n+\t\tu32 rsvd0 : 9;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_AT(x) \\\n+\t(0x10000f9c + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_AT_RST 0x0\n+union dlb2_sys_ldb_cq_at {\n+\tstruct {\n+\t\tu32 cq_at : 2;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_ISR(x) \\\n+\t(0x10000f98 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_ISR_RST 0x0\n+/* CQ Interrupt Modes */\n+#define DLB2_CQ_ISR_MODE_DIS  0\n+#define DLB2_CQ_ISR_MODE_MSI  1\n+#define DLB2_CQ_ISR_MODE_MSIX 2\n+#define DLB2_CQ_ISR_MODE_ADI  3\n+union dlb2_sys_ldb_cq_isr {\n+\tstruct {\n+\t\tu32 vector : 6;\n+\t\tu32 vf : 4;\n+\t\tu32 en_code : 2;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO(x) \\\n+\t(0x10000f94 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_RST 0x0\n+union dlb2_sys_ldb_cq2vf_pf_ro {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 ro : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_PP_V(x) \\\n+\t(0x10000f90 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_PP_V_RST 0x0\n+union dlb2_sys_ldb_pp_v {\n+\tstruct {\n+\t\tu32 pp_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_PP2VDEV(x) \\\n+\t(0x10000f8c + (x) * 0x1000)\n+#define DLB2_SYS_LDB_PP2VDEV_RST 0x0\n+union dlb2_sys_ldb_pp2vdev {\n+\tstruct {\n+\t\tu32 vdev : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_PP2VAS(x) \\\n+\t(0x10000f88 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_PP2VAS_RST 0x0\n+union dlb2_sys_ldb_pp2vas {\n+\tstruct {\n+\t\tu32 vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_ADDR_U(x) \\\n+\t(0x10000f84 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_ADDR_U_RST 0x0\n+union dlb2_sys_ldb_cq_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_ADDR_L(x) \\\n+\t(0x10000f80 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_ADDR_L_RST 0x0\n+union dlb2_sys_ldb_cq_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 6;\n+\t\tu32 addr_l : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_FMT(x) \\\n+\t(0x10000fec + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_FMT_RST 0x0\n+union dlb2_sys_dir_cq_fmt {\n+\tstruct {\n+\t\tu32 keep_pf_ppid : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_AI_DATA(x) \\\n+\t(0x10000fe8 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_AI_DATA_RST 0x0\n+union dlb2_sys_dir_cq_ai_data {\n+\tstruct {\n+\t\tu32 cq_ai_data : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR(x) \\\n+\t(0x10000fe4 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_RST 0x0\n+union dlb2_sys_dir_cq_ai_addr {\n+\tstruct {\n+\t\tu32 rsvd1 : 2;\n+\t\tu32 cq_ai_addr : 18;\n+\t\tu32 rsvd0 : 12;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_PASID(x) \\\n+\t(0x10000fe0 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_PASID_RST 0x0\n+union dlb2_sys_dir_cq_pasid {\n+\tstruct {\n+\t\tu32 pasid : 20;\n+\t\tu32 exe_req : 1;\n+\t\tu32 priv_req : 1;\n+\t\tu32 fmt2 : 1;\n+\t\tu32 rsvd0 : 9;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_AT(x) \\\n+\t(0x10000fdc + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_AT_RST 0x0\n+union dlb2_sys_dir_cq_at {\n+\tstruct {\n+\t\tu32 cq_at : 2;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_ISR(x) \\\n+\t(0x10000fd8 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_ISR_RST 0x0\n+union dlb2_sys_dir_cq_isr {\n+\tstruct {\n+\t\tu32 vector : 6;\n+\t\tu32 vf : 4;\n+\t\tu32 en_code : 2;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO(x) \\\n+\t(0x10000fd4 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_RST 0x0\n+union dlb2_sys_dir_cq2vf_pf_ro {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 ro : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_PP_V(x) \\\n+\t(0x10000fd0 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_PP_V_RST 0x0\n+union dlb2_sys_dir_pp_v {\n+\tstruct {\n+\t\tu32 pp_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_PP2VDEV(x) \\\n+\t(0x10000fcc + (x) * 0x1000)\n+#define DLB2_SYS_DIR_PP2VDEV_RST 0x0\n+union dlb2_sys_dir_pp2vdev {\n+\tstruct {\n+\t\tu32 vdev : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_PP2VAS(x) \\\n+\t(0x10000fc8 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_PP2VAS_RST 0x0\n+union dlb2_sys_dir_pp2vas {\n+\tstruct {\n+\t\tu32 vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_ADDR_U(x) \\\n+\t(0x10000fc4 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_ADDR_U_RST 0x0\n+union dlb2_sys_dir_cq_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_ADDR_L(x) \\\n+\t(0x10000fc0 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_ADDR_L_RST 0x0\n+union dlb2_sys_dir_cq_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 6;\n+\t\tu32 addr_l : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_INGRESS_ALARM_ENBL 0x10000300\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_RST 0x0\n+union dlb2_sys_ingress_alarm_enbl {\n+\tstruct {\n+\t\tu32 illegal_hcw : 1;\n+\t\tu32 illegal_pp : 1;\n+\t\tu32 illegal_pasid : 1;\n+\t\tu32 illegal_qid : 1;\n+\t\tu32 disabled_qid : 1;\n+\t\tu32 illegal_ldb_qid_cfg : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_MSIX_ACK 0x10000400\n+#define DLB2_SYS_MSIX_ACK_RST 0x0\n+union dlb2_sys_msix_ack {\n+\tstruct {\n+\t\tu32 msix_0_ack : 1;\n+\t\tu32 msix_1_ack : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_MSIX_PASSTHRU 0x10000404\n+#define DLB2_SYS_MSIX_PASSTHRU_RST 0x0\n+union dlb2_sys_msix_passthru {\n+\tstruct {\n+\t\tu32 msix_0_passthru : 1;\n+\t\tu32 msix_1_passthru : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_MSIX_MODE 0x10000408\n+#define DLB2_SYS_MSIX_MODE_RST 0x0\n+/* MSI-X Modes */\n+#define DLB2_MSIX_MODE_PACKED     0\n+#define DLB2_MSIX_MODE_COMPRESSED 1\n+union dlb2_sys_msix_mode {\n+\tstruct {\n+\t\tu32 mode : 1;\n+\t\tu32 poll_mode : 1;\n+\t\tu32 poll_mask : 1;\n+\t\tu32 poll_lock : 1;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS 0x10000440\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0\n+union dlb2_sys_dir_cq_31_0_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_0_occ_int : 1;\n+\t\tu32 cq_1_occ_int : 1;\n+\t\tu32 cq_2_occ_int : 1;\n+\t\tu32 cq_3_occ_int : 1;\n+\t\tu32 cq_4_occ_int : 1;\n+\t\tu32 cq_5_occ_int : 1;\n+\t\tu32 cq_6_occ_int : 1;\n+\t\tu32 cq_7_occ_int : 1;\n+\t\tu32 cq_8_occ_int : 1;\n+\t\tu32 cq_9_occ_int : 1;\n+\t\tu32 cq_10_occ_int : 1;\n+\t\tu32 cq_11_occ_int : 1;\n+\t\tu32 cq_12_occ_int : 1;\n+\t\tu32 cq_13_occ_int : 1;\n+\t\tu32 cq_14_occ_int : 1;\n+\t\tu32 cq_15_occ_int : 1;\n+\t\tu32 cq_16_occ_int : 1;\n+\t\tu32 cq_17_occ_int : 1;\n+\t\tu32 cq_18_occ_int : 1;\n+\t\tu32 cq_19_occ_int : 1;\n+\t\tu32 cq_20_occ_int : 1;\n+\t\tu32 cq_21_occ_int : 1;\n+\t\tu32 cq_22_occ_int : 1;\n+\t\tu32 cq_23_occ_int : 1;\n+\t\tu32 cq_24_occ_int : 1;\n+\t\tu32 cq_25_occ_int : 1;\n+\t\tu32 cq_26_occ_int : 1;\n+\t\tu32 cq_27_occ_int : 1;\n+\t\tu32 cq_28_occ_int : 1;\n+\t\tu32 cq_29_occ_int : 1;\n+\t\tu32 cq_30_occ_int : 1;\n+\t\tu32 cq_31_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS 0x10000444\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0\n+union dlb2_sys_dir_cq_63_32_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_32_occ_int : 1;\n+\t\tu32 cq_33_occ_int : 1;\n+\t\tu32 cq_34_occ_int : 1;\n+\t\tu32 cq_35_occ_int : 1;\n+\t\tu32 cq_36_occ_int : 1;\n+\t\tu32 cq_37_occ_int : 1;\n+\t\tu32 cq_38_occ_int : 1;\n+\t\tu32 cq_39_occ_int : 1;\n+\t\tu32 cq_40_occ_int : 1;\n+\t\tu32 cq_41_occ_int : 1;\n+\t\tu32 cq_42_occ_int : 1;\n+\t\tu32 cq_43_occ_int : 1;\n+\t\tu32 cq_44_occ_int : 1;\n+\t\tu32 cq_45_occ_int : 1;\n+\t\tu32 cq_46_occ_int : 1;\n+\t\tu32 cq_47_occ_int : 1;\n+\t\tu32 cq_48_occ_int : 1;\n+\t\tu32 cq_49_occ_int : 1;\n+\t\tu32 cq_50_occ_int : 1;\n+\t\tu32 cq_51_occ_int : 1;\n+\t\tu32 cq_52_occ_int : 1;\n+\t\tu32 cq_53_occ_int : 1;\n+\t\tu32 cq_54_occ_int : 1;\n+\t\tu32 cq_55_occ_int : 1;\n+\t\tu32 cq_56_occ_int : 1;\n+\t\tu32 cq_57_occ_int : 1;\n+\t\tu32 cq_58_occ_int : 1;\n+\t\tu32 cq_59_occ_int : 1;\n+\t\tu32 cq_60_occ_int : 1;\n+\t\tu32 cq_61_occ_int : 1;\n+\t\tu32 cq_62_occ_int : 1;\n+\t\tu32 cq_63_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS 0x10000460\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0\n+union dlb2_sys_ldb_cq_31_0_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_0_occ_int : 1;\n+\t\tu32 cq_1_occ_int : 1;\n+\t\tu32 cq_2_occ_int : 1;\n+\t\tu32 cq_3_occ_int : 1;\n+\t\tu32 cq_4_occ_int : 1;\n+\t\tu32 cq_5_occ_int : 1;\n+\t\tu32 cq_6_occ_int : 1;\n+\t\tu32 cq_7_occ_int : 1;\n+\t\tu32 cq_8_occ_int : 1;\n+\t\tu32 cq_9_occ_int : 1;\n+\t\tu32 cq_10_occ_int : 1;\n+\t\tu32 cq_11_occ_int : 1;\n+\t\tu32 cq_12_occ_int : 1;\n+\t\tu32 cq_13_occ_int : 1;\n+\t\tu32 cq_14_occ_int : 1;\n+\t\tu32 cq_15_occ_int : 1;\n+\t\tu32 cq_16_occ_int : 1;\n+\t\tu32 cq_17_occ_int : 1;\n+\t\tu32 cq_18_occ_int : 1;\n+\t\tu32 cq_19_occ_int : 1;\n+\t\tu32 cq_20_occ_int : 1;\n+\t\tu32 cq_21_occ_int : 1;\n+\t\tu32 cq_22_occ_int : 1;\n+\t\tu32 cq_23_occ_int : 1;\n+\t\tu32 cq_24_occ_int : 1;\n+\t\tu32 cq_25_occ_int : 1;\n+\t\tu32 cq_26_occ_int : 1;\n+\t\tu32 cq_27_occ_int : 1;\n+\t\tu32 cq_28_occ_int : 1;\n+\t\tu32 cq_29_occ_int : 1;\n+\t\tu32 cq_30_occ_int : 1;\n+\t\tu32 cq_31_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS 0x10000464\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0\n+union dlb2_sys_ldb_cq_63_32_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_32_occ_int : 1;\n+\t\tu32 cq_33_occ_int : 1;\n+\t\tu32 cq_34_occ_int : 1;\n+\t\tu32 cq_35_occ_int : 1;\n+\t\tu32 cq_36_occ_int : 1;\n+\t\tu32 cq_37_occ_int : 1;\n+\t\tu32 cq_38_occ_int : 1;\n+\t\tu32 cq_39_occ_int : 1;\n+\t\tu32 cq_40_occ_int : 1;\n+\t\tu32 cq_41_occ_int : 1;\n+\t\tu32 cq_42_occ_int : 1;\n+\t\tu32 cq_43_occ_int : 1;\n+\t\tu32 cq_44_occ_int : 1;\n+\t\tu32 cq_45_occ_int : 1;\n+\t\tu32 cq_46_occ_int : 1;\n+\t\tu32 cq_47_occ_int : 1;\n+\t\tu32 cq_48_occ_int : 1;\n+\t\tu32 cq_49_occ_int : 1;\n+\t\tu32 cq_50_occ_int : 1;\n+\t\tu32 cq_51_occ_int : 1;\n+\t\tu32 cq_52_occ_int : 1;\n+\t\tu32 cq_53_occ_int : 1;\n+\t\tu32 cq_54_occ_int : 1;\n+\t\tu32 cq_55_occ_int : 1;\n+\t\tu32 cq_56_occ_int : 1;\n+\t\tu32 cq_57_occ_int : 1;\n+\t\tu32 cq_58_occ_int : 1;\n+\t\tu32 cq_59_occ_int : 1;\n+\t\tu32 cq_60_occ_int : 1;\n+\t\tu32 cq_61_occ_int : 1;\n+\t\tu32 cq_62_occ_int : 1;\n+\t\tu32 cq_63_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_DIR_CQ_OPT_CLR 0x100004c0\n+#define DLB2_SYS_DIR_CQ_OPT_CLR_RST 0x0\n+union dlb2_sys_dir_cq_opt_clr {\n+\tstruct {\n+\t\tu32 cq : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_SYS_ALARM_HW_SYND 0x1000050c\n+#define DLB2_SYS_ALARM_HW_SYND_RST 0x0\n+union dlb2_sys_alarm_hw_synd {\n+\tstruct {\n+\t\tu32 syndrome : 8;\n+\t\tu32 rtype : 2;\n+\t\tu32 alarm : 1;\n+\t\tu32 cwd : 1;\n+\t\tu32 vf_pf_mb : 1;\n+\t\tu32 rsvd0 : 1;\n+\t\tu32 cls : 2;\n+\t\tu32 aid : 6;\n+\t\tu32 unit : 4;\n+\t\tu32 source : 4;\n+\t\tu32 more : 1;\n+\t\tu32 valid : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_AQED_PIPE_QID_FID_LIM(x) \\\n+\t(0x20000000 + (x) * 0x1000)\n+#define DLB2_AQED_PIPE_QID_FID_LIM_RST 0x7ff\n+union dlb2_aqed_pipe_qid_fid_lim {\n+\tstruct {\n+\t\tu32 qid_fid_limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_AQED_PIPE_QID_HID_WIDTH(x) \\\n+\t(0x20080000 + (x) * 0x1000)\n+#define DLB2_AQED_PIPE_QID_HID_WIDTH_RST 0x0\n+union dlb2_aqed_pipe_qid_hid_width {\n+\tstruct {\n+\t\tu32 compress_code : 3;\n+\t\tu32 rsvd0 : 29;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004\n+#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8\n+union dlb2_aqed_pipe_cfg_arb_weights_tqpri_atm_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_ATM_QID2CQIDIX_00(x) \\\n+\t(0x30080000 + (x) * 0x1000)\n+#define DLB2_ATM_QID2CQIDIX_00_RST 0x0\n+#define DLB2_ATM_QID2CQIDIX(x, y) \\\n+\t(DLB2_ATM_QID2CQIDIX_00(x) + 0x80000 * (y))\n+#define DLB2_ATM_QID2CQIDIX_NUM 16\n+union dlb2_atm_qid2cqidix_00 {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN 0x34000004\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc\n+union dlb2_atm_cfg_arb_weights_rdy_bin {\n+\tstruct {\n+\t\tu32 bin0 : 8;\n+\t\tu32 bin1 : 8;\n+\t\tu32 bin2 : 8;\n+\t\tu32 bin3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN 0x34000008\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc\n+union dlb2_atm_cfg_arb_weights_sched_bin {\n+\tstruct {\n+\t\tu32 bin0 : 8;\n+\t\tu32 bin1 : 8;\n+\t\tu32 bin2 : 8;\n+\t\tu32 bin3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_VAS_CRD(x) \\\n+\t(0x40000000 + (x) * 0x1000)\n+#define DLB2_CHP_CFG_DIR_VAS_CRD_RST 0x0\n+union dlb2_chp_cfg_dir_vas_crd {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_VAS_CRD(x) \\\n+\t(0x40080000 + (x) * 0x1000)\n+#define DLB2_CHP_CFG_LDB_VAS_CRD_RST 0x0\n+union dlb2_chp_cfg_ldb_vas_crd {\n+\tstruct {\n+\t\tu32 count : 15;\n+\t\tu32 rsvd0 : 17;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_ORD_QID_SN(x) \\\n+\t(0x40100000 + (x) * 0x1000)\n+#define DLB2_CHP_ORD_QID_SN_RST 0x0\n+union dlb2_chp_ord_qid_sn {\n+\tstruct {\n+\t\tu32 sn : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_ORD_QID_SN_MAP(x) \\\n+\t(0x40180000 + (x) * 0x1000)\n+#define DLB2_CHP_ORD_QID_SN_MAP_RST 0x0\n+union dlb2_chp_ord_qid_sn_map {\n+\tstruct {\n+\t\tu32 mode : 3;\n+\t\tu32 slot : 4;\n+\t\tu32 rsvz0 : 1;\n+\t\tu32 grp : 1;\n+\t\tu32 rsvz1 : 1;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_SN_CHK_ENBL(x) \\\n+\t(0x40200000 + (x) * 0x1000)\n+#define DLB2_CHP_SN_CHK_ENBL_RST 0x0\n+union dlb2_chp_sn_chk_enbl {\n+\tstruct {\n+\t\tu32 en : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_DEPTH(x) \\\n+\t(0x40280000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_DEPTH_RST 0x0\n+union dlb2_chp_dir_cq_depth {\n+\tstruct {\n+\t\tu32 depth : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0x40300000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0\n+union dlb2_chp_dir_cq_int_depth_thrsh {\n+\tstruct {\n+\t\tu32 depth_threshold : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_INT_ENB(x) \\\n+\t(0x40380000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_INT_ENB_RST 0x0\n+union dlb2_chp_dir_cq_int_enb {\n+\tstruct {\n+\t\tu32 en_tim : 1;\n+\t\tu32 en_depth : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH(x) \\\n+\t(0x40480000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_RST 0x1\n+union dlb2_chp_dir_cq_tmr_thrsh {\n+\tstruct {\n+\t\tu32 thrsh_0 : 1;\n+\t\tu32 thrsh_13_1 : 13;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0x40500000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0\n+union dlb2_chp_dir_cq_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_WD_ENB(x) \\\n+\t(0x40580000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_WD_ENB_RST 0x0\n+union dlb2_chp_dir_cq_wd_enb {\n+\tstruct {\n+\t\tu32 wd_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_WPTR(x) \\\n+\t(0x40600000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_WPTR_RST 0x0\n+union dlb2_chp_dir_cq_wptr {\n+\tstruct {\n+\t\tu32 write_pointer : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ2VAS(x) \\\n+\t(0x40680000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ2VAS_RST 0x0\n+union dlb2_chp_dir_cq2vas {\n+\tstruct {\n+\t\tu32 cq2vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_HIST_LIST_BASE(x) \\\n+\t(0x40700000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_BASE_RST 0x0\n+union dlb2_chp_hist_list_base {\n+\tstruct {\n+\t\tu32 base : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_HIST_LIST_LIM(x) \\\n+\t(0x40780000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_LIM_RST 0x0\n+union dlb2_chp_hist_list_lim {\n+\tstruct {\n+\t\tu32 limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_HIST_LIST_POP_PTR(x) \\\n+\t(0x40800000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_POP_PTR_RST 0x0\n+union dlb2_chp_hist_list_pop_ptr {\n+\tstruct {\n+\t\tu32 pop_ptr : 13;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR(x) \\\n+\t(0x40880000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_RST 0x0\n+union dlb2_chp_hist_list_push_ptr {\n+\tstruct {\n+\t\tu32 push_ptr : 13;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_DEPTH(x) \\\n+\t(0x40900000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_DEPTH_RST 0x0\n+union dlb2_chp_ldb_cq_depth {\n+\tstruct {\n+\t\tu32 depth : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0x40980000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0\n+union dlb2_chp_ldb_cq_int_depth_thrsh {\n+\tstruct {\n+\t\tu32 depth_threshold : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_INT_ENB(x) \\\n+\t(0x40a00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_INT_ENB_RST 0x0\n+union dlb2_chp_ldb_cq_int_enb {\n+\tstruct {\n+\t\tu32 en_tim : 1;\n+\t\tu32 en_depth : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH(x) \\\n+\t(0x40b00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_RST 0x1\n+union dlb2_chp_ldb_cq_tmr_thrsh {\n+\tstruct {\n+\t\tu32 thrsh_0 : 1;\n+\t\tu32 thrsh_13_1 : 13;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0x40b80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0\n+union dlb2_chp_ldb_cq_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_WD_ENB(x) \\\n+\t(0x40c00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_WD_ENB_RST 0x0\n+union dlb2_chp_ldb_cq_wd_enb {\n+\tstruct {\n+\t\tu32 wd_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_WPTR(x) \\\n+\t(0x40c80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_WPTR_RST 0x0\n+union dlb2_chp_ldb_cq_wptr {\n+\tstruct {\n+\t\tu32 write_pointer : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ2VAS(x) \\\n+\t(0x40d00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ2VAS_RST 0x0\n+union dlb2_chp_ldb_cq2vas {\n+\tstruct {\n+\t\tu32 cq2vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_RST 0x180002\n+union dlb2_chp_cfg_chp_csr_ctrl {\n+\tstruct {\n+\t\tu32 int_cor_alarm_dis : 1;\n+\t\tu32 int_cor_synd_dis : 1;\n+\t\tu32 int_uncr_alarm_dis : 1;\n+\t\tu32 int_unc_synd_dis : 1;\n+\t\tu32 int_inf0_alarm_dis : 1;\n+\t\tu32 int_inf0_synd_dis : 1;\n+\t\tu32 int_inf1_alarm_dis : 1;\n+\t\tu32 int_inf1_synd_dis : 1;\n+\t\tu32 int_inf2_alarm_dis : 1;\n+\t\tu32 int_inf2_synd_dis : 1;\n+\t\tu32 int_inf3_alarm_dis : 1;\n+\t\tu32 int_inf3_synd_dis : 1;\n+\t\tu32 int_inf4_alarm_dis : 1;\n+\t\tu32 int_inf4_synd_dis : 1;\n+\t\tu32 int_inf5_alarm_dis : 1;\n+\t\tu32 int_inf5_synd_dis : 1;\n+\t\tu32 dlb_cor_alarm_enable : 1;\n+\t\tu32 cfg_64bytes_qe_ldb_cq_mode : 1;\n+\t\tu32 cfg_64bytes_qe_dir_cq_mode : 1;\n+\t\tu32 pad_write_ldb : 1;\n+\t\tu32 pad_write_dir : 1;\n+\t\tu32 pad_first_write_ldb : 1;\n+\t\tu32 pad_first_write_dir : 1;\n+\t\tu32 rsvz0 : 9;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED0 0x4400005c\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED0_RST 0x0\n+union dlb2_chp_dir_cq_intr_armed0 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED1 0x44000060\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED1_RST 0x0\n+union dlb2_chp_dir_cq_intr_armed1 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RST 0x0\n+union dlb2_chp_cfg_dir_cq_timer_ctl {\n+\tstruct {\n+\t\tu32 sample_interval : 8;\n+\t\tu32 enb : 1;\n+\t\tu32 rsvz0 : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WDTO_0 0x44000088\n+#define DLB2_CHP_CFG_DIR_WDTO_0_RST 0x0\n+union dlb2_chp_cfg_dir_wdto_0 {\n+\tstruct {\n+\t\tu32 wdto : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WDTO_1 0x4400008c\n+#define DLB2_CHP_CFG_DIR_WDTO_1_RST 0x0\n+union dlb2_chp_cfg_dir_wdto_1 {\n+\tstruct {\n+\t\tu32 wdto : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE0 0x44000098\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE0_RST 0xffffffff\n+union dlb2_chp_cfg_dir_wd_disable0 {\n+\tstruct {\n+\t\tu32 wd_disable : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE1 0x4400009c\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE1_RST 0xffffffff\n+union dlb2_chp_cfg_dir_wd_disable1 {\n+\tstruct {\n+\t\tu32 wd_disable : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RST 0x0\n+union dlb2_chp_cfg_dir_wd_enb_interval {\n+\tstruct {\n+\t\tu32 sample_interval : 28;\n+\t\tu32 enb : 1;\n+\t\tu32 rsvz0 : 3;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD 0x440000ac\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RST 0x0\n+union dlb2_chp_cfg_dir_wd_threshold {\n+\tstruct {\n+\t\tu32 wd_threshold : 8;\n+\t\tu32 rsvz0 : 24;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED0 0x440000b0\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED0_RST 0x0\n+union dlb2_chp_ldb_cq_intr_armed0 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED1 0x440000b4\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED1_RST 0x0\n+union dlb2_chp_ldb_cq_intr_armed1 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RST 0x0\n+union dlb2_chp_cfg_ldb_cq_timer_ctl {\n+\tstruct {\n+\t\tu32 sample_interval : 8;\n+\t\tu32 enb : 1;\n+\t\tu32 rsvz0 : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WDTO_0 0x440000dc\n+#define DLB2_CHP_CFG_LDB_WDTO_0_RST 0x0\n+union dlb2_chp_cfg_ldb_wdto_0 {\n+\tstruct {\n+\t\tu32 wdto : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WDTO_1 0x440000e0\n+#define DLB2_CHP_CFG_LDB_WDTO_1_RST 0x0\n+union dlb2_chp_cfg_ldb_wdto_1 {\n+\tstruct {\n+\t\tu32 wdto : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE0 0x440000ec\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE0_RST 0xffffffff\n+union dlb2_chp_cfg_ldb_wd_disable0 {\n+\tstruct {\n+\t\tu32 wd_disable : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE1 0x440000f0\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE1_RST 0xffffffff\n+union dlb2_chp_cfg_ldb_wd_disable1 {\n+\tstruct {\n+\t\tu32 wd_disable : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RST 0x0\n+union dlb2_chp_cfg_ldb_wd_enb_interval {\n+\tstruct {\n+\t\tu32 sample_interval : 28;\n+\t\tu32 enb : 1;\n+\t\tu32 rsvz0 : 3;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD 0x44000100\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RST 0x0\n+union dlb2_chp_cfg_ldb_wd_threshold {\n+\tstruct {\n+\t\tu32 wd_threshold : 8;\n+\t\tu32 rsvz0 : 24;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CHP_CTRL_DIAG_02 0x4c000028\n+#define DLB2_CHP_CTRL_DIAG_02_RST 0x1555\n+union dlb2_chp_ctrl_diag_02 {\n+\tstruct {\n+\t\tu32 egress_credit_status_empty : 1;\n+\t\tu32 egress_credit_status_afull : 1;\n+\t\tu32 chp_outbound_hcw_pipe_credit_status_empty : 1;\n+\t\tu32 chp_outbound_hcw_pipe_credit_status_afull : 1;\n+\t\tu32 chp_lsp_ap_cmp_pipe_credit_status_empty : 1;\n+\t\tu32 chp_lsp_ap_cmp_pipe_credit_status_afull : 1;\n+\t\tu32 chp_lsp_tok_pipe_credit_status_empty : 1;\n+\t\tu32 chp_lsp_tok_pipe_credit_status_afull : 1;\n+\t\tu32 chp_rop_pipe_credit_status_empty : 1;\n+\t\tu32 chp_rop_pipe_credit_status_afull : 1;\n+\t\tu32 qed_to_cq_pipe_credit_status_empty : 1;\n+\t\tu32 qed_to_cq_pipe_credit_status_afull : 1;\n+\t\tu32 egress_lsp_token_credit_status_empty : 1;\n+\t\tu32 egress_lsp_token_credit_status_afull : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0 0x54000000\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfefcfaf8\n+union dlb2_dp_cfg_arb_weights_tqpri_dir_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1 0x54000004\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RST 0x0\n+union dlb2_dp_cfg_arb_weights_tqpri_dir_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x54000008\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n+union dlb2_dp_cfg_arb_weights_tqpri_replay_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x5400000c\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n+union dlb2_dp_cfg_arb_weights_tqpri_replay_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_DP_DIR_CSR_CTRL 0x54000010\n+#define DLB2_DP_DIR_CSR_CTRL_RST 0x0\n+union dlb2_dp_dir_csr_ctrl {\n+\tstruct {\n+\t\tu32 int_cor_alarm_dis : 1;\n+\t\tu32 int_cor_synd_dis : 1;\n+\t\tu32 int_uncr_alarm_dis : 1;\n+\t\tu32 int_unc_synd_dis : 1;\n+\t\tu32 int_inf0_alarm_dis : 1;\n+\t\tu32 int_inf0_synd_dis : 1;\n+\t\tu32 int_inf1_alarm_dis : 1;\n+\t\tu32 int_inf1_synd_dis : 1;\n+\t\tu32 int_inf2_alarm_dis : 1;\n+\t\tu32 int_inf2_synd_dis : 1;\n+\t\tu32 int_inf3_alarm_dis : 1;\n+\t\tu32 int_inf3_synd_dis : 1;\n+\t\tu32 int_inf4_alarm_dis : 1;\n+\t\tu32 int_inf4_synd_dis : 1;\n+\t\tu32 int_inf5_alarm_dis : 1;\n+\t\tu32 int_inf5_synd_dis : 1;\n+\t\tu32 rsvz0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014\n+#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n+union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_RO_PIPE_GRP_0_SLT_SHFT(x) \\\n+\t(0x96000000 + (x) * 0x4)\n+#define DLB2_RO_PIPE_GRP_0_SLT_SHFT_RST 0x0\n+union dlb2_ro_pipe_grp_0_slt_shft {\n+\tstruct {\n+\t\tu32 change : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_RO_PIPE_GRP_1_SLT_SHFT(x) \\\n+\t(0x96010000 + (x) * 0x4)\n+#define DLB2_RO_PIPE_GRP_1_SLT_SHFT_RST 0x0\n+union dlb2_ro_pipe_grp_1_slt_shft {\n+\tstruct {\n+\t\tu32 change : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_RO_PIPE_GRP_SN_MODE 0x94000000\n+#define DLB2_RO_PIPE_GRP_SN_MODE_RST 0x0\n+union dlb2_ro_pipe_grp_sn_mode {\n+\tstruct {\n+\t\tu32 sn_mode_0 : 3;\n+\t\tu32 rszv0 : 5;\n+\t\tu32 sn_mode_1 : 3;\n+\t\tu32 rszv1 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0 0x9c000000\n+#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0_RST 0x0\n+union dlb2_ro_pipe_cfg_ctrl_general_0 {\n+\tstruct {\n+\t\tu32 unit_single_step_mode : 1;\n+\t\tu32 rr_en : 1;\n+\t\tu32 rszv0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ2PRIOV(x) \\\n+\t(0xa0000000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2PRIOV_RST 0x0\n+union dlb2_lsp_cq2priov {\n+\tstruct {\n+\t\tu32 prio : 24;\n+\t\tu32 v : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ2QID0(x) \\\n+\t(0xa0080000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2QID0_RST 0x0\n+union dlb2_lsp_cq2qid0 {\n+\tstruct {\n+\t\tu32 qid_p0 : 7;\n+\t\tu32 rsvd3 : 1;\n+\t\tu32 qid_p1 : 7;\n+\t\tu32 rsvd2 : 1;\n+\t\tu32 qid_p2 : 7;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 qid_p3 : 7;\n+\t\tu32 rsvd0 : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ2QID1(x) \\\n+\t(0xa0100000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2QID1_RST 0x0\n+union dlb2_lsp_cq2qid1 {\n+\tstruct {\n+\t\tu32 qid_p4 : 7;\n+\t\tu32 rsvd3 : 1;\n+\t\tu32 qid_p5 : 7;\n+\t\tu32 rsvd2 : 1;\n+\t\tu32 qid_p6 : 7;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 qid_p7 : 7;\n+\t\tu32 rsvd0 : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_DIR_DSBL(x) \\\n+\t(0xa0180000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_DSBL_RST 0x1\n+union dlb2_lsp_cq_dir_dsbl {\n+\tstruct {\n+\t\tu32 disabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_DIR_TKN_CNT(x) \\\n+\t(0xa0200000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TKN_CNT_RST 0x0\n+union dlb2_lsp_cq_dir_tkn_cnt {\n+\tstruct {\n+\t\tu32 count : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n+\t(0xa0280000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0\n+union dlb2_lsp_cq_dir_tkn_depth_sel_dsi {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 disable_wb_opt : 1;\n+\t\tu32 ignore_depth : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n+\t(0xa0300000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0\n+union dlb2_lsp_cq_dir_tot_sch_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n+\t(0xa0380000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0\n+union dlb2_lsp_cq_dir_tot_sch_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_DSBL(x) \\\n+\t(0xa0400000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_DSBL_RST 0x1\n+union dlb2_lsp_cq_ldb_dsbl {\n+\tstruct {\n+\t\tu32 disabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_INFL_CNT(x) \\\n+\t(0xa0480000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_INFL_CNT_RST 0x0\n+union dlb2_lsp_cq_ldb_infl_cnt {\n+\tstruct {\n+\t\tu32 count : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_INFL_LIM(x) \\\n+\t(0xa0500000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_INFL_LIM_RST 0x0\n+union dlb2_lsp_cq_ldb_infl_lim {\n+\tstruct {\n+\t\tu32 limit : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_TKN_CNT(x) \\\n+\t(0xa0580000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TKN_CNT_RST 0x0\n+union dlb2_lsp_cq_ldb_tkn_cnt {\n+\tstruct {\n+\t\tu32 token_count : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n+\t(0xa0600000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0\n+union dlb2_lsp_cq_ldb_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 ignore_depth : 1;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n+\t(0xa0680000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0\n+union dlb2_lsp_cq_ldb_tot_sch_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n+\t(0xa0700000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0\n+union dlb2_lsp_cq_ldb_tot_sch_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH(x) \\\n+\t(0xa0780000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH_RST 0x0\n+union dlb2_lsp_qid_dir_max_depth {\n+\tstruct {\n+\t\tu32 depth : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n+\t(0xa0800000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST 0x0\n+union dlb2_lsp_qid_dir_tot_enq_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n+\t(0xa0880000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST 0x0\n+union dlb2_lsp_qid_dir_tot_enq_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT(x) \\\n+\t(0xa0900000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0\n+union dlb2_lsp_qid_dir_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH(x) \\\n+\t(0xa0980000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RST 0x0\n+union dlb2_lsp_qid_dir_depth_thrsh {\n+\tstruct {\n+\t\tu32 thresh : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT(x) \\\n+\t(0xa0a00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RST 0x0\n+union dlb2_lsp_qid_aqed_active_cnt {\n+\tstruct {\n+\t\tu32 count : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM(x) \\\n+\t(0xa0a80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RST 0x0\n+union dlb2_lsp_qid_aqed_active_lim {\n+\tstruct {\n+\t\tu32 limit : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n+\t(0xa0b00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST 0x0\n+union dlb2_lsp_qid_atm_tot_enq_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n+\t(0xa0b80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST 0x0\n+union dlb2_lsp_qid_atm_tot_enq_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT(x) \\\n+\t(0xa0c00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT_RST 0x0\n+union dlb2_lsp_qid_atq_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT(x) \\\n+\t(0xa0c80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0\n+union dlb2_lsp_qid_ldb_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_LDB_INFL_CNT(x) \\\n+\t(0xa0d00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_INFL_CNT_RST 0x0\n+union dlb2_lsp_qid_ldb_infl_cnt {\n+\tstruct {\n+\t\tu32 count : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_LDB_INFL_LIM(x) \\\n+\t(0xa0d80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_INFL_LIM_RST 0x0\n+union dlb2_lsp_qid_ldb_infl_lim {\n+\tstruct {\n+\t\tu32 limit : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID2CQIDIX_00(x) \\\n+\t(0xa0e00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID2CQIDIX_00_RST 0x0\n+#define DLB2_LSP_QID2CQIDIX(x, y) \\\n+\t(DLB2_LSP_QID2CQIDIX_00(x) + 0x80000 * (y))\n+#define DLB2_LSP_QID2CQIDIX_NUM 16\n+union dlb2_lsp_qid2cqidix_00 {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID2CQIDIX2_00(x) \\\n+\t(0xa1600000 + (x) * 0x1000)\n+#define DLB2_LSP_QID2CQIDIX2_00_RST 0x0\n+#define DLB2_LSP_QID2CQIDIX2(x, y) \\\n+\t(DLB2_LSP_QID2CQIDIX2_00(x) + 0x80000 * (y))\n+#define DLB2_LSP_QID2CQIDIX2_NUM 16\n+union dlb2_lsp_qid2cqidix2_00 {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_LDB_REPLAY_CNT(x) \\\n+\t(0xa1e00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_REPLAY_CNT_RST 0x0\n+union dlb2_lsp_qid_ldb_replay_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH(x) \\\n+\t(0xa1f00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RST 0x0\n+union dlb2_lsp_qid_naldb_max_depth {\n+\tstruct {\n+\t\tu32 depth : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n+\t(0xa1f80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST 0x0\n+union dlb2_lsp_qid_naldb_tot_enq_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n+\t(0xa2000000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST 0x0\n+union dlb2_lsp_qid_naldb_tot_enq_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH(x) \\\n+\t(0xa2080000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RST 0x0\n+union dlb2_lsp_qid_atm_depth_thrsh {\n+\tstruct {\n+\t\tu32 thresh : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH(x) \\\n+\t(0xa2100000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST 0x0\n+union dlb2_lsp_qid_naldb_depth_thrsh {\n+\tstruct {\n+\t\tu32 thresh : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_QID_ATM_ACTIVE(x) \\\n+\t(0xa2180000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_ACTIVE_RST 0x0\n+union dlb2_lsp_qid_atm_active {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0\n+union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_0 {\n+\tstruct {\n+\t\tu32 pri0_weight : 8;\n+\t\tu32 pri1_weight : 8;\n+\t\tu32 pri2_weight : 8;\n+\t\tu32 pri3_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0\n+union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0\n+union dlb2_lsp_cfg_arb_weight_ldb_qid_0 {\n+\tstruct {\n+\t\tu32 pri0_weight : 8;\n+\t\tu32 pri1_weight : 8;\n+\t\tu32 pri2_weight : 8;\n+\t\tu32 pri3_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0\n+union dlb2_lsp_cfg_arb_weight_ldb_qid_1 {\n+\tstruct {\n+\t\tu32 rsvz0 : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_LDB_SCHED_CTRL 0xa400002c\n+#define DLB2_LSP_LDB_SCHED_CTRL_RST 0x0\n+union dlb2_lsp_ldb_sched_ctrl {\n+\tstruct {\n+\t\tu32 cq : 8;\n+\t\tu32 qidix : 3;\n+\t\tu32 value : 1;\n+\t\tu32 nalb_haswork_v : 1;\n+\t\tu32 rlist_haswork_v : 1;\n+\t\tu32 slist_haswork_v : 1;\n+\t\tu32 inflight_ok_v : 1;\n+\t\tu32 aqed_nfull_v : 1;\n+\t\tu32 rsvz0 : 15;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_DIR_SCH_CNT_L 0xa4000034\n+#define DLB2_LSP_DIR_SCH_CNT_L_RST 0x0\n+union dlb2_lsp_dir_sch_cnt_l {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_DIR_SCH_CNT_H 0xa4000038\n+#define DLB2_LSP_DIR_SCH_CNT_H_RST 0x0\n+union dlb2_lsp_dir_sch_cnt_h {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_LDB_SCH_CNT_L 0xa400003c\n+#define DLB2_LSP_LDB_SCH_CNT_L_RST 0x0\n+union dlb2_lsp_ldb_sch_cnt_l {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_LDB_SCH_CNT_H 0xa4000040\n+#define DLB2_LSP_LDB_SCH_CNT_H_RST 0x0\n+union dlb2_lsp_ldb_sch_cnt_h {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_SHDW_CTRL 0xa4000070\n+#define DLB2_LSP_CFG_SHDW_CTRL_RST 0x0\n+union dlb2_lsp_cfg_shdw_ctrl {\n+\tstruct {\n+\t\tu32 transfer : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS(x) \\\n+\t(0xa4000074 + (x) * 4)\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_RST 0x40\n+union dlb2_lsp_cfg_shdw_range_cos {\n+\tstruct {\n+\t\tu32 bw_range : 9;\n+\t\tu32 rsvz0 : 22;\n+\t\tu32 no_extra_credit : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0 0xac000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RST 0x0\n+union dlb2_lsp_cfg_ctrl_general_0 {\n+\tstruct {\n+\t\tu32 disab_atq_empty_arb : 1;\n+\t\tu32 inc_tok_unit_idle : 1;\n+\t\tu32 disab_rlist_pri : 1;\n+\t\tu32 inc_cmp_unit_idle : 1;\n+\t\tu32 rsvz0 : 2;\n+\t\tu32 dir_single_op : 1;\n+\t\tu32 dir_half_bw : 1;\n+\t\tu32 dir_single_out : 1;\n+\t\tu32 dir_disab_multi : 1;\n+\t\tu32 atq_single_op : 1;\n+\t\tu32 atq_half_bw : 1;\n+\t\tu32 atq_single_out : 1;\n+\t\tu32 atq_disab_multi : 1;\n+\t\tu32 dirrpl_single_op : 1;\n+\t\tu32 dirrpl_half_bw : 1;\n+\t\tu32 dirrpl_single_out : 1;\n+\t\tu32 lbrpl_single_op : 1;\n+\t\tu32 lbrpl_half_bw : 1;\n+\t\tu32 lbrpl_single_out : 1;\n+\t\tu32 ldb_single_op : 1;\n+\t\tu32 ldb_half_bw : 1;\n+\t\tu32 ldb_disab_multi : 1;\n+\t\tu32 atm_single_sch : 1;\n+\t\tu32 atm_single_cmp : 1;\n+\t\tu32 ldb_ce_tog_arb : 1;\n+\t\tu32 rsvz1 : 1;\n+\t\tu32 smon0_valid_sel : 2;\n+\t\tu32 smon0_value_sel : 1;\n+\t\tu32 smon0_compare_sel : 2;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CFG_MSTR_DIAG_RESET_STS 0xb4000000\n+#define DLB2_CFG_MSTR_DIAG_RESET_STS_RST 0x80000bff\n+union dlb2_cfg_mstr_diag_reset_sts {\n+\tstruct {\n+\t\tu32 chp_pf_reset_done : 1;\n+\t\tu32 rop_pf_reset_done : 1;\n+\t\tu32 lsp_pf_reset_done : 1;\n+\t\tu32 nalb_pf_reset_done : 1;\n+\t\tu32 ap_pf_reset_done : 1;\n+\t\tu32 dp_pf_reset_done : 1;\n+\t\tu32 qed_pf_reset_done : 1;\n+\t\tu32 dqed_pf_reset_done : 1;\n+\t\tu32 aqed_pf_reset_done : 1;\n+\t\tu32 sys_pf_reset_done : 1;\n+\t\tu32 pf_reset_active : 1;\n+\t\tu32 flrsm_state : 7;\n+\t\tu32 rsvd0 : 13;\n+\t\tu32 dlb_proc_reset_done : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004\n+#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff\n+union dlb2_cfg_mstr_cfg_diagnostic_idle_status {\n+\tstruct {\n+\t\tu32 chp_pipeidle : 1;\n+\t\tu32 rop_pipeidle : 1;\n+\t\tu32 lsp_pipeidle : 1;\n+\t\tu32 nalb_pipeidle : 1;\n+\t\tu32 ap_pipeidle : 1;\n+\t\tu32 dp_pipeidle : 1;\n+\t\tu32 qed_pipeidle : 1;\n+\t\tu32 dqed_pipeidle : 1;\n+\t\tu32 aqed_pipeidle : 1;\n+\t\tu32 sys_pipeidle : 1;\n+\t\tu32 chp_unit_idle : 1;\n+\t\tu32 rop_unit_idle : 1;\n+\t\tu32 lsp_unit_idle : 1;\n+\t\tu32 nalb_unit_idle : 1;\n+\t\tu32 ap_unit_idle : 1;\n+\t\tu32 dp_unit_idle : 1;\n+\t\tu32 qed_unit_idle : 1;\n+\t\tu32 dqed_unit_idle : 1;\n+\t\tu32 aqed_unit_idle : 1;\n+\t\tu32 sys_unit_idle : 1;\n+\t\tu32 rsvd1 : 4;\n+\t\tu32 mstr_cfg_ring_idle : 1;\n+\t\tu32 mstr_cfg_mstr_idle : 1;\n+\t\tu32 mstr_flr_clkreq_b : 1;\n+\t\tu32 mstr_proc_idle : 1;\n+\t\tu32 mstr_proc_idle_masked : 1;\n+\t\tu32 rsvd0 : 2;\n+\t\tu32 dlb_func_idle : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CFG_MSTR_CFG_PM_STATUS 0xb4000014\n+#define DLB2_CFG_MSTR_CFG_PM_STATUS_RST 0x100403e\n+union dlb2_cfg_mstr_cfg_pm_status {\n+\tstruct {\n+\t\tu32 prochot : 1;\n+\t\tu32 pgcb_dlb_idle : 1;\n+\t\tu32 pgcb_dlb_pg_rdy_ack_b : 1;\n+\t\tu32 pmsm_pgcb_req_b : 1;\n+\t\tu32 pgbc_pmc_pg_req_b : 1;\n+\t\tu32 pmc_pgcb_pg_ack_b : 1;\n+\t\tu32 pmc_pgcb_fet_en_b : 1;\n+\t\tu32 pgcb_fet_en_b : 1;\n+\t\tu32 rsvz0 : 1;\n+\t\tu32 rsvz1 : 1;\n+\t\tu32 fuse_force_on : 1;\n+\t\tu32 fuse_proc_disable : 1;\n+\t\tu32 rsvz2 : 1;\n+\t\tu32 rsvz3 : 1;\n+\t\tu32 pm_fsm_d0tod3_ok : 1;\n+\t\tu32 pm_fsm_d3tod0_ok : 1;\n+\t\tu32 dlb_in_d3 : 1;\n+\t\tu32 rsvz4 : 7;\n+\t\tu32 pmsm : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE 0xb4000018\n+#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE_RST 0x1\n+union dlb2_cfg_mstr_cfg_pm_pmcsr_disable {\n+\tstruct {\n+\t\tu32 disable : 1;\n+\t\tu32 rsvz0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_VF2PF_MAILBOX_BYTES 256\n+#define DLB2_FUNC_VF_VF2PF_MAILBOX(x) \\\n+\t(0x1000 + (x) * 0x4)\n+#define DLB2_FUNC_VF_VF2PF_MAILBOX_RST 0x0\n+union dlb2_func_vf_vf2pf_mailbox {\n+\tstruct {\n+\t\tu32 msg : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR 0x1f00\n+#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR_RST 0x0\n+#define DLB2_FUNC_VF_SIOV_VF2PF_MAILBOX_ISR_TRIGGER 0x8000\n+union dlb2_func_vf_vf2pf_mailbox_isr {\n+\tstruct {\n+\t\tu32 isr : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_PF2VF_MAILBOX_BYTES 64\n+#define DLB2_FUNC_VF_PF2VF_MAILBOX(x) \\\n+\t(0x2000 + (x) * 0x4)\n+#define DLB2_FUNC_VF_PF2VF_MAILBOX_RST 0x0\n+union dlb2_func_vf_pf2vf_mailbox {\n+\tstruct {\n+\t\tu32 msg : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR 0x2f00\n+#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR_RST 0x0\n+union dlb2_func_vf_pf2vf_mailbox_isr {\n+\tstruct {\n+\t\tu32 pf_isr : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_VF_MSI_ISR_PEND 0x2f10\n+#define DLB2_FUNC_VF_VF_MSI_ISR_PEND_RST 0x0\n+union dlb2_func_vf_vf_msi_isr_pend {\n+\tstruct {\n+\t\tu32 isr_pend : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS 0x3000\n+#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS_RST 0x1\n+union dlb2_func_vf_vf_reset_in_progress {\n+\tstruct {\n+\t\tu32 reset_in_progress : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB2_FUNC_VF_VF_MSI_ISR 0x4000\n+#define DLB2_FUNC_VF_VF_MSI_ISR_RST 0x0\n+union dlb2_func_vf_vf_msi_isr {\n+\tstruct {\n+\t\tu32 vf_msi_isr : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#endif /* __DLB2_REGS_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nnew file mode 100644\nindex 0000000..6de8b95\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -0,0 +1,274 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_hw_types.h\"\n+#include \"dlb2_mbox.h\"\n+#include \"dlb2_osdep.h\"\n+#include \"dlb2_osdep_bitmap.h\"\n+#include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs.h\"\n+#include \"dlb2_resource.h\"\n+\n+static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)\n+{\n+\tint i;\n+\n+\tdlb2_list_init_head(&domain->used_ldb_queues);\n+\tdlb2_list_init_head(&domain->used_dir_pq_pairs);\n+\tdlb2_list_init_head(&domain->avail_ldb_queues);\n+\tdlb2_list_init_head(&domain->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->used_ldb_ports[i]);\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->avail_ldb_ports[i]);\n+}\n+\n+static void dlb2_init_fn_rsrc_lists(struct dlb2_function_resources *rsrc)\n+{\n+\tint i;\n+\n+\tdlb2_list_init_head(&rsrc->avail_domains);\n+\tdlb2_list_init_head(&rsrc->used_domains);\n+\tdlb2_list_init_head(&rsrc->avail_ldb_queues);\n+\tdlb2_list_init_head(&rsrc->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&rsrc->avail_ldb_ports[i]);\n+}\n+\n+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.field.cfg_64bytes_qe_dir_cq_mode = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n+\t\t\t      struct dlb2_get_num_resources_args *arg,\n+\t\t\t      bool vdev_req,\n+\t\t\t      unsigned int vdev_id)\n+{\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_bitmap *map;\n+\tint i;\n+\n+\tif (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)\n+\t\treturn -EINVAL;\n+\n+\tif (vdev_req)\n+\t\trsrcs = &hw->vdev[vdev_id];\n+\telse\n+\t\trsrcs = &hw->pf;\n+\n+\targ->num_sched_domains = rsrcs->num_avail_domains;\n+\n+\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n+\n+\targ->num_ldb_ports = 0;\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\targ->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];\n+\n+\targ->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];\n+\targ->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];\n+\targ->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];\n+\targ->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];\n+\n+\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n+\n+\targ->num_atomic_inflights = rsrcs->num_avail_aqed_entries;\n+\n+\tmap = rsrcs->avail_hist_list_entries;\n+\n+\targ->num_hist_list_entries = dlb2_bitmap_count(map);\n+\n+\targ->max_contiguous_hist_list_entries =\n+\t\tdlb2_bitmap_longest_set_range(map);\n+\n+\targ->num_ldb_credits = rsrcs->num_avail_qed_entries;\n+\n+\targ->num_dir_credits = rsrcs->num_avail_dqed_entries;\n+\n+\treturn 0;\n+}\n+\n+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.field.cfg_64bytes_qe_ldb_cq_mode = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+void dlb2_resource_free(struct dlb2_hw *hw)\n+{\n+\tint i;\n+\n+\tif (hw->pf.avail_hist_list_entries)\n+\t\tdlb2_bitmap_free(hw->pf.avail_hist_list_entries);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tif (hw->vdev[i].avail_hist_list_entries)\n+\t\t\tdlb2_bitmap_free(hw->vdev[i].avail_hist_list_entries);\n+\t}\n+}\n+\n+int dlb2_resource_init(struct dlb2_hw *hw)\n+{\n+\tstruct dlb2_list_entry *list;\n+\tunsigned int i;\n+\tint ret;\n+\n+\t/*\n+\t * For optimal load-balancing, ports that map to one or more QIDs in\n+\t * common should not be in numerical sequence. This is application\n+\t * dependent, but the driver interleaves port IDs as much as possible\n+\t * to reduce the likelihood of this. This initial allocation maximizes\n+\t * the average distance between an ID and its immediate neighbors (i.e.\n+\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n+\t * 3, etc.).\n+\t */\n+\tu8 init_ldb_port_allocation[DLB2_MAX_NUM_LDB_PORTS] = {\n+\t\t0,  7,  14,  5, 12,  3, 10,  1,  8, 15,  6, 13,  4, 11,  2,  9,\n+\t\t16, 23, 30, 21, 28, 19, 26, 17, 24, 31, 22, 29, 20, 27, 18, 25,\n+\t\t32, 39, 46, 37, 44, 35, 42, 33, 40, 47, 38, 45, 36, 43, 34, 41,\n+\t\t48, 55, 62, 53, 60, 51, 58, 49, 56, 63, 54, 61, 52, 59, 50, 57,\n+\t};\n+\n+\t/* Zero-out resource tracking data structures */\n+\tmemset(&hw->rsrcs, 0, sizeof(hw->rsrcs));\n+\tmemset(&hw->pf, 0, sizeof(hw->pf));\n+\n+\tdlb2_init_fn_rsrc_lists(&hw->pf);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tmemset(&hw->vdev[i], 0, sizeof(hw->vdev[i]));\n+\t\tdlb2_init_fn_rsrc_lists(&hw->vdev[i]);\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tmemset(&hw->domains[i], 0, sizeof(hw->domains[i]));\n+\t\tdlb2_init_domain_rsrc_lists(&hw->domains[i]);\n+\t\thw->domains[i].parent_func = &hw->pf;\n+\t}\n+\n+\t/* Give all resources to the PF driver */\n+\thw->pf.num_avail_domains = DLB2_MAX_NUM_DOMAINS;\n+\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n+\t\tlist = &hw->domains[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_domains, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_queues = DLB2_MAX_NUM_LDB_QUEUES;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n+\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_queues, list);\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->pf.num_avail_ldb_ports[i] =\n+\t\t\tDLB2_MAX_NUM_LDB_PORTS / DLB2_NUM_COS_DOMAINS;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\tint cos_id = i >> DLB2_NUM_COS_DOMAINS;\n+\t\tstruct dlb2_ldb_port *port;\n+\n+\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_ports[cos_id],\n+\t\t\t      &port->func_list);\n+\t}\n+\n+\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n+\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_dir_pq_pairs, list);\n+\t}\n+\n+\thw->pf.num_avail_qed_entries = DLB2_MAX_NUM_LDB_CREDITS;\n+\thw->pf.num_avail_dqed_entries = DLB2_MAX_NUM_DIR_CREDITS;\n+\thw->pf.num_avail_aqed_entries = DLB2_MAX_NUM_AQED_ENTRIES;\n+\n+\tret = dlb2_bitmap_alloc(&hw->pf.avail_hist_list_entries,\n+\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tret = dlb2_bitmap_fill(hw->pf.avail_hist_list_entries);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tret = dlb2_bitmap_alloc(&hw->vdev[i].avail_hist_list_entries,\n+\t\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\n+\t\tret = dlb2_bitmap_zero(hw->vdev[i].avail_hist_list_entries);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\t}\n+\n+\t/* Initialize the hardware resource IDs */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\thw->domains[i].id.phys_id = i;\n+\t\thw->domains[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_QUEUES; i++) {\n+\t\thw->rsrcs.ldb_queues[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_queues[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\thw->rsrcs.ldb_ports[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_ports[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS; i++) {\n+\t\thw->rsrcs.dir_pq_pairs[i].id.phys_id = i;\n+\t\thw->rsrcs.dir_pq_pairs[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\thw->rsrcs.sn_groups[i].id = i;\n+\t\t/* Default mode (0) is 64 sequence numbers per queue */\n+\t\thw->rsrcs.sn_groups[i].mode = 0;\n+\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 64;\n+\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->cos_reservation[i] = 100 / DLB2_NUM_COS_DOMAINS;\n+\n+\treturn 0;\n+\n+unwind:\n+\tdlb2_resource_free(hw);\n+\n+\treturn ret;\n+}\n+\n+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_cfg_mstr_cfg_pm_pmcsr_disable r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE);\n+\n+\tr0.field.disable = 0;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE, r0.val);\n+}\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb2/pf/base/dlb2_resource.h\nnew file mode 100644\nindex 0000000..503fdf3\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.h\n@@ -0,0 +1,1913 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_RESOURCE_H\n+#define __DLB2_RESOURCE_H\n+\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_hw_types.h\"\n+#include \"dlb2_osdep_types.h\"\n+\n+/**\n+ * dlb2_resource_init() - initialize the device\n+ * @hw: pointer to struct dlb2_hw.\n+ *\n+ * This function initializes the device's software state (pointed to by the hw\n+ * argument) and programs global scheduling QoS registers. This function should\n+ * be called during driver initialization.\n+ *\n+ * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the\n+ * device is reset.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ */\n+int dlb2_resource_init(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_resource_free() - free device state memory\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function frees software state pointed to by dlb2_hw. This function\n+ * should be called when resetting the device or unloading the driver.\n+ */\n+void dlb2_resource_free(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_resource_reset() - reset in-use resources to their initial state\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function resets in-use resources, and makes them available for use.\n+ * All resources go back to their owning function, whether a PF or a VF.\n+ */\n+void dlb2_resource_reset(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_create_sched_domain() - create a scheduling domain\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @args: scheduling domain creation arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function creates a scheduling domain containing the resources specified\n+ * in args. The individual resources (queues, ports, credits) can be configured\n+ * after creating a scheduling domain.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the domain ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_request is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, or the requested domain name\n+ *\t    is already in use.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_create_sched_domain_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp,\n+\t\t\t\tbool vdev_request,\n+\t\t\t\tunsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_create_ldb_queue() - create a load-balanced queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue creation arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function creates a load-balanced queue.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_request is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    the domain has already been started, or the requested queue name is\n+ *\t    already in use.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_ldb_queue(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_create_ldb_queue_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp,\n+\t\t\t     bool vdev_request,\n+\t\t\t     unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_create_dir_queue() - create a directed queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue creation arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function creates a directed queue.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_request is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_dir_queue(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_create_dir_queue_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp,\n+\t\t\t     bool vdev_request,\n+\t\t\t     unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_create_dir_port() - create a directed port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function creates a directed port.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_request is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t    pointer address is not properly aligned, the domain is not\n+ *\t    configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_dir_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_create_dir_port_args *args,\n+\t\t\t    uintptr_t cq_dma_base,\n+\t\t\t    struct dlb2_cmd_response *resp,\n+\t\t\t    bool vdev_request,\n+\t\t\t    unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_create_ldb_port() - create a load-balanced port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function creates a load-balanced port.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_request is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t    pointer address is not properly aligned, the domain is not\n+ *\t    configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_create_ldb_port_args *args,\n+\t\t\t    uintptr_t cq_dma_base,\n+\t\t\t    struct dlb2_cmd_response *resp,\n+\t\t\t    bool vdev_request,\n+\t\t\t    unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_start_domain() - start a scheduling domain\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: start domain arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function starts a scheduling domain, which allows applications to send\n+ * traffic through it. Once a domain is started, its resources can no longer be\n+ * configured (besides QID remapping and port enable/disable).\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - the domain is not configured, or the domain is already started.\n+ */\n+int dlb2_hw_start_domain(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_start_domain_args *args,\n+\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t bool vdev_request,\n+\t\t\t unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_map_qid() - map a load-balanced queue to a load-balanced port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: map QID arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to schedule QEs from the specified queue\n+ * to the specified port. Each load-balanced port can be mapped to up to 8\n+ * queues; each load-balanced queue can potentially map to all the\n+ * load-balanced ports.\n+ *\n+ * A successful return does not necessarily mean the mapping was configured. If\n+ * this function is unable to immediately map the queue to the port, it will\n+ * add the requested operation to a per-port list of pending map/unmap\n+ * operations, and (if it's not already running) launch a kernel thread that\n+ * periodically attempts to process all pending operations. In a sense, this is\n+ * an asynchronous function.\n+ *\n+ * This asynchronicity creates two views of the state of hardware: the actual\n+ * hardware state and the requested state (as if every request completed\n+ * immediately). If there are any pending map/unmap operations, the requested\n+ * state will differ from the actual state. All validation is performed with\n+ * respect to the pending state; for instance, if there are 8 pending map\n+ * operations for port X, a request for a 9th will fail because a load-balanced\n+ * port can only map up to 8 queues.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, invalid port or queue ID, or\n+ *\t    the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_map_qid(struct dlb2_hw *hw,\n+\t\t    u32 domain_id,\n+\t\t    struct dlb2_map_qid_args *args,\n+\t\t    struct dlb2_cmd_response *resp,\n+\t\t    bool vdev_request,\n+\t\t    unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_unmap_qid() - Unmap a load-balanced queue from a load-balanced port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: unmap QID arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to stop scheduling QEs from the specified\n+ * queue to the specified port.\n+ *\n+ * A successful return does not necessarily mean the mapping was removed. If\n+ * this function is unable to immediately unmap the queue from the port, it\n+ * will add the requested operation to a per-port list of pending map/unmap\n+ * operations, and (if it's not already running) launch a kernel thread that\n+ * periodically attempts to process all pending operations. See\n+ * dlb2_hw_map_qid() for more details.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, invalid port or queue ID, or\n+ *\t    the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_unmap_qid(struct dlb2_hw *hw,\n+\t\t      u32 domain_id,\n+\t\t      struct dlb2_unmap_qid_args *args,\n+\t\t      struct dlb2_cmd_response *resp,\n+\t\t      bool vdev_request,\n+\t\t      unsigned int vdev_id);\n+\n+/**\n+ * dlb2_finish_unmap_qid_procedures() - finish any pending unmap procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding unmap procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_finish_map_qid_procedures() - finish any pending map procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding map procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_enable_ldb_port() - enable a load-balanced port for scheduling\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port enable arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to schedule QEs to a load-balanced port.\n+ * Ports are enabled by default.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_enable_ldb_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_enable_ldb_port_args *args,\n+\t\t\t    struct dlb2_cmd_response *resp,\n+\t\t\t    bool vdev_request,\n+\t\t\t    unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_disable_ldb_port() - disable a load-balanced port for scheduling\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port disable arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to stop scheduling QEs to a load-balanced\n+ * port. Ports are enabled by default.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_disable_ldb_port(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_disable_ldb_port_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp,\n+\t\t\t     bool vdev_request,\n+\t\t\t     unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_enable_dir_port() - enable a directed port for scheduling\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port enable arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to schedule QEs to a directed port.\n+ * Ports are enabled by default.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_enable_dir_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_enable_dir_port_args *args,\n+\t\t\t    struct dlb2_cmd_response *resp,\n+\t\t\t    bool vdev_request,\n+\t\t\t    unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_disable_dir_port() - disable a directed port for scheduling\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port disable arguments.\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function configures the DLB to stop scheduling QEs to a directed port.\n+ * Ports are enabled by default.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_disable_dir_port(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_disable_dir_port_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp,\n+\t\t\t     bool vdev_request,\n+\t\t\t     unsigned int vdev_id);\n+\n+/**\n+ * dlb2_configure_ldb_cq_interrupt() - configure load-balanced CQ for\n+ *\t\t\t\t\tinterrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: load-balanced port ID.\n+ * @vector: interrupt vector ID. Should be 0 for MSI or compressed MSI-X mode,\n+ *\t    else a value up to 64.\n+ * @mode: interrupt type (DLB2_CQ_ISR_MODE_MSI or DLB2_CQ_ISR_MODE_MSIX)\n+ * @vf: If the port is VF-owned, the VF's ID. This is used for translating the\n+ *\tvirtual port ID to a physical port ID. Ignored if mode is not MSI.\n+ * @owner_vf: the VF to route the interrupt to. Ignore if mode is not MSI.\n+ * @threshold: the minimum CQ depth at which the interrupt can fire. Must be\n+ *\tgreater than 0.\n+ *\n+ * This function configures the DLB registers for load-balanced CQ's\n+ * interrupts. This doesn't enable the CQ's interrupt; that can be done with\n+ * dlb2_arm_cq_interrupt() or through an interrupt arm QE.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid.\n+ */\n+int dlb2_configure_ldb_cq_interrupt(struct dlb2_hw *hw,\n+\t\t\t\t    int port_id,\n+\t\t\t\t    int vector,\n+\t\t\t\t    int mode,\n+\t\t\t\t    unsigned int vf,\n+\t\t\t\t    unsigned int owner_vf,\n+\t\t\t\t    u16 threshold);\n+\n+/**\n+ * dlb2_configure_dir_cq_interrupt() - configure directed CQ for interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: load-balanced port ID.\n+ * @vector: interrupt vector ID. Should be 0 for MSI or compressed MSI-X mode,\n+ *\t    else a value up to 64.\n+ * @mode: interrupt type (DLB2_CQ_ISR_MODE_MSI or DLB2_CQ_ISR_MODE_MSIX)\n+ * @vf: If the port is VF-owned, the VF's ID. This is used for translating the\n+ *\tvirtual port ID to a physical port ID. Ignored if mode is not MSI.\n+ * @owner_vf: the VF to route the interrupt to. Ignore if mode is not MSI.\n+ * @threshold: the minimum CQ depth at which the interrupt can fire. Must be\n+ *\tgreater than 0.\n+ *\n+ * This function configures the DLB registers for directed CQ's interrupts.\n+ * This doesn't enable the CQ's interrupt; that can be done with\n+ * dlb2_arm_cq_interrupt() or through an interrupt arm QE.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid.\n+ */\n+int dlb2_configure_dir_cq_interrupt(struct dlb2_hw *hw,\n+\t\t\t\t    int port_id,\n+\t\t\t\t    int vector,\n+\t\t\t\t    int mode,\n+\t\t\t\t    unsigned int vf,\n+\t\t\t\t    unsigned int owner_vf,\n+\t\t\t\t    u16 threshold);\n+\n+/**\n+ * dlb2_enable_ingress_error_alarms() - enable ingress error alarm interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ */\n+void dlb2_enable_ingress_error_alarms(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_disable_ingress_error_alarms() - disable ingress error alarm interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ */\n+void dlb2_disable_ingress_error_alarms(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_set_msix_mode() - enable certain hardware alarm interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @mode: MSI-X mode (DLB2_MSIX_MODE_PACKED or DLB2_MSIX_MODE_COMPRESSED)\n+ *\n+ * This function configures the hardware to use either packed or compressed\n+ * mode. This function should not be called if using MSI interrupts.\n+ */\n+void dlb2_set_msix_mode(struct dlb2_hw *hw, int mode);\n+\n+/**\n+ * dlb2_ack_msix_interrupt() - Ack an MSI-X interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vector: interrupt vector.\n+ *\n+ * Note: Only needed for PF service interrupts (vector 0). CQ interrupts are\n+ * acked in dlb2_ack_compressed_cq_intr().\n+ */\n+void dlb2_ack_msix_interrupt(struct dlb2_hw *hw, int vector);\n+\n+/**\n+ * dlb2_arm_cq_interrupt() - arm a CQ's interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: port ID\n+ * @is_ldb: true for load-balanced port, false for a directed port\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function arms the CQ's interrupt. The CQ must be configured prior to\n+ * calling this function.\n+ *\n+ * The function does no parameter validation; that is the caller's\n+ * responsibility.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return: returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - Invalid port ID.\n+ */\n+int dlb2_arm_cq_interrupt(struct dlb2_hw *hw,\n+\t\t\t  int port_id,\n+\t\t\t  bool is_ldb,\n+\t\t\t  bool vdev_request,\n+\t\t\t  unsigned int vdev_id);\n+\n+/**\n+ * dlb2_read_compressed_cq_intr_status() - read compressed CQ interrupt status\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @ldb_interrupts: 2-entry array of u32 bitmaps\n+ * @dir_interrupts: 4-entry array of u32 bitmaps\n+ *\n+ * This function can be called from a compressed CQ interrupt handler to\n+ * determine which CQ interrupts have fired. The caller should take appropriate\n+ * (such as waking threads blocked on a CQ's interrupt) then ack the interrupts\n+ * with dlb2_ack_compressed_cq_intr().\n+ */\n+void dlb2_read_compressed_cq_intr_status(struct dlb2_hw *hw,\n+\t\t\t\t\t u32 *ldb_interrupts,\n+\t\t\t\t\t u32 *dir_interrupts);\n+\n+/**\n+ * dlb2_ack_compressed_cq_intr_status() - ack compressed CQ interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @ldb_interrupts: 2-entry array of u32 bitmaps\n+ * @dir_interrupts: 4-entry array of u32 bitmaps\n+ *\n+ * This function ACKs compressed CQ interrupts. Its arguments should be the\n+ * same ones passed to dlb2_read_compressed_cq_intr_status().\n+ */\n+void dlb2_ack_compressed_cq_intr(struct dlb2_hw *hw,\n+\t\t\t\t u32 *ldb_interrupts,\n+\t\t\t\t u32 *dir_interrupts);\n+\n+/**\n+ * dlb2_read_vf_intr_status() - read the VF interrupt status register\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function can be called from a VF's interrupt handler to determine\n+ * which interrupts have fired. The first 31 bits correspond to CQ interrupt\n+ * vectors, and the final bit is for the PF->VF mailbox interrupt vector.\n+ *\n+ * Return:\n+ * Returns a bit vector indicating which interrupt vectors are active.\n+ */\n+u32 dlb2_read_vf_intr_status(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_ack_vf_intr_status() - ack VF interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @interrupts: 32-bit bitmap\n+ *\n+ * This function ACKs a VF's interrupts. Its interrupts argument should be the\n+ * value returned by dlb2_read_vf_intr_status().\n+ */\n+void dlb2_ack_vf_intr_status(struct dlb2_hw *hw, u32 interrupts);\n+\n+/**\n+ * dlb2_ack_vf_msi_intr() - ack VF MSI interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @interrupts: 32-bit bitmap\n+ *\n+ * This function clears the VF's MSI interrupt pending register. Its interrupts\n+ * argument should be contain the MSI vectors to ACK. For example, if MSI MME\n+ * is in mode 0, then one bit 0 should ever be set.\n+ */\n+void dlb2_ack_vf_msi_intr(struct dlb2_hw *hw, u32 interrupts);\n+\n+/**\n+ * dlb2_ack_pf_mbox_int() - ack PF->VF mailbox interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * When done processing the PF mailbox request, this function unsets\n+ * the PF's mailbox ISR register.\n+ */\n+void dlb2_ack_pf_mbox_int(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_read_vdev_to_pf_int_bitvec() - return a bit vector of all requesting\n+ *\t\t\t\t\tvdevs\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * When the vdev->PF ISR fires, this function can be called to determine which\n+ * vdev(s) are requesting service. This bitvector must be passed to\n+ * dlb2_ack_vdev_to_pf_int() when processing is complete for all requesting\n+ * vdevs.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns a bit vector indicating which VFs (0-15) have requested service.\n+ */\n+u32 dlb2_read_vdev_to_pf_int_bitvec(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_ack_vdev_mbox_int() - ack processed vdev->PF mailbox interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @bitvec: bit vector returned by dlb2_read_vdev_to_pf_int_bitvec()\n+ *\n+ * When done processing all VF mailbox requests, this function unsets the VF's\n+ * mailbox ISR register.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_ack_vdev_mbox_int(struct dlb2_hw *hw, u32 bitvec);\n+\n+/**\n+ * dlb2_read_vf_flr_int_bitvec() - return a bit vector of all VFs requesting\n+ *\t\t\t\t    FLR\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * When the VF FLR ISR fires, this function can be called to determine which\n+ * VF(s) are requesting FLRs. This bitvector must passed to\n+ * dlb2_ack_vf_flr_int() when processing is complete for all requesting VFs.\n+ *\n+ * Return:\n+ * Returns a bit vector indicating which VFs (0-15) have requested FLRs.\n+ */\n+u32 dlb2_read_vf_flr_int_bitvec(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_ack_vf_flr_int() - ack processed VF<->PF interrupt(s)\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @bitvec: bit vector returned by dlb2_read_vf_flr_int_bitvec()\n+ *\n+ * When done processing all VF FLR requests, this function unsets the VF's FLR\n+ * ISR register.\n+ */\n+void dlb2_ack_vf_flr_int(struct dlb2_hw *hw, u32 bitvec);\n+\n+/**\n+ * dlb2_ack_vdev_to_pf_int() - ack processed VF mbox and FLR interrupt(s)\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @mbox_bitvec: bit vector returned by dlb2_read_vdev_to_pf_int_bitvec()\n+ * @flr_bitvec: bit vector returned by dlb2_read_vf_flr_int_bitvec()\n+ *\n+ * When done processing all VF requests, this function communicates to the\n+ * hardware that processing is complete.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_ack_vdev_to_pf_int(struct dlb2_hw *hw,\n+\t\t\t     u32 mbox_bitvec,\n+\t\t\t     u32 flr_bitvec);\n+\n+/**\n+ * dlb2_process_wdt_interrupt() - process watchdog timer interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function reads the watchdog timer interrupt cause registers to\n+ * determine which port(s) had a watchdog timeout, and notifies the\n+ * application(s) that own the port(s).\n+ */\n+void dlb2_process_wdt_interrupt(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_process_alarm_interrupt() - process an alarm interrupt\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function reads and logs the alarm syndrome, then acks the interrupt.\n+ * This function should be called from the alarm interrupt handler when\n+ * interrupt vector DLB2_INT_ALARM fires.\n+ */\n+void dlb2_process_alarm_interrupt(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_process_ingress_error_interrupt() - process ingress error interrupts\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function reads the alarm syndrome, logs it, notifies user-space, and\n+ * acks the interrupt. This function should be called from the alarm interrupt\n+ * handler when interrupt vector DLB2_INT_INGRESS_ERROR fires.\n+ *\n+ * Return:\n+ * Returns true if an ingress error interrupt occurred, false otherwise\n+ */\n+bool dlb2_process_ingress_error_interrupt(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_get_group_sequence_numbers() - return a group's number of SNs per queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the configured number of sequence numbers per queue\n+ * for the specified group.\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.\n+ */\n+int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw,\n+\t\t\t\t    unsigned int group_id);\n+\n+/**\n+ * dlb2_get_group_sequence_number_occupancy() - return a group's in-use slots\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the group's number of in-use slots (i.e. load-balanced\n+ * queues using the specified group).\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.\n+ */\n+int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,\n+\t\t\t\t\t     unsigned int group_id);\n+\n+/**\n+ * dlb2_set_group_sequence_numbers() - assign a group's number of SNs per queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ * @val: requested amount of sequence numbers per queue.\n+ *\n+ * This function configures the group's number of sequence numbers per queue.\n+ * val can be a power-of-two between 32 and 1024, inclusive. This setting can\n+ * be configured until the first ordered load-balanced queue is configured, at\n+ * which point the configuration is locked.\n+ *\n+ * Return:\n+ * Returns 0 upon success; -EINVAL if group_id or val is invalid, -EPERM if an\n+ * ordered queue is configured.\n+ */\n+int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n+\t\t\t\t    unsigned int group_id,\n+\t\t\t\t    unsigned long val);\n+\n+/**\n+ * dlb2_reset_domain() - reset a scheduling domain\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function resets and frees a DLB 2.0 scheduling domain and its associated\n+ * resources.\n+ *\n+ * Pre-condition: the driver must ensure software has stopped sending QEs\n+ * through this domain's producer ports before invoking this function, or\n+ * undefined behavior will result.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -1 otherwise.\n+ *\n+ * EINVAL - Invalid domain ID, or the domain is not configured.\n+ * EFAULT - Internal error. (Possibly caused if software is the pre-condition\n+ *\t    is not met.)\n+ * ETIMEDOUT - Hardware component didn't reset in the expected time.\n+ */\n+int dlb2_reset_domain(struct dlb2_hw *hw,\n+\t\t      u32 domain_id,\n+\t\t      bool vdev_request,\n+\t\t      unsigned int vdev_id);\n+\n+/**\n+ * dlb2_ldb_port_owned_by_domain() - query whether a port is owned by a domain\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @port_id: indicates whether this request came from a VF.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns whether a load-balanced port is owned by a specified\n+ * domain.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 if false, 1 if true, <0 otherwise.\n+ *\n+ * EINVAL - Invalid domain or port ID, or the domain is not configured.\n+ */\n+int dlb2_ldb_port_owned_by_domain(struct dlb2_hw *hw,\n+\t\t\t\t  u32 domain_id,\n+\t\t\t\t  u32 port_id,\n+\t\t\t\t  bool vdev_request,\n+\t\t\t\t  unsigned int vdev_id);\n+\n+/**\n+ * dlb2_dir_port_owned_by_domain() - query whether a port is owned by a domain\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @port_id: indicates whether this request came from a VF.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns whether a directed port is owned by a specified\n+ * domain.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 if false, 1 if true, <0 otherwise.\n+ *\n+ * EINVAL - Invalid domain or port ID, or the domain is not configured.\n+ */\n+int dlb2_dir_port_owned_by_domain(struct dlb2_hw *hw,\n+\t\t\t\t  u32 domain_id,\n+\t\t\t\t  u32 port_id,\n+\t\t\t\t  bool vdev_request,\n+\t\t\t\t  unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_get_num_resources() - query the PCI function's available resources\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @arg: pointer to resource counts.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns the number of available resources for the PF or for a\n+ * VF.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -EINVAL if vdev_request is true and vdev_id is\n+ * invalid.\n+ */\n+int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n+\t\t\t      struct dlb2_get_num_resources_args *arg,\n+\t\t\t      bool vdev_request,\n+\t\t\t      unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_get_num_used_resources() - query the PCI function's used resources\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @arg: pointer to resource counts.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns the number of resources in use by the PF or a VF. It\n+ * fills in the fields that args points to, except the following:\n+ * - max_contiguous_atomic_inflights\n+ * - max_contiguous_hist_list_entries\n+ * - max_contiguous_ldb_credits\n+ * - max_contiguous_dir_credits\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -EINVAL if vdev_request is true and vdev_id is\n+ * invalid.\n+ */\n+int dlb2_hw_get_num_used_resources(struct dlb2_hw *hw,\n+\t\t\t\t   struct dlb2_get_num_resources_args *arg,\n+\t\t\t\t   bool vdev_request,\n+\t\t\t\t   unsigned int vdev_id);\n+\n+/**\n+ * dlb2_send_async_vdev_to_pf_msg() - (vdev only) send a mailbox message to\n+ *\t\t\t\t       the PF\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function sends a VF->PF mailbox message. It is asynchronous, so it\n+ * returns once the message is sent but potentially before the PF has processed\n+ * the message. The caller must call dlb2_vdev_to_pf_complete() to determine\n+ * when the PF has finished processing the request.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_send_async_vdev_to_pf_msg(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_vdev_to_pf_complete() - check the status of an asynchronous mailbox\n+ *\t\t\t\t request\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function returns a boolean indicating whether the PF has finished\n+ * processing a VF->PF mailbox request. It should only be called after sending\n+ * an asynchronous request with dlb2_send_async_vdev_to_pf_msg().\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+bool dlb2_vdev_to_pf_complete(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_vf_flr_complete() - check the status of a VF FLR\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function returns a boolean indicating whether the PF has finished\n+ * executing the VF FLR. It should only be called after setting the VF's FLR\n+ * bit.\n+ */\n+bool dlb2_vf_flr_complete(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_send_async_pf_to_vdev_msg() - (PF only) send a mailbox message to a\n+ *\t\t\t\t\tvdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ *\n+ * This function sends a PF->vdev mailbox message. It is asynchronous, so it\n+ * returns once the message is sent but potentially before the vdev has\n+ * processed the message. The caller must call dlb2_pf_to_vdev_complete() to\n+ * determine when the vdev has finished processing the request.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_send_async_pf_to_vdev_msg(struct dlb2_hw *hw, unsigned int vdev_id);\n+\n+/**\n+ * dlb2_pf_to_vdev_complete() - check the status of an asynchronous mailbox\n+ *\t\t\t       request\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ *\n+ * This function returns a boolean indicating whether the vdev has finished\n+ * processing a PF->vdev mailbox request. It should only be called after\n+ * sending an asynchronous request with dlb2_send_async_pf_to_vdev_msg().\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+bool dlb2_pf_to_vdev_complete(struct dlb2_hw *hw, unsigned int vdev_id);\n+\n+/**\n+ * dlb2_pf_read_vf_mbox_req() - (PF only) read a VF->PF mailbox request\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vf_id: VF ID.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies one of the PF's VF->PF mailboxes into the array pointed\n+ * to by data.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_VF2PF_REQ_BYTES.\n+ */\n+int dlb2_pf_read_vf_mbox_req(struct dlb2_hw *hw,\n+\t\t\t     unsigned int vf_id,\n+\t\t\t     void *data,\n+\t\t\t     int len);\n+\n+/**\n+ * dlb2_pf_read_vf_mbox_resp() - (PF only) read a VF->PF mailbox response\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vf_id: VF ID.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies one of the PF's VF->PF mailboxes into the array pointed\n+ * to by data.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_VF2PF_RESP_BYTES.\n+ */\n+int dlb2_pf_read_vf_mbox_resp(struct dlb2_hw *hw,\n+\t\t\t      unsigned int vf_id,\n+\t\t\t      void *data,\n+\t\t\t      int len);\n+\n+/**\n+ * dlb2_pf_write_vf_mbox_resp() - (PF only) write a PF->VF mailbox response\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vf_id: VF ID.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the user-provided message data into of the PF's VF->PF\n+ * mailboxes.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_PF2VF_RESP_BYTES.\n+ */\n+int dlb2_pf_write_vf_mbox_resp(struct dlb2_hw *hw,\n+\t\t\t       unsigned int vf_id,\n+\t\t\t       void *data,\n+\t\t\t       int len);\n+\n+/**\n+ * dlb2_pf_write_vf_mbox_req() - (PF only) write a PF->VF mailbox request\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vf_id: VF ID.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the user-provided message data into of the PF's VF->PF\n+ * mailboxes.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_PF2VF_REQ_BYTES.\n+ */\n+int dlb2_pf_write_vf_mbox_req(struct dlb2_hw *hw,\n+\t\t\t      unsigned int vf_id,\n+\t\t\t      void *data,\n+\t\t\t      int len);\n+\n+/**\n+ * dlb2_vf_read_pf_mbox_resp() - (VF only) read a PF->VF mailbox response\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the VF's PF->VF mailbox into the array pointed to by\n+ * data.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_PF2VF_RESP_BYTES.\n+ */\n+int dlb2_vf_read_pf_mbox_resp(struct dlb2_hw *hw, void *data, int len);\n+\n+/**\n+ * dlb2_vf_read_pf_mbox_req() - (VF only) read a PF->VF mailbox request\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the VF's PF->VF mailbox into the array pointed to by\n+ * data.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_PF2VF_REQ_BYTES.\n+ */\n+int dlb2_vf_read_pf_mbox_req(struct dlb2_hw *hw, void *data, int len);\n+\n+/**\n+ * dlb2_vf_write_pf_mbox_req() - (VF only) write a VF->PF mailbox request\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the user-provided message data into of the VF's PF->VF\n+ * mailboxes.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_VF2PF_REQ_BYTES.\n+ */\n+int dlb2_vf_write_pf_mbox_req(struct dlb2_hw *hw, void *data, int len);\n+\n+/**\n+ * dlb2_vf_write_pf_mbox_resp() - (VF only) write a VF->PF mailbox response\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @data: pointer to message data.\n+ * @len: size, in bytes, of the data array.\n+ *\n+ * This function copies the user-provided message data into of the VF's PF->VF\n+ * mailboxes.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - len >= DLB2_VF2PF_RESP_BYTES.\n+ */\n+int dlb2_vf_write_pf_mbox_resp(struct dlb2_hw *hw, void *data, int len);\n+\n+/**\n+ * dlb2_reset_vdev() - reset the hardware owned by a virtual device\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function resets the hardware owned by a vdev, by resetting the vdev's\n+ * domains one by one.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+int dlb2_reset_vdev(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_vdev_is_locked() - check whether the vdev's resources are locked\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function returns whether or not the vdev's resource assignments are\n+ * locked. If locked, no resources can be added to or subtracted from the\n+ * group.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+bool dlb2_vdev_is_locked(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_lock_vdev() - lock the vdev's resources\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function sets a flag indicating that the vdev is using its resources.\n+ * When the vdev is locked, its resource assignment cannot be changed.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_lock_vdev(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_unlock_vdev() - unlock the vdev's resources\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function unlocks the vdev's resource assignment, allowing it to be\n+ * modified.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ */\n+void dlb2_unlock_vdev(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_update_vdev_sched_domains() - update the domains assigned to a vdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of scheduling domains to assign to this vdev\n+ *\n+ * This function assigns num scheduling domains to the specified vdev. If the\n+ * vdev already has domains assigned, this existing assignment is adjusted\n+ * accordingly.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_sched_domains(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_ldb_queues() - update the LDB queues assigned to a vdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of LDB queues to assign to this vdev\n+ *\n+ * This function assigns num LDB queues to the specified vdev. If the vdev\n+ * already has LDB queues assigned, this existing assignment is adjusted\n+ * accordingly.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_ldb_queues(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_ldb_ports() - update the LDB ports assigned to a vdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of LDB ports to assign to this vdev\n+ *\n+ * This function assigns num LDB ports to the specified vdev. If the vdev\n+ * already has LDB ports assigned, this existing assignment is adjusted\n+ * accordingly.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_ldb_ports(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_ldb_cos_ports() - update the LDB ports assigned to a vdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @cos: class-of-service ID\n+ * @num: number of LDB ports to assign to this vdev\n+ *\n+ * This function assigns num LDB ports from class-of-service cos to the\n+ * specified vdev. If the vdev already has LDB ports from this class-of-service\n+ * assigned, this existing assignment is adjusted accordingly.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_ldb_cos_ports(struct dlb2_hw *hw,\n+\t\t\t\t   u32 id,\n+\t\t\t\t   u32 cos,\n+\t\t\t\t   u32 num);\n+\n+/**\n+ * dlb2_update_vdev_dir_ports() - update the DIR ports assigned to a vdev\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of DIR ports to assign to this vdev\n+ *\n+ * This function assigns num DIR ports to the specified vdev. If the vdev\n+ * already has DIR ports assigned, this existing assignment is adjusted\n+ * accordingly.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_dir_ports(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_ldb_credits() - update the vdev's assigned LDB credits\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of LDB credit credits to assign to this vdev\n+ *\n+ * This function assigns num LDB credit to the specified vdev. If the vdev\n+ * already has LDB credits assigned, this existing assignment is adjusted\n+ * accordingly. vdevs are assigned a contiguous chunk of credits, so this\n+ * function may fail if a sufficiently large contiguous chunk is not available.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_ldb_credits(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_dir_credits() - update the vdev's assigned DIR credits\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of DIR credits to assign to this vdev\n+ *\n+ * This function assigns num DIR credit to the specified vdev. If the vdev\n+ * already has DIR credits assigned, this existing assignment is adjusted\n+ * accordingly. vdevs are assigned a contiguous chunk of credits, so this\n+ * function may fail if a sufficiently large contiguous chunk is not available.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_dir_credits(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_hist_list_entries() - update the vdev's assigned HL entries\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of history list entries to assign to this vdev\n+ *\n+ * This function assigns num history list entries to the specified vdev. If the\n+ * vdev already has history list entries assigned, this existing assignment is\n+ * adjusted accordingly. vdevs are assigned a contiguous chunk of entries, so\n+ * this function may fail if a sufficiently large contiguous chunk is not\n+ * available.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_hist_list_entries(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_update_vdev_atomic_inflights() - update the vdev's atomic inflights\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ * @num: number of atomic inflights to assign to this vdev\n+ *\n+ * This function assigns num atomic inflights to the specified vdev. If the vdev\n+ * already has atomic inflights assigned, this existing assignment is adjusted\n+ * accordingly. vdevs are assigned a contiguous chunk of entries, so this\n+ * function may fail if a sufficiently large contiguous chunk is not available.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid, or the requested number of resources are\n+ *\t    unavailable.\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_update_vdev_atomic_inflights(struct dlb2_hw *hw, u32 id, u32 num);\n+\n+/**\n+ * dlb2_reset_vdev_resources() - reassign the vdev's resources to the PF\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function takes any resources currently assigned to the vdev and\n+ * reassigns them to the PF.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - id is invalid\n+ * EPERM  - The vdev's resource assignment is locked and cannot be changed.\n+ */\n+int dlb2_reset_vdev_resources(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_notify_vf() - send an alarm to a VF\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vf_id: VF ID\n+ * @notification: notification\n+ *\n+ * This function sends a notification (as defined in dlb2_mbox.h) to a VF.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 if the VF doesn't ACK the PF->VF interrupt.\n+ */\n+int dlb2_notify_vf(struct dlb2_hw *hw,\n+\t\t   unsigned int vf_id,\n+\t\t   u32 notification);\n+\n+/**\n+ * dlb2_vdev_in_use() - query whether a virtual device is in use\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual device ID\n+ *\n+ * This function sends a mailbox request to the vdev to query whether the vdev\n+ * is in use.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 for false, 1 for true, and <0 if the mailbox request times out or\n+ * an internal error occurs.\n+ */\n+int dlb2_vdev_in_use(struct dlb2_hw *hw, unsigned int id);\n+\n+/**\n+ * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * Clearing the PMCSR must be done at initialization to make the device fully\n+ * operational.\n+ */\n+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_get_ldb_queue_depth() - returns the depth of a load-balanced queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue depth args\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns the depth of a load-balanced queue.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the depth.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid domain ID or queue ID.\n+ */\n+int dlb2_hw_get_ldb_queue_depth(struct dlb2_hw *hw,\n+\t\t\t\tu32 domain_id,\n+\t\t\t\tstruct dlb2_get_ldb_queue_depth_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp,\n+\t\t\t\tbool vdev_request,\n+\t\t\t\tunsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_get_dir_queue_depth() - returns the depth of a directed queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue depth args\n+ * @resp: response structure.\n+ * @vdev_request: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * This function returns the depth of a directed queue.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the depth.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid domain ID or queue ID.\n+ */\n+int dlb2_hw_get_dir_queue_depth(struct dlb2_hw *hw,\n+\t\t\t\tu32 domain_id,\n+\t\t\t\tstruct dlb2_get_dir_queue_depth_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp,\n+\t\t\t\tbool vdev_request,\n+\t\t\t\tunsigned int vdev_id);\n+\n+enum dlb2_virt_mode {\n+\tDLB2_VIRT_NONE,\n+\tDLB2_VIRT_SRIOV,\n+\tDLB2_VIRT_SIOV,\n+\n+\t/* NUM_DLB2_VIRT_MODES must be last */\n+\tNUM_DLB2_VIRT_MODES,\n+};\n+\n+/**\n+ * dlb2_hw_set_virt_mode() - set the device's virtualization mode\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @mode: either none, SR-IOV, or Scalable IOV.\n+ *\n+ * This function sets the virtualization mode of the device. This controls\n+ * whether the device uses a software or hardware mailbox.\n+ *\n+ * This should be called by the PF driver when either SR-IOV or Scalable IOV is\n+ * selected as the virtualization mechanism, and by the VF/VDEV driver during\n+ * initialization after recognizing itself as an SR-IOV or Scalable IOV device.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid mode.\n+ */\n+int dlb2_hw_set_virt_mode(struct dlb2_hw *hw, enum dlb2_virt_mode mode);\n+\n+/**\n+ * dlb2_hw_get_virt_mode() - get the device's virtualization mode\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function gets the virtualization mode of the device.\n+ */\n+enum dlb2_virt_mode dlb2_hw_get_virt_mode(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_get_ldb_port_phys_id() - get a physical port ID from its virt ID\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual port ID.\n+ * @vdev_id: vdev ID.\n+ *\n+ * Return:\n+ * Returns >= 0 upon success, -1 otherwise.\n+ */\n+s32 dlb2_hw_get_ldb_port_phys_id(struct dlb2_hw *hw,\n+\t\t\t\t u32 id,\n+\t\t\t\t unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_get_dir_port_phys_id() - get a physical port ID from its virt ID\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: virtual port ID.\n+ * @vdev_id: vdev ID.\n+ *\n+ * Return:\n+ * Returns >= 0 upon success, -1 otherwise.\n+ */\n+s32 dlb2_hw_get_dir_port_phys_id(struct dlb2_hw *hw,\n+\t\t\t\t u32 id,\n+\t\t\t\t unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_register_sw_mbox() - register a software mailbox\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ * @vdev2pf_mbox: pointer to a 4KB memory page used for vdev->PF communication.\n+ * @pf2vdev_mbox: pointer to a 4KB memory page used for PF->vdev communication.\n+ * @pf2vdev_inject: callback function for injecting a PF->vdev interrupt.\n+ * @inject_arg: user argument for pf2vdev_inject callback.\n+ *\n+ * When Scalable IOV is enabled, the VDCM must register a software mailbox for\n+ * every virtual device during vdev creation.\n+ *\n+ * This function notifies the driver to use a software mailbox using the\n+ * provided pointers, instead of the device's hardware mailbox. When the driver\n+ * calls mailbox functions like dlb2_pf_write_vf_mbox_req(), the request will\n+ * go to the software mailbox instead of the hardware one. This is used in\n+ * Scalable IOV virtualization.\n+ */\n+void dlb2_hw_register_sw_mbox(struct dlb2_hw *hw,\n+\t\t\t      unsigned int vdev_id,\n+\t\t\t      u32 *vdev2pf_mbox,\n+\t\t\t      u32 *pf2vdev_mbox,\n+\t\t\t      void (*pf2vdev_inject)(void *),\n+\t\t\t      void *inject_arg);\n+\n+/**\n+ * dlb2_hw_unregister_sw_mbox() - unregister a software mailbox\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ *\n+ * This function notifies the driver to stop using a previously registered\n+ * software mailbox.\n+ */\n+void dlb2_hw_unregister_sw_mbox(struct dlb2_hw *hw, unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_setup_cq_ims_entry() - setup a CQ's IMS entry\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ * @virt_cq_id: virtual CQ ID.\n+ * @is_ldb: CQ is load-balanced.\n+ * @addr_lo: least-significant 32 bits of address.\n+ * @data: 32 data bits.\n+ *\n+ * This sets up the CQ's IMS entry with the provided address and data values.\n+ * This function should only be called if the device is configured for Scalable\n+ * IOV virtualization. The upper 32 address bits are fixed in hardware and thus\n+ * not needed.\n+ */\n+void dlb2_hw_setup_cq_ims_entry(struct dlb2_hw *hw,\n+\t\t\t\tunsigned int vdev_id,\n+\t\t\t\tu32 virt_cq_id,\n+\t\t\t\tbool is_ldb,\n+\t\t\t\tu32 addr_lo,\n+\t\t\t\tu32 data);\n+\n+/**\n+ * dlb2_hw_clear_cq_ims_entry() - clear a CQ's IMS entry\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ * @virt_cq_id: virtual CQ ID.\n+ * @is_ldb: CQ is load-balanced.\n+ *\n+ * This clears the CQ's IMS entry, reverting it to its reset state.\n+ */\n+void dlb2_hw_clear_cq_ims_entry(struct dlb2_hw *hw,\n+\t\t\t\tunsigned int vdev_id,\n+\t\t\t\tu32 virt_cq_id,\n+\t\t\t\tbool is_ldb);\n+\n+/**\n+ * dlb2_hw_register_pasid() - register a vdev's PASID\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @vdev_id: vdev ID.\n+ * @pasid: the vdev's PASID.\n+ *\n+ * This function stores the user-supplied PASID, and uses it when configuring\n+ * the vdev's CQs.\n+ *\n+ * Return:\n+ * Returns >= 0 upon success, -1 otherwise.\n+ */\n+int dlb2_hw_register_pasid(struct dlb2_hw *hw,\n+\t\t\t   unsigned int vdev_id,\n+\t\t\t   unsigned int pasid);\n+\n+/**\n+ * dlb2_hw_pending_port_unmaps() - returns the number of unmap operations in\n+ *\tprogress.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: number of unmaps in progress args\n+ * @resp: response structure.\n+ * @vf_request: indicates whether this request came from a VF.\n+ * @vf_id: If vf_request is true, this contains the VF's ID.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the number of unmaps in progress.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid port ID.\n+ */\n+int dlb2_hw_pending_port_unmaps(struct dlb2_hw *hw,\n+\t\t\t\tu32 domain_id,\n+\t\t\t\tstruct dlb2_pending_port_unmaps_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp,\n+\t\t\t\tbool vf_request,\n+\t\t\t\tunsigned int vf_id);\n+\n+/**\n+ * dlb2_hw_get_cos_bandwidth() - returns the percent of bandwidth allocated\n+ *\tto a port class-of-service.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @cos_id: class-of-service ID.\n+ *\n+ * Return:\n+ * Returns -EINVAL if cos_id is invalid, else the class' bandwidth allocation.\n+ */\n+int dlb2_hw_get_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id);\n+\n+/**\n+ * dlb2_hw_set_cos_bandwidth() - set a bandwidth allocation percentage for a\n+ *\tport class-of-service.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @cos_id: class-of-service ID.\n+ * @bandwidth: class-of-service bandwidth.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid cos ID, bandwidth is greater than 100, or bandwidth would\n+ *\t    cause the total bandwidth across all classes of service to exceed\n+ *\t    100%.\n+ */\n+int dlb2_hw_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bandwidth);\n+\n+enum dlb2_wd_tmo {\n+\t/* 40s watchdog timeout */\n+\tDLB2_WD_TMO_40S,\n+\t/* 10s watchdog timeout */\n+\tDLB2_WD_TMO_10S,\n+\t/* 1s watchdog timeout */\n+\tDLB2_WD_TMO_1S,\n+\n+\t/* Must be last */\n+\tNUM_DLB2_WD_TMOS,\n+};\n+\n+/**\n+ * dlb2_hw_enable_wd_timer() - enable the CQ watchdog timers with a\n+ *\tcaller-specified timeout.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @tmo: watchdog timeout.\n+ *\n+ * This function should be called during device initialization and after reset.\n+ * The watchdog timer interrupt must also be enabled per-CQ, using either\n+ * dlb2_hw_enable_dir_cq_wd_int() or dlb2_hw_enable_ldb_cq_wd_int().\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid timeout.\n+ */\n+int dlb2_hw_enable_wd_timer(struct dlb2_hw *hw, enum dlb2_wd_tmo tmo);\n+\n+/**\n+ * dlb2_hw_enable_dir_cq_wd_int() - enable the CQ watchdog interrupt on an\n+ *\tindividual CQ.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: port ID.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid directed port ID.\n+ */\n+int dlb2_hw_enable_dir_cq_wd_int(struct dlb2_hw *hw,\n+\t\t\t\t u32 id,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_enable_ldb_cq_wd_int() - enable the CQ watchdog interrupt on an\n+ *\tindividual CQ.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @id: port ID.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_request is true, this contains the vdev's ID.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid load-balanced port ID.\n+ */\n+int dlb2_hw_enable_ldb_cq_wd_int(struct dlb2_hw *hw,\n+\t\t\t\t u32 id,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id);\n+\n+/**\n+ * dlb2_hw_enable_sparse_ldb_cq_mode() - enable sparse mode for load-balanced\n+ *\tports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_enable_sparse_dir_cq_mode() - enable sparse mode for directed ports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_hw_set_qe_arbiter_weights() - program QE arbiter weights\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @weight: 8-entry array of arbiter weights.\n+ *\n+ * weight[N] programs priority N's weight. In cases where the 8 priorities are\n+ * reduced to 4 bins, the mapping is:\n+ * - weight[1] programs bin 0\n+ * - weight[3] programs bin 1\n+ * - weight[5] programs bin 2\n+ * - weight[7] programs bin 3\n+ */\n+void dlb2_hw_set_qe_arbiter_weights(struct dlb2_hw *hw, u8 weight[8]);\n+\n+/**\n+ * dlb2_hw_set_qid_arbiter_weights() - program QID arbiter weights\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @weight: 8-entry array of arbiter weights.\n+ *\n+ * weight[N] programs priority N's weight. In cases where the 8 priorities are\n+ * reduced to 4 bins, the mapping is:\n+ * - weight[1] programs bin 0\n+ * - weight[3] programs bin 1\n+ * - weight[5] programs bin 2\n+ * - weight[7] programs bin 3\n+ */\n+void dlb2_hw_set_qid_arbiter_weights(struct dlb2_hw *hw, u8 weight[8]);\n+\n+/**\n+ * dlb2_hw_ldb_cq_interrupt_enabled() - Check if the interrupt is enabled\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: physical load-balanced port ID.\n+ *\n+ * This function returns whether the load-balanced CQ interrupt is enabled.\n+ */\n+int dlb2_hw_ldb_cq_interrupt_enabled(struct dlb2_hw *hw, int port_id);\n+\n+/**\n+ * dlb2_hw_ldb_cq_interrupt_set_mode() - Program the CQ interrupt mode\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: physical load-balanced port ID.\n+ * @mode: interrupt type (DLB2_CQ_ISR_MODE_{DIS, MSI, MSIX, ADI})\n+ *\n+ * This function can be used to disable (MODE_DIS) and re-enable the\n+ * load-balanced CQ's interrupt. It should only be called after the interrupt\n+ * has been configured with dlb2_configure_ldb_cq_interrupt().\n+ */\n+void dlb2_hw_ldb_cq_interrupt_set_mode(struct dlb2_hw *hw,\n+\t\t\t\t       int port_id,\n+\t\t\t\t       int mode);\n+\n+/**\n+ * dlb2_hw_dir_cq_interrupt_enabled() - Check if the interrupt is enabled\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: physical load-balanced port ID.\n+ *\n+ * This function returns whether the load-balanced CQ interrupt is enabled.\n+ */\n+int dlb2_hw_dir_cq_interrupt_enabled(struct dlb2_hw *hw, int port_id);\n+\n+/**\n+ * dlb2_hw_dir_cq_interrupt_set_mode() - Program the CQ interrupt mode\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port_id: physical directed port ID.\n+ * @mode: interrupt type (DLB2_CQ_ISR_MODE_{DIS, MSI, MSIX, ADI})\n+ *\n+ * This function can be used to disable (MODE_DIS) and re-enable the\n+ * directed CQ's interrupt. It should only be called after the interrupt\n+ * has been configured with dlb2_configure_dir_cq_interrupt().\n+ */\n+void dlb2_hw_dir_cq_interrupt_set_mode(struct dlb2_hw *hw,\n+\t\t\t\t       int port_id,\n+\t\t\t\t       int mode);\n+\n+#endif /* __DLB2_RESOURCE_H */\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nnew file mode 100644\nindex 0000000..1c275ff\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -0,0 +1,620 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+\n+#include \"base/dlb2_resource.h\"\n+#include \"base/dlb2_osdep.h\"\n+#include \"base/dlb2_regs.h\"\n+#include \"dlb2_main.h\"\n+#include \"../dlb2_user.h\"\n+#include \"../dlb2_priv.h\"\n+#include \"../dlb2_iface.h\"\n+#include \"../dlb2_inline_fns.h\"\n+\n+#define PF_ID_ZERO 0\t/* PF ONLY! */\n+#define NO_OWNER_VF 0\t/* PF ONLY! */\n+#define NOT_VF_REQ false /* PF ONLY! */\n+\n+#define DLB2_PCI_CFG_SPACE_SIZE 256\n+#define DLB2_PCI_CAP_POINTER 0x34\n+#define DLB2_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC)\n+#define DLB2_PCI_CAP_ID(hdr) ((hdr) & 0xFF)\n+#define DLB2_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC)\n+#define DLB2_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF)\n+#define DLB2_PCI_EXT_CAP_ID_ERR 1\n+#define DLB2_PCI_ERR_UNCOR_MASK 8\n+#define DLB2_PCI_ERR_UNC_UNSUP  0x00100000\n+\n+#define DLB2_PCI_EXP_DEVCTL 8\n+#define DLB2_PCI_LNKCTL 16\n+#define DLB2_PCI_SLTCTL 24\n+#define DLB2_PCI_RTCTL 28\n+#define DLB2_PCI_EXP_DEVCTL2 40\n+#define DLB2_PCI_LNKCTL2 48\n+#define DLB2_PCI_SLTCTL2 56\n+#define DLB2_PCI_CMD 4\n+#define DLB2_PCI_X_CMD 2\n+#define DLB2_PCI_EXP_DEVSTA 10\n+#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20\n+#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000\n+\n+#define DLB2_PCI_CAP_ID_EXP       0x10\n+#define DLB2_PCI_CAP_ID_MSIX      0x11\n+#define DLB2_PCI_EXT_CAP_ID_PAS   0x1B\n+#define DLB2_PCI_EXT_CAP_ID_PRI   0x13\n+#define DLB2_PCI_EXT_CAP_ID_ACS   0xD\n+\n+#define DLB2_PCI_PRI_CTRL_ENABLE         0x1\n+#define DLB2_PCI_PRI_ALLOC_REQ           0xC\n+#define DLB2_PCI_PRI_CTRL                0x4\n+#define DLB2_PCI_MSIX_FLAGS              0x2\n+#define DLB2_PCI_MSIX_FLAGS_ENABLE       0x8000\n+#define DLB2_PCI_MSIX_FLAGS_MASKALL      0x4000\n+#define DLB2_PCI_ERR_ROOT_STATUS         0x30\n+#define DLB2_PCI_ERR_COR_STATUS          0x10\n+#define DLB2_PCI_ERR_UNCOR_STATUS        0x4\n+#define DLB2_PCI_COMMAND_INTX_DISABLE    0x400\n+#define DLB2_PCI_ACS_CAP                 0x4\n+#define DLB2_PCI_ACS_CTRL                0x6\n+#define DLB2_PCI_ACS_SV                  0x1\n+#define DLB2_PCI_ACS_RR                  0x4\n+#define DLB2_PCI_ACS_CR                  0x8\n+#define DLB2_PCI_ACS_UF                  0x10\n+#define DLB2_PCI_ACS_EC                  0x20\n+\n+static int\n+dlb2_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)\n+{\n+\tuint32_t hdr;\n+\tsize_t sz;\n+\tint pos;\n+\n+\tpos = DLB2_PCI_CFG_SPACE_SIZE;\n+\tsz = sizeof(hdr);\n+\n+\twhile (pos > 0xFF) {\n+\t\tif (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz)\n+\t\t\treturn -1;\n+\n+\t\tif (DLB2_PCI_EXT_CAP_ID(hdr) == id)\n+\t\t\treturn pos;\n+\n+\t\tpos = DLB2_PCI_EXT_CAP_NEXT(hdr);\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)\n+{\n+\tuint8_t pos;\n+\tint ret;\n+\tuint16_t hdr;\n+\n+\tret = rte_pci_read_config(pdev, &pos, 1, DLB2_PCI_CAP_POINTER);\n+\tpos &= 0xFC;\n+\n+\tif (ret != 1)\n+\t\treturn -1;\n+\n+\twhile (pos > 0x3F) {\n+\t\tret = rte_pci_read_config(pdev, &hdr, 2, pos);\n+\t\tif (ret != 2)\n+\t\t\treturn -1;\n+\n+\t\tif (DLB2_PCI_CAP_ID(hdr) == id)\n+\t\t\treturn pos;\n+\n+\t\tif (DLB2_PCI_CAP_ID(hdr) == 0xFF)\n+\t\t\treturn -1;\n+\n+\t\tpos = DLB2_PCI_CAP_NEXT(hdr);\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static int\n+dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)\n+{\n+\tint i;\n+\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIR64B))\n+\t\tdlb2_dev->enqueue_four = dlb2_movdir64b;\n+\telse\n+\t\tdlb2_dev->enqueue_four = dlb2_movntdq;\n+\n+\t/* Initialize software state */\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++)\n+\t\tdlb2_list_init_head(&dlb2_dev->ldb_port_pages[i].list);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS; i++)\n+\t\tdlb2_list_init_head(&dlb2_dev->dir_port_pages[i].list);\n+\n+\trte_spinlock_init(&dlb2_dev->resource_mutex);\n+\trte_spinlock_init(&dlb2_dev->measurement_lock);\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_pf_enable_pm(struct dlb2_dev *dlb2_dev)\n+{\n+\tdlb2_clr_pmcsr_disable(&dlb2_dev->hw);\n+}\n+\n+#define DLB2_READY_RETRY_LIMIT 1000\n+static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev)\n+{\n+\tu32 retries = 0;\n+\n+\t/* Allow at least 1s for the device to become active after power-on */\n+\tfor (retries = 0; retries < DLB2_READY_RETRY_LIMIT; retries++) {\n+\t\tunion dlb2_cfg_mstr_cfg_diagnostic_idle_status idle;\n+\t\tunion dlb2_cfg_mstr_cfg_pm_status pm_st;\n+\t\tu32 addr;\n+\n+\t\taddr = DLB2_CFG_MSTR_CFG_PM_STATUS;\n+\t\tpm_st.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n+\t\taddr = DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS;\n+\t\tidle.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n+\t\tif (pm_st.field.pmsm == 1 && idle.field.dlb_func_idle == 1)\n+\t\t\tbreak;\n+\n+\t\trte_delay_ms(1);\n+\t};\n+\n+\tif (retries == DLB2_READY_RETRY_LIMIT) {\n+\t\tprintf(\"[%s()] wait for device ready timed out\\n\",\n+\t\t       __func__);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+struct dlb2_dev *\n+dlb2_probe(struct rte_pci_device *pdev)\n+{\n+\tstruct dlb2_dev *dlb2_dev;\n+\tint ret = 0;\n+\n+\tDLB2_INFO(dlb2_dev, \"probe\\n\");\n+\n+\tdlb2_dev = rte_malloc(\"DLB2_PF\", sizeof(struct dlb2_dev),\n+\t\t\t      RTE_CACHE_LINE_SIZE);\n+\n+\tif (!dlb2_dev) {\n+\t\tret = -ENOMEM;\n+\t\tgoto dlb2_dev_malloc_fail;\n+\t}\n+\n+\t/* PCI Bus driver has already mapped bar space into process.\n+\t * Save off our IO register and FUNC addresses.\n+\t */\n+\n+\t/* BAR 0 */\n+\tif (pdev->mem_resource[0].addr == NULL) {\n+\t\tDLB2_ERR(dlb2_dev, \"probe: BAR 0 addr (csr_kva) is NULL\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto pci_mmap_bad_addr;\n+\t}\n+\tdlb2_dev->hw.func_kva = (void *)(uintptr_t)pdev->mem_resource[0].addr;\n+\tdlb2_dev->hw.func_phys_addr = pdev->mem_resource[0].phys_addr;\n+\n+\tDLB2_INFO(dlb2_dev, \"DLB2 FUNC VA=%p, PA=%p, len=%p\\n\",\n+\t\t  (void *)dlb2_dev->hw.func_kva,\n+\t\t  (void *)dlb2_dev->hw.func_phys_addr,\n+\t\t  (void *)(pdev->mem_resource[0].len));\n+\n+\t/* BAR 2 */\n+\tif (pdev->mem_resource[2].addr == NULL) {\n+\t\tDLB2_ERR(dlb2_dev, \"probe: BAR 2 addr (func_kva) is NULL\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto pci_mmap_bad_addr;\n+\t}\n+\tdlb2_dev->hw.csr_kva = (void *)(uintptr_t)pdev->mem_resource[2].addr;\n+\tdlb2_dev->hw.csr_phys_addr = pdev->mem_resource[2].phys_addr;\n+\n+\tDLB2_INFO(dlb2_dev, \"DLB2 CSR VA=%p, PA=%p, len=%p\\n\",\n+\t\t  (void *)dlb2_dev->hw.csr_kva,\n+\t\t  (void *)dlb2_dev->hw.csr_phys_addr,\n+\t\t  (void *)(pdev->mem_resource[2].len));\n+\n+\tdlb2_dev->pdev = pdev;\n+\n+\t/* PM enable must be done before any other MMIO accesses, and this\n+\t * setting is persistent across device reset.\n+\t */\n+\tdlb2_pf_enable_pm(dlb2_dev);\n+\n+\tret = dlb2_pf_wait_for_device_ready(dlb2_dev);\n+\tif (ret)\n+\t\tgoto wait_for_device_ready_fail;\n+\n+\tret = dlb2_pf_reset(dlb2_dev);\n+\tif (ret)\n+\t\tgoto dlb2_reset_fail;\n+\n+\tret = dlb2_pf_init_driver_state(dlb2_dev);\n+\tif (ret)\n+\t\tgoto init_driver_state_fail;\n+\n+\tret = dlb2_resource_init(&dlb2_dev->hw);\n+\tif (ret)\n+\t\tgoto resource_init_fail;\n+\n+\treturn dlb2_dev;\n+\n+resource_init_fail:\n+\tdlb2_resource_free(&dlb2_dev->hw);\n+init_driver_state_fail:\n+dlb2_reset_fail:\n+pci_mmap_bad_addr:\n+wait_for_device_ready_fail:\n+\trte_free(dlb2_dev);\n+dlb2_dev_malloc_fail:\n+\trte_errno = ret;\n+\treturn NULL;\n+}\n+\n+int\n+dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n+{\n+\tint ret = 0;\n+\tint i = 0;\n+\tuint32_t dword[16];\n+\tuint16_t cmd;\n+\toff_t off;\n+\n+\tuint16_t dev_ctl_word;\n+\tuint16_t dev_ctl2_word;\n+\tuint16_t lnk_word;\n+\tuint16_t lnk_word2;\n+\tuint16_t slt_word;\n+\tuint16_t slt_word2;\n+\tuint16_t rt_ctl_word;\n+\tuint32_t pri_reqs_dword;\n+\tuint16_t pri_ctrl_word;\n+\n+\tint pcie_cap_offset;\n+\tint pri_cap_offset;\n+\tint msix_cap_offset;\n+\tint err_cap_offset;\n+\tint acs_cap_offset;\n+\tint wait_count;\n+\n+\tuint16_t devsta_busy_word;\n+\tuint16_t devctl_word;\n+\n+\tstruct rte_pci_device *pdev = dlb2_dev->pdev;\n+\n+\t/* Save PCI config state */\n+\n+\tfor (i = 0; i < 16; i++) {\n+\t\tif (rte_pci_read_config(pdev, &dword[i], 4, i * 4) != 4)\n+\t\t\treturn ret;\n+\t}\n+\n+\tpcie_cap_offset = dlb2_pci_find_capability(pdev, DLB2_PCI_CAP_ID_EXP);\n+\n+\tif (pcie_cap_offset < 0) {\n+\t\tprintf(\"[%s()] failed to find the pcie capability\\n\",\n+\t\t       __func__);\n+\t\treturn pcie_cap_offset;\n+\t}\n+\n+\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;\n+\tif (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)\n+\t\tdev_ctl_word = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_LNKCTL;\n+\tif (rte_pci_read_config(pdev, &lnk_word, 2, off) != 2)\n+\t\tlnk_word = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_SLTCTL;\n+\tif (rte_pci_read_config(pdev, &slt_word, 2, off) != 2)\n+\t\tslt_word = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_RTCTL;\n+\tif (rte_pci_read_config(pdev, &rt_ctl_word, 2, off) != 2)\n+\t\trt_ctl_word = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;\n+\tif (rte_pci_read_config(pdev, &dev_ctl2_word, 2, off) != 2)\n+\t\tdev_ctl2_word = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_LNKCTL2;\n+\tif (rte_pci_read_config(pdev, &lnk_word2, 2, off) != 2)\n+\t\tlnk_word2 = 0;\n+\n+\toff = pcie_cap_offset + DLB2_PCI_SLTCTL2;\n+\tif (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)\n+\t\tslt_word2 = 0;\n+\n+\toff = DLB2_PCI_EXT_CAP_ID_PRI;\n+\tpri_cap_offset = dlb2_pci_find_ext_capability(pdev, off);\n+\n+\tif (pri_cap_offset >= 0) {\n+\t\toff = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;\n+\t\tif (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) != 4)\n+\t\t\tpri_reqs_dword = 0;\n+\t}\n+\n+\t/* clear the PCI command register before issuing the FLR */\n+\n+\toff = DLB2_PCI_CMD;\n+\tcmd = 0;\n+\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\tprintf(\"[%s()] failed to write the pci command\\n\",\n+\t\t       __func__);\n+\t\treturn ret;\n+\t}\n+\n+\t/* issue the FLR */\n+\tfor (wait_count = 0; wait_count < 4; wait_count++) {\n+\t\tint sleep_time;\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVSTA;\n+\t\tret = rte_pci_read_config(pdev, &devsta_busy_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to read the pci device status\\n\",\n+\t\t\t       __func__);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (!(devsta_busy_word & DLB2_PCI_EXP_DEVSTA_TRPND))\n+\t\t\tbreak;\n+\n+\t\tsleep_time = (1 << (wait_count)) * 100;\n+\t\trte_delay_ms(sleep_time);\n+\t}\n+\n+\tif (wait_count == 4) {\n+\t\tprintf(\"[%s()] wait for pci pending transactions timed out\\n\",\n+\t\t       __func__);\n+\t\treturn -1;\n+\t}\n+\n+\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;\n+\tret = rte_pci_read_config(pdev, &devctl_word, 2, off);\n+\tif (ret != 2) {\n+\t\tprintf(\"[%s()] failed to read the pcie device control\\n\",\n+\t\t       __func__);\n+\t\treturn ret;\n+\t}\n+\n+\tdevctl_word |= DLB2_PCI_EXP_DEVCTL_BCR_FLR;\n+\n+\tret = rte_pci_write_config(pdev, &devctl_word, 2, off);\n+\tif (ret != 2) {\n+\t\tprintf(\"[%s()] failed to write the pcie device control\\n\",\n+\t\t       __func__);\n+\t\treturn ret;\n+\t}\n+\n+\trte_delay_ms(100);\n+\n+\t/* Restore PCI config state */\n+\n+\tif (pcie_cap_offset >= 0) {\n+\t\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;\n+\t\tret = rte_pci_write_config(pdev, &dev_ctl_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie device control at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_LNKCTL;\n+\t\tret = rte_pci_write_config(pdev, &lnk_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_SLTCTL;\n+\t\tret = rte_pci_write_config(pdev, &slt_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_RTCTL;\n+\t\tret = rte_pci_write_config(pdev, &rt_ctl_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;\n+\t\tret = rte_pci_write_config(pdev, &dev_ctl2_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_LNKCTL2;\n+\t\tret = rte_pci_write_config(pdev, &lnk_word2, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB2_PCI_SLTCTL2;\n+\t\tret = rte_pci_write_config(pdev, &slt_word2, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tif (pri_cap_offset >= 0) {\n+\t\tpri_ctrl_word = DLB2_PCI_PRI_CTRL_ENABLE;\n+\n+\t\toff = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;\n+\t\tret = rte_pci_write_config(pdev, &pri_reqs_dword, 4, off);\n+\t\tif (ret != 4) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = pri_cap_offset + DLB2_PCI_PRI_CTRL;\n+\t\tret = rte_pci_write_config(pdev, &pri_ctrl_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\toff = DLB2_PCI_EXT_CAP_ID_ERR;\n+\terr_cap_offset = dlb2_pci_find_ext_capability(pdev, off);\n+\n+\tif (err_cap_offset >= 0) {\n+\t\tuint32_t tmp;\n+\n+\t\toff = err_cap_offset + DLB2_PCI_ERR_ROOT_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tret = rte_pci_write_config(pdev, &tmp, 4, off);\n+\t\tif (ret != 4) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = err_cap_offset + DLB2_PCI_ERR_COR_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tret = rte_pci_write_config(pdev, &tmp, 4, off);\n+\t\tif (ret != 4) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = err_cap_offset + DLB2_PCI_ERR_UNCOR_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tret = rte_pci_write_config(pdev, &tmp, 4, off);\n+\t\tif (ret != 4) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tfor (i = 16; i > 0; i--) {\n+\t\toff = (i - 1) * 4;\n+\t\tret = rte_pci_write_config(pdev, &dword[i - 1], 4, off);\n+\t\tif (ret != 4) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\toff = DLB2_PCI_CMD;\n+\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\tcmd &= ~DLB2_PCI_COMMAND_INTX_DISABLE;\n+\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pci command\\n\",\n+\t\t\t       __func__);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmsix_cap_offset = dlb2_pci_find_capability(pdev,\n+\t\t\t\t\t\t   DLB2_PCI_CAP_ID_MSIX);\n+\tif (msix_cap_offset >= 0) {\n+\t\toff = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;\n+\t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\t\tcmd |= DLB2_PCI_MSIX_FLAGS_ENABLE;\n+\t\t\tcmd |= DLB2_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\t\tprintf(\"[%s()] failed to write msix flags\\n\",\n+\t\t\t\t       __func__);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\toff = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;\n+\t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\t\tcmd &= ~DLB2_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\t\tprintf(\"[%s()] failed to write msix flags\\n\",\n+\t\t\t\t       __func__);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\toff = DLB2_PCI_EXT_CAP_ID_ACS;\n+\tacs_cap_offset = dlb2_pci_find_ext_capability(pdev, off);\n+\n+\tif (acs_cap_offset >= 0) {\n+\t\tuint16_t acs_cap, acs_ctrl, acs_mask;\n+\t\toff = acs_cap_offset + DLB2_PCI_ACS_CAP;\n+\t\tif (rte_pci_read_config(pdev, &acs_cap, 2, off) != 2)\n+\t\t\tacs_cap = 0;\n+\n+\t\toff = acs_cap_offset + DLB2_PCI_ACS_CTRL;\n+\t\tif (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)\n+\t\t\tacs_ctrl = 0;\n+\n+\t\tacs_mask = DLB2_PCI_ACS_SV | DLB2_PCI_ACS_RR;\n+\t\tacs_mask |= (DLB2_PCI_ACS_CR | DLB2_PCI_ACS_UF);\n+\t\tacs_ctrl |= (acs_cap & acs_mask);\n+\n+\t\tret = rte_pci_write_config(pdev, &acs_ctrl, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\toff = acs_cap_offset + DLB2_PCI_ACS_CTRL;\n+\t\tif (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)\n+\t\t\tacs_ctrl = 0;\n+\n+\t\tacs_mask = DLB2_PCI_ACS_RR | DLB2_PCI_ACS_CR;\n+\t\tacs_mask |= DLB2_PCI_ACS_EC;\n+\t\tacs_ctrl &= ~acs_mask;\n+\n+\t\toff = acs_cap_offset + DLB2_PCI_ACS_CTRL;\n+\t\tret = rte_pci_write_config(pdev, &acs_ctrl, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n+\t\t\t\t__func__, (int)off);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**********************************/\n+/****** Device configuration ******/\n+/**********************************/\n+\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb2/pf/dlb2_main.h\nnew file mode 100644\nindex 0000000..a914077\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/dlb2_main.h\n@@ -0,0 +1,107 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_MAIN_H\n+#define __DLB2_MAIN_H\n+\n+#include <rte_debug.h>\n+#include <rte_log.h>\n+#include <rte_spinlock.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#ifndef PAGE_SIZE\n+#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n+#endif\n+\n+#include \"base/dlb2_hw_types.h\"\n+#include \"../dlb2_user.h\"\n+\n+#define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5\n+\n+struct dlb2_dev;\n+\n+struct dlb2_port_memory {\n+\tstruct dlb2_list_head list;\n+\tvoid *cq_base;\n+\tbool valid;\n+};\n+\n+struct dlb2_dev {\n+\tstruct rte_pci_device *pdev;\n+\tstruct dlb2_hw hw;\n+\t/* struct list_head list; */\n+\tstruct device *dlb2_device;\n+\tstruct dlb2_port_memory ldb_port_pages[DLB2_MAX_NUM_LDB_PORTS];\n+\tstruct dlb2_port_memory dir_port_pages[DLB2_MAX_NUM_DIR_PORTS];\n+\t/* The enqueue_four function enqueues four HCWs (one cache-line worth)\n+\t * to the DLB2, using whichever mechanism is supported by the platform\n+\t * on which this driver is running.\n+\t */\n+\tvoid (*enqueue_four)(void *qe4, void *pp_addr);\n+\n+\tbool domain_reset_failed;\n+\t/* The resource mutex serializes access to driver data structures and\n+\t * hardware registers.\n+\t */\n+\trte_spinlock_t resource_mutex;\n+\trte_spinlock_t measurement_lock;\n+\tbool worker_launched;\n+\tu8 revision;\n+};\n+\n+struct dlb2_dev *dlb2_probe(struct rte_pci_device *pdev);\n+\n+/* The following functions were pf_ops in kernel driver implementation */\n+int dlb2_pf_reset(struct dlb2_dev *dlb2_dev);\n+int dlb2_pf_create_sched_domain(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_create_sched_domain_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp);\n+int dlb2_pf_create_ldb_queue(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_create_ldb_queue_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp);\n+int dlb2_pf_create_dir_queue(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_create_dir_queue_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp);\n+int dlb2_pf_create_ldb_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_create_ldb_port_args *args,\n+\t\t\t    uintptr_t cq_dma_base,\n+\t\t\t    struct dlb2_cmd_response *resp);\n+int dlb2_pf_create_dir_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_create_dir_port_args *args,\n+\t\t\t    uintptr_t cq_dma_base,\n+\t\t\t    struct dlb2_cmd_response *resp);\n+int dlb2_pf_start_domain(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_start_domain_args *args,\n+\t\t\t struct dlb2_cmd_response *resp);\n+int dlb2_pf_enable_ldb_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_enable_ldb_port_args *args,\n+\t\t\t    struct dlb2_cmd_response *resp);\n+int dlb2_pf_disable_ldb_port(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_disable_ldb_port_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp);\n+int dlb2_pf_enable_dir_port(struct dlb2_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb2_enable_dir_port_args *args,\n+\t\t\t    struct dlb2_cmd_response *resp);\n+int dlb2_pf_disable_dir_port(struct dlb2_hw *hw,\n+\t\t\t     u32 domain_id,\n+\t\t\t     struct dlb2_disable_dir_port_args *args,\n+\t\t\t     struct dlb2_cmd_response *resp);\n+int dlb2_pf_reset_domain(struct dlb2_hw *hw, u32 domain_id);\n+int dlb2_pf_ldb_port_owned_by_domain(struct dlb2_hw *hw,\n+\t\t\t\t     u32 domain_id,\n+\t\t\t\t     u32 port_id);\n+int dlb2_pf_dir_port_owned_by_domain(struct dlb2_hw *hw,\n+\t\t\t\t     u32 domain_id,\n+\t\t\t\t     u32 port_id);\n+\n+#endif /* __DLB2_MAIN_H */\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nnew file mode 100644\nindex 0000000..8c5ec20\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -0,0 +1,251 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <sys/mman.h>\n+#include <sys/fcntl.h>\n+#include <sys/time.h>\n+#include <errno.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+#include <rte_debug.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_devargs.h>\n+#include <rte_mbuf.h>\n+#include <rte_ring.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+#include <rte_malloc.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+#include <rte_eventdev_pmd_pci.h>\n+#include <rte_memory.h>\n+#include <rte_string_fns.h>\n+\n+#include \"../dlb2_priv.h\"\n+#include \"../dlb2_iface.h\"\n+#include \"../dlb2_inline_fns.h\"\n+#include \"dlb2_main.h\"\n+#include \"base/dlb2_hw_types.h\"\n+#include \"base/dlb2_osdep.h\"\n+#include \"base/dlb2_resource.h\"\n+\n+extern struct dlb2_dev *dlb2_probe(struct rte_pci_device *pdev);\n+\n+#if !defined RTE_ARCH_X86_64\n+#error \"This implementation only supports RTE_ARCH_X86_64 architecture.\"\n+#endif\n+\n+static const char *event_dlb2_pf_name = RTE_STR(EVDEV_DLB2_NAME_PMD);\n+\n+static void\n+dlb2_pf_low_level_io_init(void)\n+{\n+\tint i;\n+\t/* Addresses will be initialized at port create */\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++) {\n+\t\t/* First directed ports */\n+\t\tdlb2_port[i][DLB2_DIR_PORT].pp_addr = NULL;\n+\t\tdlb2_port[i][DLB2_DIR_PORT].cq_base = NULL;\n+\t\tdlb2_port[i][DLB2_DIR_PORT].mmaped = true;\n+\n+\t\t/* Now load balanced ports */\n+\t\tdlb2_port[i][DLB2_LDB_PORT].pp_addr = NULL;\n+\t\tdlb2_port[i][DLB2_LDB_PORT].cq_base = NULL;\n+\t\tdlb2_port[i][DLB2_LDB_PORT].mmaped = true;\n+\t}\n+}\n+\n+static int\n+dlb2_pf_open(struct dlb2_hw_dev *handle, const char *name)\n+{\n+\tRTE_SET_USED(handle);\n+\tRTE_SET_USED(name);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_pf_get_device_version(struct dlb2_hw_dev *handle,\n+\t\t\t   uint8_t *revision)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\t*revision = dlb2_dev->revision;\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_pf_hardware_init(struct dlb2_hw_dev *handle)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\tdlb2_hw_enable_sparse_ldb_cq_mode(&dlb2_dev->hw);\n+\tdlb2_hw_enable_sparse_dir_cq_mode(&dlb2_dev->hw);\n+}\n+\n+static int\n+dlb2_pf_get_num_resources(struct dlb2_hw_dev *handle,\n+\t\t\t  struct dlb2_get_num_resources_args *rsrcs)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\treturn dlb2_hw_get_num_resources(&dlb2_dev->hw, rsrcs, false, 0);\n+}\n+\n+static int\n+dlb2_pf_get_cq_poll_mode(struct dlb2_hw_dev *handle,\n+\t\t\t enum dlb2_cq_poll_modes *mode)\n+{\n+\tRTE_SET_USED(handle);\n+\n+\t*mode = DLB2_CQ_POLL_MODE_SPARSE;\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_pf_iface_fn_ptrs_init(void)\n+{\n+\n+\tdlb2_iface_low_level_io_init = dlb2_pf_low_level_io_init;\n+\tdlb2_iface_open = dlb2_pf_open;\n+\tdlb2_iface_get_device_version = dlb2_pf_get_device_version;\n+\tdlb2_iface_hardware_init = dlb2_pf_hardware_init;\n+\tdlb2_iface_get_num_resources = dlb2_pf_get_num_resources;\n+\tdlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;\n+}\n+\n+/* PCI DEV HOOKS */\n+static int\n+dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n+{\n+\tint ret = 0;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct dlb2_devargs dlb2_args = {\n+\t\t.socket_id = rte_socket_id(),\n+\t\t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n+\t\t.num_dir_credits_override = -1,\n+\t\t.qid_depth_thresholds = { {0} },\n+\t\t.cos_id = DLB2_COS_DEFAULT\n+\t};\n+\tstruct dlb2_eventdev *dlb2;\n+\n+\tDLB2_LOG_DBG(\"Enter with dev_id=%d socket_id=%d\",\n+\t\t     eventdev->data->dev_id, eventdev->data->socket_id);\n+\n+\tdlb2_pf_iface_fn_ptrs_init();\n+\n+\tpci_dev = RTE_DEV_TO_PCI(eventdev->dev);\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tdlb2 = dlb2_pmd_priv(eventdev); /* rte_zmalloc_socket mem */\n+\n+\t\t/* Probe the DLB2 PF layer */\n+\t\tdlb2->qm_instance.pf_dev = dlb2_probe(pci_dev);\n+\n+\t\tif (dlb2->qm_instance.pf_dev == NULL) {\n+\t\t\tDLB2_LOG_ERR(\"DLB2 PF Probe failed with error %d\\n\",\n+\t\t\t\t     rte_errno);\n+\t\t\tret = -rte_errno;\n+\t\t\tgoto dlb2_probe_failed;\n+\t\t}\n+\n+\t\t/* Were we invoked with runtime parameters? */\n+\t\tif (pci_dev->device.devargs) {\n+\t\t\tret = dlb2_parse_params(pci_dev->device.devargs->args,\n+\t\t\t\t\t\tpci_dev->device.devargs->name,\n+\t\t\t\t\t\t&dlb2_args);\n+\t\t\tif (ret) {\n+\t\t\t\tDLB2_LOG_ERR(\"PFPMD failed to parse args ret=%d, errno=%d\\n\",\n+\t\t\t\t\t     ret, rte_errno);\n+\t\t\t\tgoto dlb2_probe_failed;\n+\t\t\t}\n+\t\t}\n+\n+\t\tret = dlb2_primary_eventdev_probe(eventdev,\n+\t\t\t\t\t\t  event_dlb2_pf_name,\n+\t\t\t\t\t\t  &dlb2_args);\n+\t} else {\n+\t\tret = dlb2_secondary_eventdev_probe(eventdev,\n+\t\t\t\t\t\t    event_dlb2_pf_name);\n+\t}\n+\tif (ret)\n+\t\tgoto dlb2_probe_failed;\n+\n+\tDLB2_LOG_INFO(\"DLB2 PF Probe success\\n\");\n+\n+\treturn 0;\n+\n+dlb2_probe_failed:\n+\n+\tDLB2_LOG_INFO(\"DLB2 PF Probe failed, ret=%d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+#define EVENTDEV_INTEL_VENDOR_ID 0x8086\n+\n+static const struct rte_pci_id pci_id_dlb2_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(EVENTDEV_INTEL_VENDOR_ID,\n+\t\t\t       PCI_DEVICE_ID_INTEL_DLB2_PF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static int\n+event_dlb2_pci_probe(struct rte_pci_driver *pci_drv,\n+\t\t     struct rte_pci_device *pci_dev)\n+{\n+\tint ret;\n+\n+\tret = rte_event_pmd_pci_probe_named(pci_drv, pci_dev,\n+\t\t\t\t\t     sizeof(struct dlb2_eventdev),\n+\t\t\t\t\t     dlb2_eventdev_pci_init,\n+\t\t\t\t\t     event_dlb2_pf_name);\n+\tif (ret) {\n+\t\tDLB2_LOG_INFO(\"rte_event_pmd_pci_probe_named() failed, \"\n+\t\t\t\t\"ret=%d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+event_dlb2_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tint ret;\n+\n+\tret = rte_event_pmd_pci_remove(pci_dev, NULL);\n+\n+\tif (ret) {\n+\t\tDLB2_LOG_INFO(\"rte_event_pmd_pci_remove() failed, \"\n+\t\t\t\t\"ret=%d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+\n+}\n+\n+static struct rte_pci_driver pci_eventdev_dlb2_pmd = {\n+\t.id_table = pci_id_dlb2_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = event_dlb2_pci_probe,\n+\t.remove = event_dlb2_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(event_dlb2_pf, pci_eventdev_dlb2_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(event_dlb2_pf, pci_id_dlb2_map);\n",
    "prefixes": [
        "06/22"
    ]
}