Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/77513/?format=api
{ "id": 77513, "url": "http://patches.dpdk.org/api/patches/77513/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-9-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599855987-25976-9-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599855987-25976-9-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-09-11T20:26:13", "name": "[08/22] event/dlb2: add infos get and configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9c82b3b28e7eb69909ac798aaef1e35af740aa5a", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-9-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 12164, "url": "http://patches.dpdk.org/api/series/12164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12164", "date": "2020-09-11T20:26:05", "name": "Add DLB2 PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/12164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77513/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/77513/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9C719A04C1;\n\tFri, 11 Sep 2020 22:31:17 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E15A1C1E1;\n\tFri, 11 Sep 2020 22:30:27 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id 5769B1C192\n for <dev@dpdk.org>; Fri, 11 Sep 2020 22:29:59 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 13:29:58 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga005.jf.intel.com with ESMTP; 11 Sep 2020 13:29:57 -0700" ], "IronPort-SDR": [ "\n zjZuk3W9Lg2mARUGVaWt1zP7ZzqaiSXqYvDp9UFGoceKJzMk389ognclgAkPMG71RdB9LrhjV9\n T7r+4BWiSfJw==", "\n yL0ClUXuQyOa9gTLOZisPEHwCsKXjWrJ+GJr1a5JSPTjaJVS9aGfmVTVpJIsCnmpfh+chbTeJM\n v7sjbA0jlqdg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9741\"; a=\"156244351\"", "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"156244351\"", "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"481453539\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com", "Date": "Fri, 11 Sep 2020 15:26:13 -0500", "Message-Id": "<1599855987-25976-9-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH 08/22] event/dlb2: add infos get and configure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for configuring the DLB hardware.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 334 +++\n drivers/event/dlb2/dlb2_iface.c | 7 +-\n drivers/event/dlb2/dlb2_iface.h | 5 +\n drivers/event/dlb2/pf/base/dlb2_resource.c | 3234 ++++++++++++++++++++++++++++\n drivers/event/dlb2/pf/dlb2_main.c | 14 +\n drivers/event/dlb2/pf/dlb2_pf.c | 44 +\n 6 files changed, 3637 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 0d6fea4..58e953b 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -92,6 +92,28 @@ dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,\n \treturn 0;\n }\n \n+static void\n+dlb2_free_qe_mem(struct dlb2_port *qm_port)\n+{\n+\tif (qm_port == NULL)\n+\t\treturn;\n+\n+\tif (qm_port->qe4) {\n+\t\trte_free(qm_port->qe4);\n+\t\tqm_port->qe4 = NULL;\n+\t}\n+\n+\tif (qm_port->int_arm_qe) {\n+\t\trte_free(qm_port->int_arm_qe);\n+\t\tqm_port->int_arm_qe = NULL;\n+\t}\n+\n+\tif (qm_port->consume_qe) {\n+\t\trte_free(qm_port->consume_qe);\n+\t\tqm_port->consume_qe = NULL;\n+\t}\n+}\n+\n /* override defaults with value(s) provided on command line */\n static void\n dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,\n@@ -366,10 +388,322 @@ set_qid_depth_thresh(const char *key __rte_unused,\n }\n \n static void\n+dlb2_eventdev_info_get(struct rte_eventdev *dev,\n+\t\t struct rte_event_dev_info *dev_info)\n+{\n+\tstruct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);\n+\tint ret;\n+\n+\tret = dlb2_hw_query_resources(dlb2);\n+\tif (ret) {\n+\t\tconst struct rte_eventdev_data *data = dev->data;\n+\n+\t\tDLB2_LOG_ERR(\"get resources err=%d, devid=%d\\n\",\n+\t\t\t ret, data->dev_id);\n+\t\t/* fn is void, so fall through and return values set up in\n+\t\t * probe\n+\t\t */\n+\t}\n+\n+\t/* Add num resources currently owned by this domain.\n+\t * These would become available if the scheduling domain were reset due\n+\t * to the application recalling eventdev_configure to *reconfigure* the\n+\t * domain.\n+\t */\n+\tevdev_dlb2_default_info.max_event_ports += dlb2->num_ldb_ports;\n+\tevdev_dlb2_default_info.max_event_queues += dlb2->num_ldb_queues;\n+\tevdev_dlb2_default_info.max_num_events += dlb2->max_ldb_credits;\n+\n+\tevdev_dlb2_default_info.max_event_queues =\n+\t\tRTE_MIN(evdev_dlb2_default_info.max_event_queues,\n+\t\t\tRTE_EVENT_MAX_QUEUES_PER_DEV);\n+\n+\tevdev_dlb2_default_info.max_num_events =\n+\t\tRTE_MIN(evdev_dlb2_default_info.max_num_events,\n+\t\t\tdlb2->max_num_events_override);\n+\n+\t*dev_info = evdev_dlb2_default_info;\n+}\n+\n+static int\n+dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n+\t\t\t const struct dlb2_hw_rsrcs *resources_asked)\n+{\n+\tint ret = 0;\n+\tstruct dlb2_create_sched_domain_args *config_params;\n+\n+\tif (resources_asked == NULL) {\n+\t\tDLB2_LOG_ERR(\"dlb2: dlb2_create NULL parameter\\n\");\n+\t\tret = EINVAL;\n+\t\tgoto error_exit;\n+\t}\n+\n+\t/* Map generic qm resources to dlb2 resources */\n+\tconfig_params = &handle->cfg.resources;\n+\n+\t/* DIR ports and queues */\n+\n+\tconfig_params->num_dir_ports =\n+\t\tresources_asked->num_dir_ports;\n+\n+\tconfig_params->num_dir_credits =\n+\t\tresources_asked->num_dir_credits;\n+\n+\t/* LDB queues */\n+\n+\tconfig_params->num_ldb_queues =\n+\t\tresources_asked->num_ldb_queues;\n+\n+\t/* LDB ports */\n+\n+\tconfig_params->cos_strict = 0; /* Best effort */\n+\tconfig_params->num_cos_ldb_ports[0] = 0;\n+\tconfig_params->num_cos_ldb_ports[1] = 0;\n+\tconfig_params->num_cos_ldb_ports[2] = 0;\n+\tconfig_params->num_cos_ldb_ports[3] = 0;\n+\n+\tswitch (handle->cos_id) {\n+\tcase DLB2_COS_0:\n+\t\tconfig_params->num_ldb_ports = 0; /* no don't care ports */\n+\t\tconfig_params->num_cos_ldb_ports[0] =\n+\t\t\tresources_asked->num_ldb_ports;\n+\t\tbreak;\n+\tcase DLB2_COS_1:\n+\t\tconfig_params->num_ldb_ports = 0; /* no don't care ports */\n+\t\tconfig_params->num_cos_ldb_ports[1] =\n+\t\t\tresources_asked->num_ldb_ports;\n+\t\tbreak;\n+\tcase DLB2_COS_2:\n+\t\tconfig_params->num_ldb_ports = 0; /* no don't care ports */\n+\t\tconfig_params->num_cos_ldb_ports[2] =\n+\t\t\tresources_asked->num_ldb_ports;\n+\t\tbreak;\n+\tcase DLB2_COS_3:\n+\t\tconfig_params->num_ldb_ports = 0; /* no don't care ports */\n+\t\tconfig_params->num_cos_ldb_ports[3] =\n+\t\t\tresources_asked->num_ldb_ports;\n+\t\tbreak;\n+\tcase DLB2_COS_DEFAULT:\n+\t\t/* all ldb ports are don't care ports from a cos perspective */\n+\t\tconfig_params->num_ldb_ports =\n+\t\t\tresources_asked->num_ldb_ports;\n+\t\tbreak;\n+\t}\n+\n+\tconfig_params->num_ldb_credits =\n+\t\tresources_asked->num_ldb_credits;\n+\n+\tconfig_params->num_atomic_inflights =\n+\t\tDLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE *\n+\t\tconfig_params->num_ldb_queues;\n+\n+\tconfig_params->num_hist_list_entries = resources_asked->num_ldb_ports *\n+\t\tDLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\n+\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\\n\",\n+\t\t config_params->num_ldb_queues,\n+\t\t resources_asked->num_ldb_ports,\n+\t\t config_params->num_dir_ports,\n+\t\t config_params->num_atomic_inflights,\n+\t\t config_params->num_hist_list_entries,\n+\t\t config_params->num_ldb_credits,\n+\t\t config_params->num_dir_credits);\n+\n+\t/* Configure the QM */\n+\n+\tret = dlb2_iface_sched_domain_create(handle, config_params);\n+\tif (ret < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2: domain create failed, device_id = %d, (driver ret = %d, extra status: %s)\\n\",\n+\t\t\t handle->device_id,\n+\t\t\t ret,\n+\t\t\t dlb2_error_strings\n+\t\t\t\t[config_params->response.status]);\n+\n+\t\tgoto error_exit;\n+\t}\n+\n+\thandle->domain_id = config_params->response.id;\n+\thandle->domain_id_valid = 1;\n+\thandle->cfg.configured = true;\n+\n+error_exit:\n+\n+\treturn ret;\n+}\n+\n+static void\n+dlb2_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig)\n+{\n+\tstruct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);\n+\tenum dlb2_configuration_state config_state;\n+\tint i, j;\n+\n+\tdlb2_iface_domain_reset(dlb2);\n+\n+\t/* Free all dynamically allocated port memory */\n+\tfor (i = 0; i < dlb2->num_ports; i++)\n+\t\tdlb2_free_qe_mem(&dlb2->ev_ports[i].qm_port);\n+\n+\t/* If reconfiguring, mark the device's queues and ports as \"previously\n+\t * configured.\" If the user doesn't reconfigure them, the PMD will\n+\t * reapply their previous configuration when the device is started.\n+\t */\n+\tconfig_state = (reconfig) ? DLB2_PREV_CONFIGURED :\n+\t\tDLB2_NOT_CONFIGURED;\n+\n+\tfor (i = 0; i < dlb2->num_ports; i++) {\n+\t\tdlb2->ev_ports[i].qm_port.config_state = config_state;\n+\t\t/* Reset setup_done so ports can be reconfigured */\n+\t\tdlb2->ev_ports[i].setup_done = false;\n+\t\tfor (j = 0; j < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; j++)\n+\t\t\tdlb2->ev_ports[i].link[j].mapped = false;\n+\t}\n+\n+\tfor (i = 0; i < dlb2->num_queues; i++)\n+\t\tdlb2->ev_queues[i].qm_queue.config_state = config_state;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES; i++)\n+\t\tdlb2->ev_queues[i].setup_done = false;\n+\n+\tdlb2->num_ports = 0;\n+\tdlb2->num_ldb_ports = 0;\n+\tdlb2->num_dir_ports = 0;\n+\tdlb2->num_queues = 0;\n+\tdlb2->num_ldb_queues = 0;\n+\tdlb2->num_dir_queues = 0;\n+\tdlb2->configured = false;\n+}\n+\n+/* Note: 1 QM instance per QM device, QM instance/device == event device */\n+static int\n+dlb2_eventdev_configure(const struct rte_eventdev *dev)\n+{\n+\tstruct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);\n+\tstruct dlb2_hw_dev *handle = &dlb2->qm_instance;\n+\tstruct dlb2_hw_rsrcs *rsrcs = &handle->info.hw_rsrc_max;\n+\tconst struct rte_eventdev_data *data = dev->data;\n+\tconst struct rte_event_dev_config *config = &data->dev_conf;\n+\tint ret;\n+\n+\t/* If this eventdev is already configured, we must release the current\n+\t * scheduling domain before attempting to configure a new one.\n+\t */\n+\tif (dlb2->configured) {\n+\t\tdlb2_hw_reset_sched_domain(dev, true);\n+\n+\t\tret = dlb2_hw_query_resources(dlb2);\n+\t\tif (ret) {\n+\t\t\tDLB2_LOG_ERR(\"get resources err=%d, devid=%d\\n\",\n+\t\t\t\t ret, data->dev_id);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tif (config->nb_event_queues > rsrcs->num_queues) {\n+\t\tDLB2_LOG_ERR(\"nb_event_queues parameter (%d) exceeds the QM device's capabilities (%d).\\n\",\n+\t\t\t config->nb_event_queues,\n+\t\t\t rsrcs->num_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (config->nb_event_ports > (rsrcs->num_ldb_ports\n+\t\t\t+ rsrcs->num_dir_ports)) {\n+\t\tDLB2_LOG_ERR(\"nb_event_ports parameter (%d) exceeds the QM device's capabilities (%d).\\n\",\n+\t\t\t config->nb_event_ports,\n+\t\t\t (rsrcs->num_ldb_ports + rsrcs->num_dir_ports));\n+\t\treturn -EINVAL;\n+\t}\n+\tif (config->nb_events_limit > rsrcs->nb_events_limit) {\n+\t\tDLB2_LOG_ERR(\"nb_events_limit parameter (%d) exceeds the QM device's capabilities (%d).\\n\",\n+\t\t\t config->nb_events_limit,\n+\t\t\t rsrcs->nb_events_limit);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (config->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) {\n+\t\tdlb2->global_dequeue_wait = false;\n+\t} else {\n+\t\tuint32_t timeout32;\n+\n+\t\tdlb2->global_dequeue_wait = true;\n+\n+\t\t/* Craziness here is due to size mismatch in eventdev lib.\n+\t\t * TODO: Submit patch so dequeue API and config use same bit\n+\t\t * width timeout value and same units or time, instead of one\n+\t\t * being 32b ns and the other being 64b ticks.\n+\t\t */\n+\n+\t\ttimeout32 = config->dequeue_timeout_ns;\n+\n+\t\tdlb2->global_dequeue_wait_ticks =\n+\t\t\ttimeout32 * (rte_get_timer_hz() / 1E9);\n+\t}\n+\n+\t/* Does this platform support umonitor/umwait? */\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_UMWAIT)) {\n+\t\tif (RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 0 &&\n+\t\t RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 1) {\n+\t\t\tDLB2_LOG_ERR(\"invalid value (%d) for RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE, must be 0 or 1.\\n\",\n+\t\t\t\t RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tdlb2->umwait_allowed = true;\n+\t}\n+\n+\t/* FIXME: DLB should revert to load-balanced ports if dir are not\n+\t * available\n+\t */\n+\n+\trsrcs->num_dir_ports = config->nb_single_link_event_port_queues;\n+\trsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;\n+\t/* 1 dir queue per dir port */\n+\trsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;\n+\n+\t/* Scale down nb_events_limit by 4 for directed credits, since there\n+\t * are 4x as many load-balanced credits.\n+\t */\n+\trsrcs->num_ldb_credits = 0;\n+\trsrcs->num_dir_credits = 0;\n+\n+\tif (rsrcs->num_ldb_queues)\n+\t\trsrcs->num_ldb_credits = config->nb_events_limit;\n+\tif (rsrcs->num_dir_ports)\n+\t\trsrcs->num_dir_credits = config->nb_events_limit / 4;\n+\tif (dlb2->num_dir_credits_override != -1)\n+\t\trsrcs->num_dir_credits = dlb2->num_dir_credits_override;\n+\n+\tif (dlb2_hw_create_sched_domain(handle, rsrcs) < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2_hw_create_sched_domain failed\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdlb2->new_event_limit = config->nb_events_limit;\n+\t__atomic_store_n(&dlb2->inflights, 0, __ATOMIC_SEQ_CST);\n+\n+\n+\t/* Save number of ports/queues for this event dev */\n+\tdlb2->num_ports = config->nb_event_ports;\n+\tdlb2->num_queues = config->nb_event_queues;\n+\tdlb2->num_dir_ports = rsrcs->num_dir_ports;\n+\tdlb2->num_ldb_ports = dlb2->num_ports - dlb2->num_dir_ports;\n+\tdlb2->num_ldb_queues = dlb2->num_queues - dlb2->num_dir_ports;\n+\tdlb2->num_dir_queues = dlb2->num_dir_ports;\n+\tdlb2->ldb_credit_pool = rsrcs->num_ldb_credits;\n+\tdlb2->max_ldb_credits = rsrcs->num_ldb_credits;\n+\tdlb2->dir_credit_pool = rsrcs->num_dir_credits;\n+\tdlb2->max_dir_credits = rsrcs->num_dir_credits;\n+\n+\tdlb2->configured = true;\n+\n+\treturn 0;\n+}\n+\n+static void\n dlb2_entry_points_init(struct rte_eventdev *dev)\n {\n \t/* Expose PMD's eventdev interface */\n \tstatic struct rte_eventdev_ops dlb2_eventdev_entry_ops = {\n+\t\t.dev_infos_get = dlb2_eventdev_info_get,\n+\t\t.dev_configure = dlb2_eventdev_configure,\n \t\t.dump = dlb2_eventdev_dump,\n \t\t.xstats_get = dlb2_eventdev_xstats_get,\n \t\t.xstats_get_names = dlb2_eventdev_xstats_get_names,\ndiff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c\nindex fefdf78..5c11736 100644\n--- a/drivers/event/dlb2/dlb2_iface.c\n+++ b/drivers/event/dlb2/dlb2_iface.c\n@@ -39,4 +39,9 @@ int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,\n \t\t\t\t enum dlb2_cq_poll_modes *mode);\n \n int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,\n-\t\t\t\t struct dlb2_get_num_resources_args *rsrcs);\n+\t\t\t\tstruct dlb2_get_num_resources_args *rsrcs);\n+\n+int (*dlb2_iface_sched_domain_create)(struct dlb2_hw_dev *handle,\n+\t\t\t\tstruct dlb2_create_sched_domain_args *args);\n+\n+void (*dlb2_iface_domain_reset)(struct dlb2_eventdev *dlb2);\ndiff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h\nindex 4fb416e..576c1c3 100644\n--- a/drivers/event/dlb2/dlb2_iface.h\n+++ b/drivers/event/dlb2/dlb2_iface.h\n@@ -26,4 +26,9 @@ extern int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,\n extern int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,\n \t\t\t\tstruct dlb2_get_num_resources_args *rsrcs);\n \n+extern int (*dlb2_iface_sched_domain_create)(struct dlb2_hw_dev *handle,\n+\t\t\t\t struct dlb2_create_sched_domain_args *args);\n+\n+extern void (*dlb2_iface_domain_reset)(struct dlb2_eventdev *dlb2);\n+\n #endif /* _DLB2_IFACE_H_ */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 6de8b95..f83f8a1 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -12,6 +12,24 @@\n #include \"dlb2_regs.h\"\n #include \"dlb2_resource.h\"\n \n+#define DLB2_DOM_LIST_HEAD(head, type) \\\n+\tDLB2_LIST_HEAD((head), type, domain_list)\n+\n+#define DLB2_FUNC_LIST_HEAD(head, type) \\\n+\tDLB2_LIST_HEAD((head), type, func_list)\n+\n+#define DLB2_DOM_LIST_FOR(head, ptr, iter) \\\n+\tDLB2_LIST_FOR_EACH(head, ptr, domain_list, iter)\n+\n+#define DLB2_FUNC_LIST_FOR(head, ptr, iter) \\\n+\tDLB2_LIST_FOR_EACH(head, ptr, func_list, iter)\n+\n+#define DLB2_DOM_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n+\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, domain_list, it, it_tmp)\n+\n+#define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n+\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n+\n static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)\n {\n \tint i;\n@@ -272,3 +290,3219 @@ void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw)\n \n \tDLB2_CSR_WR(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE, r0.val);\n }\n+\n+static void dlb2_configure_domain_credits(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tunion dlb2_chp_cfg_ldb_vas_crd r0 = { {0} };\n+\tunion dlb2_chp_cfg_dir_vas_crd r1 = { {0} };\n+\n+\tr0.field.count = domain->num_ldb_credits;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id), r0.val);\n+\n+\tr1.field.count = domain->num_dir_credits;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id), r1.val);\n+}\n+\n+static struct dlb2_ldb_port *\n+dlb2_get_next_ldb_port(struct dlb2_hw *hw,\n+\t\t struct dlb2_function_resources *rsrcs,\n+\t\t u32 domain_id,\n+\t\t u32 cos_id)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tRTE_SET_USED(iter);\n+\t/*\n+\t * To reduce the odds of consecutive load-balanced ports mapping to the\n+\t * same queue(s), the driver attempts to allocate ports whose neighbors\n+\t * are owned by a different domain.\n+\t */\n+\tDLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {\n+\t\tu32 next, prev;\n+\t\tu32 phys_id;\n+\n+\t\tphys_id = port->id.phys_id;\n+\t\tnext = phys_id + 1;\n+\t\tprev = phys_id - 1;\n+\n+\t\tif (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)\n+\t\t\tnext = 0;\n+\t\tif (phys_id == 0)\n+\t\t\tprev = DLB2_MAX_NUM_LDB_PORTS - 1;\n+\n+\t\tif (!hw->rsrcs.ldb_ports[next].owned ||\n+\t\t hw->rsrcs.ldb_ports[next].domain_id.phys_id == domain_id)\n+\t\t\tcontinue;\n+\n+\t\tif (!hw->rsrcs.ldb_ports[prev].owned ||\n+\t\t hw->rsrcs.ldb_ports[prev].domain_id.phys_id == domain_id)\n+\t\t\tcontinue;\n+\n+\t\treturn port;\n+\t}\n+\n+\t/*\n+\t * Failing that, the driver looks for a port with one neighbor owned by\n+\t * a different domain and the other unallocated.\n+\t */\n+\tDLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {\n+\t\tu32 next, prev;\n+\t\tu32 phys_id;\n+\n+\t\tphys_id = port->id.phys_id;\n+\t\tnext = phys_id + 1;\n+\t\tprev = phys_id - 1;\n+\n+\t\tif (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)\n+\t\t\tnext = 0;\n+\t\tif (phys_id == 0)\n+\t\t\tprev = DLB2_MAX_NUM_LDB_PORTS - 1;\n+\n+\t\tif (!hw->rsrcs.ldb_ports[prev].owned &&\n+\t\t hw->rsrcs.ldb_ports[next].owned &&\n+\t\t hw->rsrcs.ldb_ports[next].domain_id.phys_id != domain_id)\n+\t\t\treturn port;\n+\n+\t\tif (!hw->rsrcs.ldb_ports[next].owned &&\n+\t\t hw->rsrcs.ldb_ports[prev].owned &&\n+\t\t hw->rsrcs.ldb_ports[prev].domain_id.phys_id != domain_id)\n+\t\t\treturn port;\n+\t}\n+\n+\t/*\n+\t * Failing that, the driver looks for a port with both neighbors\n+\t * unallocated.\n+\t */\n+\tDLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {\n+\t\tu32 next, prev;\n+\t\tu32 phys_id;\n+\n+\t\tphys_id = port->id.phys_id;\n+\t\tnext = phys_id + 1;\n+\t\tprev = phys_id - 1;\n+\n+\t\tif (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)\n+\t\t\tnext = 0;\n+\t\tif (phys_id == 0)\n+\t\t\tprev = DLB2_MAX_NUM_LDB_PORTS - 1;\n+\n+\t\tif (!hw->rsrcs.ldb_ports[prev].owned &&\n+\t\t !hw->rsrcs.ldb_ports[next].owned)\n+\t\t\treturn port;\n+\t}\n+\n+\t/* If all else fails, the driver returns the next available port. */\n+\treturn DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_ports[cos_id],\n+\t\t\t\t typeof(*port));\n+}\n+\n+static int __dlb2_attach_ldb_ports(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_ports,\n+\t\t\t\t u32 cos_id,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tunsigned int i;\n+\n+\tif (rsrcs->num_avail_ldb_ports[cos_id] < num_ports) {\n+\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < num_ports; i++) {\n+\t\tstruct dlb2_ldb_port *port;\n+\n+\t\tport = dlb2_get_next_ldb_port(hw, rsrcs,\n+\t\t\t\t\t domain->id.phys_id, cos_id);\n+\t\tif (!port) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: domain validation failed\\n\",\n+\t\t\t\t __func__);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\tdlb2_list_del(&rsrcs->avail_ldb_ports[cos_id],\n+\t\t\t &port->func_list);\n+\n+\t\tport->domain_id = domain->id;\n+\t\tport->owned = true;\n+\n+\t\tdlb2_list_add(&domain->avail_ldb_ports[cos_id],\n+\t\t\t &port->domain_list);\n+\t}\n+\n+\trsrcs->num_avail_ldb_ports[cos_id] -= num_ports;\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_create_sched_domain_args *args,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tunsigned int i, j;\n+\tint ret;\n+\n+\tif (args->cos_strict) {\n+\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\t\tu32 num = args->num_cos_ldb_ports[i];\n+\n+\t\t\t/* Allocate ports from specific classes-of-service */\n+\t\t\tret = __dlb2_attach_ldb_ports(hw,\n+\t\t\t\t\t\t rsrcs,\n+\t\t\t\t\t\t domain,\n+\t\t\t\t\t\t num,\n+\t\t\t\t\t\t i,\n+\t\t\t\t\t\t resp);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t} else {\n+\t\tunsigned int k;\n+\t\tu32 cos_id;\n+\n+\t\t/*\n+\t\t * Attempt to allocate from specific class-of-service, but\n+\t\t * fallback to the other classes if that fails.\n+\t\t */\n+\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\t\tfor (j = 0; j < args->num_cos_ldb_ports[i]; j++) {\n+\t\t\t\tfor (k = 0; k < DLB2_NUM_COS_DOMAINS; k++) {\n+\t\t\t\t\tcos_id = (i + k) % DLB2_NUM_COS_DOMAINS;\n+\n+\t\t\t\t\tret = __dlb2_attach_ldb_ports(hw,\n+\t\t\t\t\t\t\t\t rsrcs,\n+\t\t\t\t\t\t\t\t domain,\n+\t\t\t\t\t\t\t\t 1,\n+\t\t\t\t\t\t\t\t cos_id,\n+\t\t\t\t\t\t\t\t resp);\n+\t\t\t\t\tif (ret == 0)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\n+\t\t\t\tif (ret < 0)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Allocate num_ldb_ports from any class-of-service */\n+\tfor (i = 0; i < args->num_ldb_ports; i++) {\n+\t\tfor (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {\n+\t\t\tret = __dlb2_attach_ldb_ports(hw,\n+\t\t\t\t\t\t rsrcs,\n+\t\t\t\t\t\t domain,\n+\t\t\t\t\t\t 1,\n+\t\t\t\t\t\t j,\n+\t\t\t\t\t\t resp);\n+\t\t\tif (ret == 0)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_attach_dir_ports(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_ports,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tunsigned int i;\n+\n+\tif (rsrcs->num_avail_dir_pq_pairs < num_ports) {\n+\t\tresp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < num_ports; i++) {\n+\t\tstruct dlb2_dir_pq_pair *port;\n+\n+\t\tport = DLB2_FUNC_LIST_HEAD(rsrcs->avail_dir_pq_pairs,\n+\t\t\t\t\t typeof(*port));\n+\t\tif (!port) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: domain validation failed\\n\",\n+\t\t\t\t __func__);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\tdlb2_list_del(&rsrcs->avail_dir_pq_pairs, &port->func_list);\n+\n+\t\tport->domain_id = domain->id;\n+\t\tport->owned = true;\n+\n+\t\tdlb2_list_add(&domain->avail_dir_pq_pairs, &port->domain_list);\n+\t}\n+\n+\trsrcs->num_avail_dir_pq_pairs -= num_ports;\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_attach_ldb_credits(struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_credits,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tif (rsrcs->num_avail_qed_entries < num_credits) {\n+\t\tresp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trsrcs->num_avail_qed_entries -= num_credits;\n+\tdomain->num_ldb_credits += num_credits;\n+\treturn 0;\n+}\n+\n+static int dlb2_attach_dir_credits(struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_credits,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tif (rsrcs->num_avail_dqed_entries < num_credits) {\n+\t\tresp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trsrcs->num_avail_dqed_entries -= num_credits;\n+\tdomain->num_dir_credits += num_credits;\n+\treturn 0;\n+}\n+\n+static int dlb2_attach_atomic_inflights(struct dlb2_function_resources *rsrcs,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain,\n+\t\t\t\t\tu32 num_atomic_inflights,\n+\t\t\t\t\tstruct dlb2_cmd_response *resp)\n+{\n+\tif (rsrcs->num_avail_aqed_entries < num_atomic_inflights) {\n+\t\tresp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trsrcs->num_avail_aqed_entries -= num_atomic_inflights;\n+\tdomain->num_avail_aqed_entries += num_atomic_inflights;\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_attach_domain_hist_list_entries(struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_hist_list_entries,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tstruct dlb2_bitmap *bitmap;\n+\tint base;\n+\n+\tif (num_hist_list_entries) {\n+\t\tbitmap = rsrcs->avail_hist_list_entries;\n+\n+\t\tbase = dlb2_bitmap_find_set_bit_range(bitmap,\n+\t\t\t\t\t\t num_hist_list_entries);\n+\t\tif (base < 0)\n+\t\t\tgoto error;\n+\n+\t\tdomain->total_hist_list_entries = num_hist_list_entries;\n+\t\tdomain->avail_hist_list_entries = num_hist_list_entries;\n+\t\tdomain->hist_list_entry_base = base;\n+\t\tdomain->hist_list_entry_offset = 0;\n+\n+\t\tdlb2_bitmap_clear_range(bitmap, base, num_hist_list_entries);\n+\t}\n+\treturn 0;\n+\n+error:\n+\tresp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;\n+\treturn -EINVAL;\n+}\n+\n+static int dlb2_attach_ldb_queues(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t u32 num_queues,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tunsigned int i;\n+\n+\tif (rsrcs->num_avail_ldb_queues < num_queues) {\n+\t\tresp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < num_queues; i++) {\n+\t\tstruct dlb2_ldb_queue *queue;\n+\n+\t\tqueue = DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_queues,\n+\t\t\t\t\t typeof(*queue));\n+\t\tif (!queue) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: domain validation failed\\n\",\n+\t\t\t\t __func__);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\tdlb2_list_del(&rsrcs->avail_ldb_queues, &queue->func_list);\n+\n+\t\tqueue->domain_id = domain->id;\n+\t\tqueue->owned = true;\n+\n+\t\tdlb2_list_add(&domain->avail_ldb_queues, &queue->domain_list);\n+\t}\n+\n+\trsrcs->num_avail_ldb_queues -= num_queues;\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_domain_attach_resources(struct dlb2_hw *hw,\n+\t\t\t struct dlb2_function_resources *rsrcs,\n+\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t struct dlb2_create_sched_domain_args *args,\n+\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tint ret;\n+\n+\tret = dlb2_attach_ldb_queues(hw,\n+\t\t\t\t rsrcs,\n+\t\t\t\t domain,\n+\t\t\t\t args->num_ldb_queues,\n+\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_ldb_ports(hw,\n+\t\t\t\t rsrcs,\n+\t\t\t\t domain,\n+\t\t\t\t args,\n+\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_dir_ports(hw,\n+\t\t\t\t rsrcs,\n+\t\t\t\t domain,\n+\t\t\t\t args->num_dir_ports,\n+\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_ldb_credits(rsrcs,\n+\t\t\t\t domain,\n+\t\t\t\t args->num_ldb_credits,\n+\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_dir_credits(rsrcs,\n+\t\t\t\t domain,\n+\t\t\t\t args->num_dir_credits,\n+\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_domain_hist_list_entries(rsrcs,\n+\t\t\t\t\t\t domain,\n+\t\t\t\t\t\t args->num_hist_list_entries,\n+\t\t\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_attach_atomic_inflights(rsrcs,\n+\t\t\t\t\t domain,\n+\t\t\t\t\t args->num_atomic_inflights,\n+\t\t\t\t\t resp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tdlb2_configure_domain_credits(hw, domain);\n+\n+\tdomain->configured = true;\n+\n+\tdomain->started = false;\n+\n+\trsrcs->num_avail_domains--;\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_verify_create_sched_dom_args(struct dlb2_function_resources *rsrcs,\n+\t\t\t\t struct dlb2_create_sched_domain_args *args,\n+\t\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\tu32 num_avail_ldb_ports, req_ldb_ports;\n+\tstruct dlb2_bitmap *avail_hl_entries;\n+\tunsigned int max_contig_hl_range;\n+\tint i;\n+\n+\tavail_hl_entries = rsrcs->avail_hist_list_entries;\n+\n+\tmax_contig_hl_range = dlb2_bitmap_longest_set_range(avail_hl_entries);\n+\n+\tnum_avail_ldb_ports = 0;\n+\treq_ldb_ports = 0;\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tnum_avail_ldb_ports += rsrcs->num_avail_ldb_ports[i];\n+\n+\t\treq_ldb_ports += args->num_cos_ldb_ports[i];\n+\t}\n+\n+\treq_ldb_ports += args->num_ldb_ports;\n+\n+\tif (rsrcs->num_avail_domains < 1) {\n+\t\tresp->status = DLB2_ST_DOMAIN_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsrcs->num_avail_ldb_queues < args->num_ldb_queues) {\n+\t\tresp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (req_ldb_ports > num_avail_ldb_ports) {\n+\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; args->cos_strict && i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tif (args->num_cos_ldb_ports[i] >\n+\t\t rsrcs->num_avail_ldb_ports[i]) {\n+\t\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (args->num_ldb_queues > 0 && req_ldb_ports == 0) {\n+\t\tresp->status = DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsrcs->num_avail_dir_pq_pairs < args->num_dir_ports) {\n+\t\tresp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsrcs->num_avail_qed_entries < args->num_ldb_credits) {\n+\t\tresp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsrcs->num_avail_dqed_entries < args->num_dir_credits) {\n+\t\tresp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsrcs->num_avail_aqed_entries < args->num_atomic_inflights) {\n+\t\tresp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (max_contig_hl_range < args->num_hist_list_entries) {\n+\t\tresp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_log_create_sched_domain_args(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_create_sched_domain_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 create sched domain arguments:\\n\");\n+\tif (vdev_req)\n+\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB queues: %d\\n\",\n+\t\t args->num_ldb_queues);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB ports (any CoS): %d\\n\",\n+\t\t args->num_ldb_ports);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB ports (CoS 0): %d\\n\",\n+\t\t args->num_cos_ldb_ports[0]);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB ports (CoS 1): %d\\n\",\n+\t\t args->num_cos_ldb_ports[1]);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB ports (CoS 2): %d\\n\",\n+\t\t args->num_cos_ldb_ports[1]);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB ports (CoS 3): %d\\n\",\n+\t\t args->num_cos_ldb_ports[1]);\n+\tDLB2_HW_DBG(hw, \"\\tStrict CoS allocation: %d\\n\",\n+\t\t args->cos_strict);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of DIR ports: %d\\n\",\n+\t\t args->num_dir_ports);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of ATM inflights: %d\\n\",\n+\t\t args->num_atomic_inflights);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of hist list entries: %d\\n\",\n+\t\t args->num_hist_list_entries);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of LDB credits: %d\\n\",\n+\t\t args->num_ldb_credits);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of DIR credits: %d\\n\",\n+\t\t args->num_dir_credits);\n+}\n+\n+/**\n+ * dlb2_hw_create_sched_domain() - Allocate and initialize a DLB scheduling\n+ *\tdomain and its resources.\n+ * @hw:\tContains the current state of the DLB2 hardware.\n+ * @args: User-provided arguments.\n+ * @resp: Response to user.\n+ * @vdev_req: Request came from a virtual device.\n+ * @vdev_id: If vdev_req is true, this contains the virtual device's ID.\n+ *\n+ * Return: returns < 0 on error, 0 otherwise. If the driver is unable to\n+ * satisfy a request, resp->status will be set accordingly.\n+ */\n+int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_create_sched_domain_args *args,\n+\t\t\t\tstruct dlb2_cmd_response *resp,\n+\t\t\t\tbool vdev_req,\n+\t\t\t\tunsigned int vdev_id)\n+{\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_hw_domain *domain;\n+\tint ret;\n+\n+\trsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;\n+\n+\tdlb2_log_create_sched_domain_args(hw, args, vdev_req, vdev_id);\n+\n+\t/*\n+\t * Verify that hardware resources are available before attempting to\n+\t * satisfy the request. This simplifies the error unwinding code.\n+\t */\n+\tret = dlb2_verify_create_sched_dom_args(rsrcs, args, resp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdomain = DLB2_FUNC_LIST_HEAD(rsrcs->avail_domains, typeof(*domain));\n+\tif (!domain) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: no available domains\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (domain->configured) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: avail_domains contains configured domains.\\n\",\n+\t\t\t __func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tdlb2_init_domain_rsrc_lists(domain);\n+\n+\tret = dlb2_domain_attach_resources(hw, rsrcs, domain, args, resp);\n+\tif (ret < 0) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: failed to verify args.\\n\",\n+\t\t\t __func__);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tdlb2_list_del(&rsrcs->avail_domains, &domain->func_list);\n+\n+\tdlb2_list_add(&rsrcs->used_domains, &domain->func_list);\n+\n+\tresp->id = (vdev_req) ? domain->id.virt_id : domain->id.phys_id;\n+\tresp->status = 0;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * The PF driver cannot assume that a register write will affect subsequent HCW\n+ * writes. To ensure a write completes, the driver must read back a CSR. This\n+ * function only need be called for configuration that can occur after the\n+ * domain has started; prior to starting, applications can't send HCWs.\n+ */\n+static inline void dlb2_flush_csr(struct dlb2_hw *hw)\n+{\n+\tDLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);\n+}\n+\n+static void dlb2_dir_port_cq_disable(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_dir_pq_pair *port)\n+{\n+\tunion dlb2_lsp_cq_dir_dsbl reg;\n+\n+\treg.field.disabled = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_DIR_DSBL(port->id.phys_id), reg.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static u32 dlb2_dir_cq_token_count(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_dir_pq_pair *port)\n+{\n+\tunion dlb2_lsp_cq_dir_tkn_cnt r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id));\n+\n+\t/*\n+\t * Account for the initial token count, which is used in order to\n+\t * provide a CQ with depth less than 8.\n+\t */\n+\n+\treturn r0.field.count - port->init_tkn_cnt;\n+}\n+\n+static int dlb2_drain_dir_cq(struct dlb2_hw *hw,\n+\t\t\t struct dlb2_dir_pq_pair *port)\n+{\n+\tunsigned int port_id = port->id.phys_id;\n+\tu32 cnt;\n+\n+\t/* Return any outstanding tokens */\n+\tcnt = dlb2_dir_cq_token_count(hw, port);\n+\n+\tif (cnt != 0) {\n+\t\tstruct dlb2_hcw hcw_mem[8], *hcw;\n+\t\tvoid *pp_addr;\n+\n+\t\tpp_addr = os_map_producer_port(hw, port_id, false);\n+\n+\t\t/* Point hcw to a 64B-aligned location */\n+\t\thcw = (struct dlb2_hcw *)((uintptr_t)&hcw_mem[4] & ~0x3F);\n+\n+\t\t/*\n+\t\t * Program the first HCW for a batch token return and\n+\t\t * the rest as NOOPS\n+\t\t */\n+\t\tmemset(hcw, 0, 4 * sizeof(*hcw));\n+\t\thcw->cq_token = 1;\n+\t\thcw->lock_id = cnt - 1;\n+\n+\t\tos_enqueue_four_hcws(hw, hcw, pp_addr);\n+\n+\t\tos_fence_hcw(hw, pp_addr);\n+\n+\t\tos_unmap_producer_port(hw, pp_addr);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_dir_port_cq_enable(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_dir_pq_pair *port)\n+{\n+\tunion dlb2_lsp_cq_dir_dsbl reg;\n+\n+\treg.field.disabled = 0;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_DIR_DSBL(port->id.phys_id), reg.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static int dlb2_domain_drain_dir_cqs(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t bool toggle_port)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tint ret;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter) {\n+\t\t/*\n+\t\t * Can't drain a port if it's not configured, and there's\n+\t\t * nothing to drain if its queue is unconfigured.\n+\t\t */\n+\t\tif (!port->port_configured || !port->queue_configured)\n+\t\t\tcontinue;\n+\n+\t\tif (toggle_port)\n+\t\t\tdlb2_dir_port_cq_disable(hw, port);\n+\n+\t\tret = dlb2_drain_dir_cq(hw, port);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (toggle_port)\n+\t\t\tdlb2_dir_port_cq_enable(hw, port);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static u32 dlb2_dir_queue_depth(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_dir_pq_pair *queue)\n+{\n+\tunion dlb2_lsp_qid_dir_enqueue_cnt r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_DIR_ENQUEUE_CNT(queue->id.phys_id));\n+\n+\treturn r0.field.count;\n+}\n+\n+static bool dlb2_dir_queue_is_empty(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_dir_pq_pair *queue)\n+{\n+\treturn dlb2_dir_queue_depth(hw, queue) == 0;\n+}\n+\n+static bool dlb2_domain_dir_queues_empty(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, queue, iter) {\n+\t\tif (!dlb2_dir_queue_is_empty(hw, queue))\n+\t\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+static int dlb2_domain_drain_dir_queues(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tint i, ret;\n+\n+\t/* If the domain hasn't been started, there's no traffic to drain */\n+\tif (!domain->started)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < DLB2_MAX_QID_EMPTY_CHECK_LOOPS; i++) {\n+\t\tret = dlb2_domain_drain_dir_cqs(hw, domain, true);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (dlb2_domain_dir_queues_empty(hw, domain))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == DLB2_MAX_QID_EMPTY_CHECK_LOOPS) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: failed to empty queues\\n\",\n+\t\t\t __func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/*\n+\t * Drain the CQs one more time. For the queues to go empty, they would\n+\t * have scheduled one or more QEs.\n+\t */\n+\tret = dlb2_domain_drain_dir_cqs(hw, domain, true);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_ldb_port_cq_enable(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tunion dlb2_lsp_cq_ldb_dsbl reg;\n+\n+\t/*\n+\t * Don't re-enable the port if a removal is pending. The caller should\n+\t * mark this port as enabled (if it isn't already), and when the\n+\t * removal completes the port will be enabled.\n+\t */\n+\tif (port->num_pending_removals)\n+\t\treturn;\n+\n+\treg.field.disabled = 0;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static void dlb2_ldb_port_cq_disable(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tunion dlb2_lsp_cq_ldb_dsbl reg;\n+\n+\treg.field.disabled = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static u32 dlb2_ldb_cq_inflight_count(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tunion dlb2_lsp_cq_ldb_infl_cnt r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_LDB_INFL_CNT(port->id.phys_id));\n+\n+\treturn r0.field.count;\n+}\n+\n+static u32 dlb2_ldb_cq_token_count(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tunion dlb2_lsp_cq_ldb_tkn_cnt r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id));\n+\n+\t/*\n+\t * Account for the initial token count, which is used in order to\n+\t * provide a CQ with depth less than 8.\n+\t */\n+\n+\treturn r0.field.token_count - port->init_tkn_cnt;\n+}\n+\n+static int dlb2_drain_ldb_cq(struct dlb2_hw *hw, struct dlb2_ldb_port *port)\n+{\n+\tu32 infl_cnt, tkn_cnt;\n+\tunsigned int i;\n+\n+\tinfl_cnt = dlb2_ldb_cq_inflight_count(hw, port);\n+\ttkn_cnt = dlb2_ldb_cq_token_count(hw, port);\n+\n+\tif (infl_cnt || tkn_cnt) {\n+\t\tstruct dlb2_hcw hcw_mem[8], *hcw;\n+\t\tvoid *pp_addr;\n+\n+\t\tpp_addr = os_map_producer_port(hw, port->id.phys_id, true);\n+\n+\t\t/* Point hcw to a 64B-aligned location */\n+\t\thcw = (struct dlb2_hcw *)((uintptr_t)&hcw_mem[4] & ~0x3F);\n+\n+\t\t/*\n+\t\t * Program the first HCW for a completion and token return and\n+\t\t * the other HCWs as NOOPS\n+\t\t */\n+\n+\t\tmemset(hcw, 0, 4 * sizeof(*hcw));\n+\t\thcw->qe_comp = (infl_cnt > 0);\n+\t\thcw->cq_token = (tkn_cnt > 0);\n+\t\thcw->lock_id = tkn_cnt - 1;\n+\n+\t\t/* Return tokens in the first HCW */\n+\t\tos_enqueue_four_hcws(hw, hcw, pp_addr);\n+\n+\t\thcw->cq_token = 0;\n+\n+\t\t/* Issue remaining completions (if any) */\n+\t\tfor (i = 1; i < infl_cnt; i++)\n+\t\t\tos_enqueue_four_hcws(hw, hcw, pp_addr);\n+\n+\t\tos_fence_hcw(hw, pp_addr);\n+\n+\t\tos_unmap_producer_port(hw, pp_addr);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_domain_drain_ldb_cqs(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t bool toggle_port)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint ret, i;\n+\tRTE_SET_USED(iter);\n+\n+\t/* If the domain hasn't been started, there's no traffic to drain */\n+\tif (!domain->started)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tif (toggle_port)\n+\t\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n+\n+\t\t\tret = dlb2_drain_ldb_cq(hw, port);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\n+\t\t\tif (toggle_port)\n+\t\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static u32 dlb2_ldb_queue_depth(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_ldb_queue *queue)\n+{\n+\tunion dlb2_lsp_qid_aqed_active_cnt r0;\n+\tunion dlb2_lsp_qid_atm_active r1;\n+\tunion dlb2_lsp_qid_ldb_enqueue_cnt r2;\n+\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_AQED_ACTIVE_CNT(queue->id.phys_id));\n+\tr1.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_ATM_ACTIVE(queue->id.phys_id));\n+\n+\tr2.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_LDB_ENQUEUE_CNT(queue->id.phys_id));\n+\n+\treturn r0.field.count + r1.field.count + r2.field.count;\n+}\n+\n+static bool dlb2_ldb_queue_is_empty(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\treturn dlb2_ldb_queue_depth(hw, queue) == 0;\n+}\n+\n+static bool dlb2_domain_mapped_queues_empty(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_queue *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter) {\n+\t\tif (queue->num_mappings == 0)\n+\t\t\tcontinue;\n+\n+\t\tif (!dlb2_ldb_queue_is_empty(hw, queue))\n+\t\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+static int dlb2_domain_drain_mapped_queues(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tint i, ret;\n+\n+\t/* If the domain hasn't been started, there's no traffic to drain */\n+\tif (!domain->started)\n+\t\treturn 0;\n+\n+\tif (domain->num_pending_removals > 0) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: failed to unmap domain queues\\n\",\n+\t\t\t __func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_QID_EMPTY_CHECK_LOOPS; i++) {\n+\t\tret = dlb2_domain_drain_ldb_cqs(hw, domain, true);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (dlb2_domain_mapped_queues_empty(hw, domain))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == DLB2_MAX_QID_EMPTY_CHECK_LOOPS) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: failed to empty queues\\n\",\n+\t\t\t __func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/*\n+\t * Drain the CQs one more time. For the queues to go empty, they would\n+\t * have scheduled one or more QEs.\n+\t */\n+\tret = dlb2_domain_drain_ldb_cqs(hw, domain, true);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_domain_enable_ldb_cqs(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tport->enabled = true;\n+\n+\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\t\t}\n+\t}\n+}\n+\n+static struct dlb2_ldb_queue *\n+dlb2_get_ldb_queue_from_id(struct dlb2_hw *hw,\n+\t\t\t u32 id,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_list_entry *iter1;\n+\tstruct dlb2_list_entry *iter2;\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_queue *queue;\n+\tRTE_SET_USED(iter1);\n+\tRTE_SET_USED(iter2);\n+\n+\tif (id >= DLB2_MAX_NUM_LDB_QUEUES)\n+\t\treturn NULL;\n+\n+\trsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;\n+\n+\tif (!vdev_req)\n+\t\treturn &hw->rsrcs.ldb_queues[id];\n+\n+\tDLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iter1) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter2)\n+\t\t\tif (queue->id.virt_id == id)\n+\t\t\t\treturn queue;\n+\t}\n+\n+\tDLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_queues, queue, iter1)\n+\t\tif (queue->id.virt_id == id)\n+\t\t\treturn queue;\n+\n+\treturn NULL;\n+}\n+\n+static struct dlb2_hw_domain *dlb2_get_domain_from_id(struct dlb2_hw *hw,\n+\t\t\t\t\t\t u32 id,\n+\t\t\t\t\t\t bool vdev_req,\n+\t\t\t\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_list_entry *iteration;\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_hw_domain *domain;\n+\tRTE_SET_USED(iteration);\n+\n+\tif (id >= DLB2_MAX_NUM_DOMAINS)\n+\t\treturn NULL;\n+\n+\tif (!vdev_req)\n+\t\treturn &hw->domains[id];\n+\n+\trsrcs = &hw->vdev[vdev_id];\n+\n+\tDLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iteration)\n+\t\tif (domain->id.virt_id == id)\n+\t\t\treturn domain;\n+\n+\treturn NULL;\n+}\n+\n+static int dlb2_port_slot_state_transition(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t\t int slot,\n+\t\t\t\t\t enum dlb2_qid_map_state new_state)\n+{\n+\tenum dlb2_qid_map_state curr_state = port->qid_map[slot].state;\n+\tstruct dlb2_hw_domain *domain;\n+\tint domain_id;\n+\n+\tdomain_id = port->domain_id.phys_id;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, false, 0);\n+\tif (!domain) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: unable to find domain %d\\n\",\n+\t\t\t __func__, domain_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (curr_state) {\n+\tcase DLB2_QUEUE_UNMAPPED:\n+\t\tswitch (new_state) {\n+\t\tcase DLB2_QUEUE_MAPPED:\n+\t\t\tqueue->num_mappings++;\n+\t\t\tport->num_mappings++;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_MAP_IN_PROG:\n+\t\t\tqueue->num_pending_additions++;\n+\t\t\tdomain->num_pending_additions++;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto error;\n+\t\t}\n+\t\tbreak;\n+\tcase DLB2_QUEUE_MAPPED:\n+\t\tswitch (new_state) {\n+\t\tcase DLB2_QUEUE_UNMAPPED:\n+\t\t\tqueue->num_mappings--;\n+\t\t\tport->num_mappings--;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n+\t\t\tport->num_pending_removals++;\n+\t\t\tdomain->num_pending_removals++;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_MAPPED:\n+\t\t\t/* Priority change, nothing to update */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto error;\n+\t\t}\n+\t\tbreak;\n+\tcase DLB2_QUEUE_MAP_IN_PROG:\n+\t\tswitch (new_state) {\n+\t\tcase DLB2_QUEUE_UNMAPPED:\n+\t\t\tqueue->num_pending_additions--;\n+\t\t\tdomain->num_pending_additions--;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_MAPPED:\n+\t\t\tqueue->num_mappings++;\n+\t\t\tport->num_mappings++;\n+\t\t\tqueue->num_pending_additions--;\n+\t\t\tdomain->num_pending_additions--;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto error;\n+\t\t}\n+\t\tbreak;\n+\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n+\t\tswitch (new_state) {\n+\t\tcase DLB2_QUEUE_UNMAPPED:\n+\t\t\tport->num_pending_removals--;\n+\t\t\tdomain->num_pending_removals--;\n+\t\t\tqueue->num_mappings--;\n+\t\t\tport->num_mappings--;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_MAPPED:\n+\t\t\tport->num_pending_removals--;\n+\t\t\tdomain->num_pending_removals--;\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:\n+\t\t\t/* Nothing to update */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto error;\n+\t\t}\n+\t\tbreak;\n+\tcase DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:\n+\t\tswitch (new_state) {\n+\t\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n+\t\t\t/* Nothing to update */\n+\t\t\tbreak;\n+\t\tcase DLB2_QUEUE_UNMAPPED:\n+\t\t\t/*\n+\t\t\t * An UNMAP_IN_PROG_PENDING_MAP slot briefly\n+\t\t\t * becomes UNMAPPED before it transitions to\n+\t\t\t * MAP_IN_PROG.\n+\t\t\t */\n+\t\t\tqueue->num_mappings--;\n+\t\t\tport->num_mappings--;\n+\t\t\tport->num_pending_removals--;\n+\t\t\tdomain->num_pending_removals--;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto error;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto error;\n+\t}\n+\n+\tport->qid_map[slot].state = new_state;\n+\n+\tDLB2_HW_DBG(hw,\n+\t\t \"[%s()] queue %d -> port %d state transition (%d -> %d)\\n\",\n+\t\t __func__, queue->id.phys_id, port->id.phys_id,\n+\t\t curr_state, new_state);\n+\treturn 0;\n+\n+error:\n+\tDLB2_HW_ERR(hw,\n+\t\t \"[%s()] Internal error: invalid queue %d -> port %d state transition (%d -> %d)\\n\",\n+\t\t __func__, queue->id.phys_id, port->id.phys_id,\n+\t\t curr_state, new_state);\n+\treturn -EFAULT;\n+}\n+\n+static bool dlb2_port_find_slot(struct dlb2_ldb_port *port,\n+\t\t\t\tenum dlb2_qid_map_state state,\n+\t\t\t\tint *slot)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n+\t\tif (port->qid_map[i].state == state)\n+\t\t\tbreak;\n+\t}\n+\n+\t*slot = i;\n+\n+\treturn (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);\n+}\n+\n+static bool dlb2_port_find_slot_queue(struct dlb2_ldb_port *port,\n+\t\t\t\t enum dlb2_qid_map_state state,\n+\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t int *slot)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n+\t\tif (port->qid_map[i].state == state &&\n+\t\t port->qid_map[i].qid == queue->id.phys_id)\n+\t\t\tbreak;\n+\t}\n+\n+\t*slot = i;\n+\n+\treturn (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);\n+}\n+\n+/*\n+ * dlb2_ldb_queue_{enable, disable}_mapped_cqs() don't operate exactly as\n+ * their function names imply, and should only be called by the dynamic CQ\n+ * mapping code.\n+ */\n+static void dlb2_ldb_queue_disable_mapped_cqs(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint slot, i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tenum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;\n+\n+\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n+\t\t\t\t\t\t queue, &slot))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (port->enabled)\n+\t\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n+\t\t}\n+\t}\n+}\n+\n+static void dlb2_ldb_queue_enable_mapped_cqs(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint slot, i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tenum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;\n+\n+\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n+\t\t\t\t\t\t queue, &slot))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (port->enabled)\n+\t\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\t\t}\n+\t}\n+}\n+\n+static void dlb2_ldb_port_clear_queue_if_status(struct dlb2_hw *hw,\n+\t\t\t\t\t\tstruct dlb2_ldb_port *port,\n+\t\t\t\t\t\tint slot)\n+{\n+\tunion dlb2_lsp_ldb_sched_ctrl r0 = { {0} };\n+\n+\tr0.field.cq = port->id.phys_id;\n+\tr0.field.qidix = slot;\n+\tr0.field.value = 0;\n+\tr0.field.inflight_ok_v = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static void dlb2_ldb_port_set_queue_if_status(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t\t int slot)\n+{\n+\tunion dlb2_lsp_ldb_sched_ctrl r0 = { {0} };\n+\n+\tr0.field.cq = port->id.phys_id;\n+\tr0.field.qidix = slot;\n+\tr0.field.value = 1;\n+\tr0.field.inflight_ok_v = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static int dlb2_ldb_port_map_qid_static(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_ldb_port *p,\n+\t\t\t\t\tstruct dlb2_ldb_queue *q,\n+\t\t\t\t\tu8 priority)\n+{\n+\tunion dlb2_lsp_cq2priov r0;\n+\tunion dlb2_lsp_cq2qid0 r1;\n+\tunion dlb2_atm_qid2cqidix_00 r2;\n+\tunion dlb2_lsp_qid2cqidix_00 r3;\n+\tunion dlb2_lsp_qid2cqidix2_00 r4;\n+\tenum dlb2_qid_map_state state;\n+\tint i;\n+\n+\t/* Look for a pending or already mapped slot, else an unused slot */\n+\tif (!dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAP_IN_PROG, q, &i) &&\n+\t !dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAPPED, q, &i) &&\n+\t !dlb2_port_find_slot(p, DLB2_QUEUE_UNMAPPED, &i)) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: CQ has no available QID mapping slots\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: port slot tracking failed\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* Read-modify-write the priority and valid bit register */\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id));\n+\n+\tr0.field.v |= 1 << i;\n+\tr0.field.prio |= (priority & 0x7) << i * 3;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id), r0.val);\n+\n+\t/* Read-modify-write the QID map register */\n+\tif (i < 4)\n+\t\tr1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID0(p->id.phys_id));\n+\telse\n+\t\tr1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID1(p->id.phys_id));\n+\n+\tif (i == 0 || i == 4)\n+\t\tr1.field.qid_p0 = q->id.phys_id;\n+\tif (i == 1 || i == 5)\n+\t\tr1.field.qid_p1 = q->id.phys_id;\n+\tif (i == 2 || i == 6)\n+\t\tr1.field.qid_p2 = q->id.phys_id;\n+\tif (i == 3 || i == 7)\n+\t\tr1.field.qid_p3 = q->id.phys_id;\n+\n+\tif (i < 4)\n+\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2QID0(p->id.phys_id), r1.val);\n+\telse\n+\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2QID1(p->id.phys_id), r1.val);\n+\n+\tr2.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_ATM_QID2CQIDIX(q->id.phys_id,\n+\t\t\t\t\t\t p->id.phys_id / 4));\n+\n+\tr3.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID2CQIDIX(q->id.phys_id,\n+\t\t\t\t\t\t p->id.phys_id / 4));\n+\n+\tr4.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID2CQIDIX2(q->id.phys_id,\n+\t\t\t\t\t\t p->id.phys_id / 4));\n+\n+\tswitch (p->id.phys_id % 4) {\n+\tcase 0:\n+\t\tr2.field.cq_p0 |= 1 << i;\n+\t\tr3.field.cq_p0 |= 1 << i;\n+\t\tr4.field.cq_p0 |= 1 << i;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tr2.field.cq_p1 |= 1 << i;\n+\t\tr3.field.cq_p1 |= 1 << i;\n+\t\tr4.field.cq_p1 |= 1 << i;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tr2.field.cq_p2 |= 1 << i;\n+\t\tr3.field.cq_p2 |= 1 << i;\n+\t\tr4.field.cq_p2 |= 1 << i;\n+\t\tbreak;\n+\n+\tcase 3:\n+\t\tr2.field.cq_p3 |= 1 << i;\n+\t\tr3.field.cq_p3 |= 1 << i;\n+\t\tr4.field.cq_p3 |= 1 << i;\n+\t\tbreak;\n+\t}\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_ATM_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),\n+\t\t r2.val);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),\n+\t\t r3.val);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID2CQIDIX2(q->id.phys_id, p->id.phys_id / 4),\n+\t\t r4.val);\n+\n+\tdlb2_flush_csr(hw);\n+\n+\tp->qid_map[i].qid = q->id.phys_id;\n+\tp->qid_map[i].priority = priority;\n+\n+\tstate = DLB2_QUEUE_MAPPED;\n+\n+\treturn dlb2_port_slot_state_transition(hw, p, q, i, state);\n+}\n+\n+static int dlb2_ldb_port_set_has_work_bits(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t\t int slot)\n+{\n+\tunion dlb2_lsp_qid_aqed_active_cnt r0;\n+\tunion dlb2_lsp_qid_ldb_enqueue_cnt r1;\n+\tunion dlb2_lsp_ldb_sched_ctrl r2 = { {0} };\n+\n+\t/* Set the atomic scheduling haswork bit */\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_AQED_ACTIVE_CNT(queue->id.phys_id));\n+\n+\tr2.field.cq = port->id.phys_id;\n+\tr2.field.qidix = slot;\n+\tr2.field.value = 1;\n+\tr2.field.rlist_haswork_v = r0.field.count > 0;\n+\n+\t/* Set the non-atomic scheduling haswork bit */\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n+\n+\tr1.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_LDB_ENQUEUE_CNT(queue->id.phys_id));\n+\n+\tmemset(&r2, 0, sizeof(r2));\n+\n+\tr2.field.cq = port->id.phys_id;\n+\tr2.field.qidix = slot;\n+\tr2.field.value = 1;\n+\tr2.field.nalb_haswork_v = (r1.field.count > 0);\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n+\n+\tdlb2_flush_csr(hw);\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_ldb_port_clear_has_work_bits(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t\t u8 slot)\n+{\n+\tunion dlb2_lsp_ldb_sched_ctrl r2 = { {0} };\n+\n+\tr2.field.cq = port->id.phys_id;\n+\tr2.field.qidix = slot;\n+\tr2.field.value = 0;\n+\tr2.field.rlist_haswork_v = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n+\n+\tmemset(&r2, 0, sizeof(r2));\n+\n+\tr2.field.cq = port->id.phys_id;\n+\tr2.field.qidix = slot;\n+\tr2.field.value = 0;\n+\tr2.field.nalb_haswork_v = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n+\n+\tdlb2_flush_csr(hw);\n+}\n+\n+static void dlb2_ldb_queue_set_inflight_limit(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\tunion dlb2_lsp_qid_ldb_infl_lim r0 = { {0} };\n+\n+\tr0.field.limit = queue->num_qid_inflights;\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), r0.val);\n+}\n+\n+static void dlb2_ldb_queue_clear_inflight_limit(struct dlb2_hw *hw,\n+\t\t\t\t\t\tstruct dlb2_ldb_queue *queue)\n+{\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id),\n+\t\t DLB2_LSP_QID_LDB_INFL_LIM_RST);\n+}\n+\n+static int dlb2_ldb_port_finish_map_qid_dynamic(struct dlb2_hw *hw,\n+\t\t\t\t\t\tstruct dlb2_hw_domain *domain,\n+\t\t\t\t\t\tstruct dlb2_ldb_port *port,\n+\t\t\t\t\t\tstruct dlb2_ldb_queue *queue)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_lsp_qid_ldb_infl_cnt r0;\n+\tenum dlb2_qid_map_state state;\n+\tint slot, ret, i;\n+\tu8 prio;\n+\tRTE_SET_USED(iter);\n+\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n+\n+\tif (r0.field.count) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: non-zero QID inflight count\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Static map the port and set its corresponding has_work bits.\n+\t */\n+\tstate = DLB2_QUEUE_MAP_IN_PROG;\n+\tif (!dlb2_port_find_slot_queue(port, state, queue, &slot))\n+\t\treturn -EINVAL;\n+\n+\tif (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: port slot tracking failed\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tprio = port->qid_map[slot].priority;\n+\n+\t/*\n+\t * Update the CQ2QID, CQ2PRIOV, and QID2CQIDX registers, and\n+\t * the port's qid_map state.\n+\t */\n+\tret = dlb2_ldb_port_map_qid_static(hw, port, queue, prio);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dlb2_ldb_port_set_has_work_bits(hw, port, queue, slot);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * Ensure IF_status(cq,qid) is 0 before enabling the port to\n+\t * prevent spurious schedules to cause the queue's inflight\n+\t * count to increase.\n+\t */\n+\tdlb2_ldb_port_clear_queue_if_status(hw, port, slot);\n+\n+\t/* Reset the queue's inflight status */\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tstate = DLB2_QUEUE_MAPPED;\n+\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n+\t\t\t\t\t\t queue, &slot))\n+\t\t\t\tcontinue;\n+\n+\t\t\tdlb2_ldb_port_set_queue_if_status(hw, port, slot);\n+\t\t}\n+\t}\n+\n+\tdlb2_ldb_queue_set_inflight_limit(hw, queue);\n+\n+\t/* Re-enable CQs mapped to this queue */\n+\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n+\n+\t/* If this queue has other mappings pending, clear its inflight limit */\n+\tif (queue->num_pending_additions > 0)\n+\t\tdlb2_ldb_queue_clear_inflight_limit(hw, queue);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_ldb_port_map_qid_dynamic() - perform a \"dynamic\" QID->CQ mapping\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @port: load-balanced port\n+ * @queue: load-balanced queue\n+ * @priority: queue servicing priority\n+ *\n+ * Returns 0 if the queue was mapped, 1 if the mapping is scheduled to occur\n+ * at a later point, and <0 if an error occurred.\n+ */\n+static int dlb2_ldb_port_map_qid_dynamic(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t\t u8 priority)\n+{\n+\tunion dlb2_lsp_qid_ldb_infl_cnt r0 = { {0} };\n+\tenum dlb2_qid_map_state state;\n+\tstruct dlb2_hw_domain *domain;\n+\tint domain_id, slot, ret;\n+\n+\tdomain_id = port->domain_id.phys_id;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, false, 0);\n+\tif (!domain) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: unable to find domain %d\\n\",\n+\t\t\t __func__, port->domain_id.phys_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Set the QID inflight limit to 0 to prevent further scheduling of the\n+\t * queue.\n+\t */\n+\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), 0);\n+\n+\tif (!dlb2_port_find_slot(port, DLB2_QUEUE_UNMAPPED, &slot)) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"Internal error: No available unmapped slots\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: port slot tracking failed\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tport->qid_map[slot].qid = queue->id.phys_id;\n+\tport->qid_map[slot].priority = priority;\n+\n+\tstate = DLB2_QUEUE_MAP_IN_PROG;\n+\tret = dlb2_port_slot_state_transition(hw, port, queue, slot, state);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n+\n+\tif (r0.field.count) {\n+\t\t/*\n+\t\t * The queue is owed completions so it's not safe to map it\n+\t\t * yet. Schedule a kernel thread to complete the mapping later,\n+\t\t * once software has completed all the queue's inflight events.\n+\t\t */\n+\t\tif (!os_worker_active(hw))\n+\t\t\tos_schedule_work(hw);\n+\n+\t\treturn 1;\n+\t}\n+\n+\t/*\n+\t * Disable the affected CQ, and the CQs already mapped to the QID,\n+\t * before reading the QID's inflight count a second time. There is an\n+\t * unlikely race in which the QID may schedule one more QE after we\n+\t * read an inflight count of 0, and disabling the CQs guarantees that\n+\t * the race will not occur after a re-read of the inflight count\n+\t * register.\n+\t */\n+\tif (port->enabled)\n+\t\tdlb2_ldb_port_cq_disable(hw, port);\n+\n+\tdlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);\n+\n+\tr0.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n+\n+\tif (r0.field.count) {\n+\t\tif (port->enabled)\n+\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\n+\t\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n+\n+\t\t/*\n+\t\t * The queue is owed completions so it's not safe to map it\n+\t\t * yet. Schedule a kernel thread to complete the mapping later,\n+\t\t * once software has completed all the queue's inflight events.\n+\t\t */\n+\t\tif (!os_worker_active(hw))\n+\t\t\tos_schedule_work(hw);\n+\n+\t\treturn 1;\n+\t}\n+\n+\treturn dlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);\n+}\n+\n+static void dlb2_domain_finish_map_port(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain,\n+\t\t\t\t\tstruct dlb2_ldb_port *port)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n+\t\tunion dlb2_lsp_qid_ldb_infl_cnt r0;\n+\t\tstruct dlb2_ldb_queue *queue;\n+\t\tint qid;\n+\n+\t\tif (port->qid_map[i].state != DLB2_QUEUE_MAP_IN_PROG)\n+\t\t\tcontinue;\n+\n+\t\tqid = port->qid_map[i].qid;\n+\n+\t\tqueue = dlb2_get_ldb_queue_from_id(hw, qid, false, 0);\n+\n+\t\tif (!queue) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: unable to find queue %d\\n\",\n+\t\t\t\t __func__, qid);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));\n+\n+\t\tif (r0.field.count)\n+\t\t\tcontinue;\n+\n+\t\t/*\n+\t\t * Disable the affected CQ, and the CQs already mapped to the\n+\t\t * QID, before reading the QID's inflight count a second time.\n+\t\t * There is an unlikely race in which the QID may schedule one\n+\t\t * more QE after we read an inflight count of 0, and disabling\n+\t\t * the CQs guarantees that the race will not occur after a\n+\t\t * re-read of the inflight count register.\n+\t\t */\n+\t\tif (port->enabled)\n+\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n+\n+\t\tdlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);\n+\n+\t\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));\n+\n+\t\tif (r0.field.count) {\n+\t\t\tif (port->enabled)\n+\t\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\n+\t\t\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n+\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tdlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);\n+\t}\n+}\n+\n+static unsigned int\n+dlb2_domain_finish_map_qid_procedures(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tif (!domain->configured || domain->num_pending_additions == 0)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n+\t\t\tdlb2_domain_finish_map_port(hw, domain, port);\n+\t}\n+\n+\treturn domain->num_pending_additions;\n+}\n+\n+static int dlb2_ldb_port_unmap_qid(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\tenum dlb2_qid_map_state mapped, in_progress, pending_map, unmapped;\n+\tunion dlb2_lsp_cq2priov r0;\n+\tunion dlb2_atm_qid2cqidix_00 r1;\n+\tunion dlb2_lsp_qid2cqidix_00 r2;\n+\tunion dlb2_lsp_qid2cqidix2_00 r3;\n+\tu32 queue_id;\n+\tu32 port_id;\n+\tint i;\n+\n+\t/* Find the queue's slot */\n+\tmapped = DLB2_QUEUE_MAPPED;\n+\tin_progress = DLB2_QUEUE_UNMAP_IN_PROG;\n+\tpending_map = DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP;\n+\n+\tif (!dlb2_port_find_slot_queue(port, mapped, queue, &i) &&\n+\t !dlb2_port_find_slot_queue(port, in_progress, queue, &i) &&\n+\t !dlb2_port_find_slot_queue(port, pending_map, queue, &i)) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: QID %d isn't mapped\\n\",\n+\t\t\t __func__, __LINE__, queue->id.phys_id);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: port slot tracking failed\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tport_id = port->id.phys_id;\n+\tqueue_id = queue->id.phys_id;\n+\n+\t/* Read-modify-write the priority and valid bit register */\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(port_id));\n+\n+\tr0.field.v &= ~(1 << i);\n+\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port_id), r0.val);\n+\n+\tr1.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4));\n+\n+\tr2.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4));\n+\n+\tr3.val = DLB2_CSR_RD(hw,\n+\t\t\t DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4));\n+\n+\tswitch (port_id % 4) {\n+\tcase 0:\n+\t\tr1.field.cq_p0 &= ~(1 << i);\n+\t\tr2.field.cq_p0 &= ~(1 << i);\n+\t\tr3.field.cq_p0 &= ~(1 << i);\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tr1.field.cq_p1 &= ~(1 << i);\n+\t\tr2.field.cq_p1 &= ~(1 << i);\n+\t\tr3.field.cq_p1 &= ~(1 << i);\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tr1.field.cq_p2 &= ~(1 << i);\n+\t\tr2.field.cq_p2 &= ~(1 << i);\n+\t\tr3.field.cq_p2 &= ~(1 << i);\n+\t\tbreak;\n+\n+\tcase 3:\n+\t\tr1.field.cq_p3 &= ~(1 << i);\n+\t\tr2.field.cq_p3 &= ~(1 << i);\n+\t\tr3.field.cq_p3 &= ~(1 << i);\n+\t\tbreak;\n+\t}\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4),\n+\t\t r1.val);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4),\n+\t\t r2.val);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4),\n+\t\t r3.val);\n+\n+\tdlb2_flush_csr(hw);\n+\n+\tunmapped = DLB2_QUEUE_UNMAPPED;\n+\n+\treturn dlb2_port_slot_state_transition(hw, port, queue, i, unmapped);\n+}\n+\n+static int dlb2_ldb_port_map_qid(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t u8 prio)\n+{\n+\tif (domain->started)\n+\t\treturn dlb2_ldb_port_map_qid_dynamic(hw, port, queue, prio);\n+\telse\n+\t\treturn dlb2_ldb_port_map_qid_static(hw, port, queue, prio);\n+}\n+\n+static void\n+dlb2_domain_finish_unmap_port_slot(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t int slot)\n+{\n+\tenum dlb2_qid_map_state state;\n+\tstruct dlb2_ldb_queue *queue;\n+\n+\tqueue = &hw->rsrcs.ldb_queues[port->qid_map[slot].qid];\n+\n+\tstate = port->qid_map[slot].state;\n+\n+\t/* Update the QID2CQIDX and CQ2QID vectors */\n+\tdlb2_ldb_port_unmap_qid(hw, port, queue);\n+\n+\t/*\n+\t * Ensure the QID will not be serviced by this {CQ, slot} by clearing\n+\t * the has_work bits\n+\t */\n+\tdlb2_ldb_port_clear_has_work_bits(hw, port, slot);\n+\n+\t/* Reset the {CQ, slot} to its default state */\n+\tdlb2_ldb_port_set_queue_if_status(hw, port, slot);\n+\n+\t/* Re-enable the CQ if it wasn't manually disabled by the user */\n+\tif (port->enabled)\n+\t\tdlb2_ldb_port_cq_enable(hw, port);\n+\n+\t/*\n+\t * If there is a mapping that is pending this slot's removal, perform\n+\t * the mapping now.\n+\t */\n+\tif (state == DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP) {\n+\t\tstruct dlb2_ldb_port_qid_map *map;\n+\t\tstruct dlb2_ldb_queue *map_queue;\n+\t\tu8 prio;\n+\n+\t\tmap = &port->qid_map[slot];\n+\n+\t\tmap->qid = map->pending_qid;\n+\t\tmap->priority = map->pending_priority;\n+\n+\t\tmap_queue = &hw->rsrcs.ldb_queues[map->qid];\n+\t\tprio = map->priority;\n+\n+\t\tdlb2_ldb_port_map_qid(hw, domain, port, map_queue, prio);\n+\t}\n+}\n+\n+static bool dlb2_domain_finish_unmap_port(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tunion dlb2_lsp_cq_ldb_infl_cnt r0;\n+\tint i;\n+\n+\tif (port->num_pending_removals == 0)\n+\t\treturn false;\n+\n+\t/*\n+\t * The unmap requires all the CQ's outstanding inflights to be\n+\t * completed.\n+\t */\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_LDB_INFL_CNT(port->id.phys_id));\n+\tif (r0.field.count > 0)\n+\t\treturn false;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n+\t\tstruct dlb2_ldb_port_qid_map *map;\n+\n+\t\tmap = &port->qid_map[i];\n+\n+\t\tif (map->state != DLB2_QUEUE_UNMAP_IN_PROG &&\n+\t\t map->state != DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP)\n+\t\t\tcontinue;\n+\n+\t\tdlb2_domain_finish_unmap_port_slot(hw, domain, port, i);\n+\t}\n+\n+\treturn true;\n+}\n+\n+static unsigned int\n+dlb2_domain_finish_unmap_qid_procedures(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tif (!domain->configured || domain->num_pending_removals == 0)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n+\t\t\tdlb2_domain_finish_unmap_port(hw, domain, port);\n+\t}\n+\n+\treturn domain->num_pending_removals;\n+}\n+\n+static void dlb2_domain_disable_ldb_cqs(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tport->enabled = false;\n+\n+\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n+\t\t}\n+\t}\n+}\n+\n+static void dlb2_log_reset_domain(struct dlb2_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 reset domain:\\n\");\n+\tif (vdev_req)\n+\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n+\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\", domain_id);\n+}\n+\n+static void dlb2_domain_disable_dir_vpps(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_sys_vf_dir_vpp_v r1;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tRTE_SET_USED(iter);\n+\n+\tr1.field.vpp_v = 0;\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter) {\n+\t\tunsigned int offs;\n+\t\tu32 virt_id;\n+\n+\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\tvirt_id = port->id.virt_id;\n+\t\telse\n+\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;\n+\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), r1.val);\n+\t}\n+}\n+\n+static void dlb2_domain_disable_ldb_vpps(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_sys_vf_ldb_vpp_v r1;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tr1.field.vpp_v = 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tunsigned int offs;\n+\t\t\tu32 virt_id;\n+\n+\t\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\t\tvirt_id = port->id.virt_id;\n+\t\t\telse\n+\t\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\t\toffs = vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;\n+\n+\t\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP_V(offs), r1.val);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+dlb2_domain_disable_ldb_port_interrupts(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_chp_ldb_cq_int_enb r0 = { {0} };\n+\tunion dlb2_chp_ldb_cq_wd_enb r1 = { {0} };\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tr0.field.en_tim = 0;\n+\tr0.field.en_depth = 0;\n+\n+\tr1.field.wd_enable = 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_CHP_LDB_CQ_INT_ENB(port->id.phys_id),\n+\t\t\t\t r0.val);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_CHP_LDB_CQ_WD_ENB(port->id.phys_id),\n+\t\t\t\t r1.val);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+dlb2_domain_disable_dir_port_interrupts(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_chp_dir_cq_int_enb r0 = { {0} };\n+\tunion dlb2_chp_dir_cq_wd_enb r1 = { {0} };\n+\tstruct dlb2_dir_pq_pair *port;\n+\tRTE_SET_USED(iter);\n+\n+\tr0.field.en_tim = 0;\n+\tr0.field.en_depth = 0;\n+\n+\tr1.field.wd_enable = 0;\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter) {\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_CHP_DIR_CQ_INT_ENB(port->id.phys_id),\n+\t\t\t r0.val);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_CHP_DIR_CQ_WD_ENB(port->id.phys_id),\n+\t\t\t r1.val);\n+\t}\n+}\n+\n+static void\n+dlb2_domain_disable_ldb_queue_write_perms(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tint domain_offset = domain->id.phys_id * DLB2_MAX_NUM_LDB_QUEUES;\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_queue *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter) {\n+\t\tunion dlb2_sys_ldb_vasqid_v r0 = { {0} };\n+\t\tunion dlb2_sys_ldb_qid2vqid r1 = { {0} };\n+\t\tunion dlb2_sys_vf_ldb_vqid_v r2 = { {0} };\n+\t\tunion dlb2_sys_vf_ldb_vqid2qid r3 = { {0} };\n+\t\tint idx;\n+\n+\t\tidx = domain_offset + queue->id.phys_id;\n+\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_VASQID_V(idx), r0.val);\n+\n+\t\tif (queue->id.vdev_owned) {\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_LDB_QID2VQID(queue->id.phys_id),\n+\t\t\t\t r1.val);\n+\n+\t\t\tidx = queue->id.vdev_id * DLB2_MAX_NUM_LDB_QUEUES +\n+\t\t\t\tqueue->id.virt_id;\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_VF_LDB_VQID_V(idx),\n+\t\t\t\t r2.val);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_VF_LDB_VQID2QID(idx),\n+\t\t\t\t r3.val);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+dlb2_domain_disable_dir_queue_write_perms(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tint domain_offset = domain->id.phys_id * DLB2_MAX_NUM_DIR_PORTS;\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, queue, iter) {\n+\t\tunion dlb2_sys_dir_vasqid_v r0 = { {0} };\n+\t\tunion dlb2_sys_vf_dir_vqid_v r1 = { {0} };\n+\t\tunion dlb2_sys_vf_dir_vqid2qid r2 = { {0} };\n+\t\tint idx;\n+\n+\t\tidx = domain_offset + queue->id.phys_id;\n+\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(idx), r0.val);\n+\n+\t\tif (queue->id.vdev_owned) {\n+\t\t\tidx = queue->id.vdev_id * DLB2_MAX_NUM_DIR_PORTS +\n+\t\t\t\tqueue->id.virt_id;\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_VF_DIR_VQID_V(idx),\n+\t\t\t\t r1.val);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_VF_DIR_VQID2QID(idx),\n+\t\t\t\t r2.val);\n+\t\t}\n+\t}\n+}\n+\n+static void dlb2_domain_disable_ldb_seq_checks(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_chp_sn_chk_enbl r1;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tr1.field.en = 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_CHP_SN_CHK_ENBL(port->id.phys_id),\n+\t\t\t\t r1.val);\n+\t}\n+}\n+\n+static int dlb2_domain_wait_for_ldb_cqs_to_empty(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tint i;\n+\n+\t\t\tfor (i = 0; i < DLB2_MAX_CQ_COMP_CHECK_LOOPS; i++) {\n+\t\t\t\tif (dlb2_ldb_cq_inflight_count(hw, port) == 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (i == DLB2_MAX_CQ_COMP_CHECK_LOOPS) {\n+\t\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t\t \"[%s()] Internal error: failed to flush load-balanced port %d's completions.\\n\",\n+\t\t\t\t\t __func__, port->id.phys_id);\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_domain_disable_dir_cqs(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter) {\n+\t\tport->enabled = false;\n+\n+\t\tdlb2_dir_port_cq_disable(hw, port);\n+\t}\n+}\n+\n+static void\n+dlb2_domain_disable_dir_producer_ports(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tunion dlb2_sys_dir_pp_v r1;\n+\tRTE_SET_USED(iter);\n+\n+\tr1.field.pp_v = 0;\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter)\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_DIR_PP_V(port->id.phys_id),\n+\t\t\t r1.val);\n+}\n+\n+static void\n+dlb2_domain_disable_ldb_producer_ports(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tunion dlb2_sys_ldb_pp_v r1;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tr1.field.pp_v = 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_SYS_LDB_PP_V(port->id.phys_id),\n+\t\t\t\t r1.val);\n+\t}\n+}\n+\n+static int dlb2_domain_verify_reset_success(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *dir_port;\n+\tstruct dlb2_ldb_port *ldb_port;\n+\tstruct dlb2_ldb_queue *queue;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\t/*\n+\t * Confirm that all the domain's queue's inflight counts and AQED\n+\t * active counts are 0.\n+\t */\n+\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter) {\n+\t\tif (!dlb2_ldb_queue_is_empty(hw, queue)) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: failed to empty ldb queue %d\\n\",\n+\t\t\t\t __func__, queue->id.phys_id);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\t/* Confirm that all the domain's CQs inflight and token counts are 0. */\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], ldb_port, iter) {\n+\t\t\tif (dlb2_ldb_cq_inflight_count(hw, ldb_port) ||\n+\t\t\t dlb2_ldb_cq_token_count(hw, ldb_port)) {\n+\t\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t\t \"[%s()] Internal error: failed to empty ldb port %d\\n\",\n+\t\t\t\t\t __func__, ldb_port->id.phys_id);\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, dir_port, iter) {\n+\t\tif (!dlb2_dir_queue_is_empty(hw, dir_port)) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: failed to empty dir queue %d\\n\",\n+\t\t\t\t __func__, dir_port->id.phys_id);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\tif (dlb2_dir_cq_token_count(hw, dir_port)) {\n+\t\t\tDLB2_HW_ERR(hw,\n+\t\t\t\t \"[%s()] Internal error: failed to empty dir port %d\\n\",\n+\t\t\t\t __func__, dir_port->id.phys_id);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void __dlb2_domain_reset_ldb_port_registers(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_ldb_port *port)\n+{\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_PP2VAS(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_PP2VAS_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ2VAS(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ2VAS_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_PP2VDEV(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_PP2VDEV_RST);\n+\n+\tif (port->id.vdev_owned) {\n+\t\tunsigned int offs;\n+\t\tu32 virt_id;\n+\n+\t\t/*\n+\t\t * DLB uses producer port address bits 17:12 to determine the\n+\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n+\t\t * through the PF MMIO window for the physical producer port,\n+\t\t * so for translation purposes the virtual and physical port\n+\t\t * IDs are equal.\n+\t\t */\n+\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\tvirt_id = port->id.virt_id;\n+\t\telse\n+\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\toffs = port->id.vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_VF_LDB_VPP2PP(offs),\n+\t\t\t DLB2_SYS_VF_LDB_VPP2PP_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_VF_LDB_VPP_V(offs),\n+\t\t\t DLB2_SYS_VF_LDB_VPP_V_RST);\n+\t}\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_PP_V(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_PP_V_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_DSBL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_DEPTH(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_DEPTH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_INFL_LIM(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_INFL_LIM_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_HIST_LIST_LIM(port->id.phys_id),\n+\t\t DLB2_CHP_HIST_LIST_LIM_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_HIST_LIST_BASE(port->id.phys_id),\n+\t\t DLB2_CHP_HIST_LIST_BASE_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_HIST_LIST_POP_PTR(port->id.phys_id),\n+\t\t DLB2_CHP_HIST_LIST_POP_PTR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_HIST_LIST_PUSH_PTR(port->id.phys_id),\n+\t\t DLB2_CHP_HIST_LIST_PUSH_PTR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_TMR_THRSH(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_TMR_THRSH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_INT_ENB(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_INT_ENB_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ_ISR(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ_ISR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_WPTR(port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_WPTR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_TKN_CNT_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ_ADDR_L(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ_ADDR_L_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ_ADDR_U(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ_ADDR_U_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ_AT(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ_AT_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ_PASID(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ_PASID_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_LDB_CQ2VF_PF_RO(port->id.phys_id),\n+\t\t DLB2_SYS_LDB_CQ2VF_PF_RO_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ2QID0(port->id.phys_id),\n+\t\t DLB2_LSP_CQ2QID0_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ2QID1(port->id.phys_id),\n+\t\t DLB2_LSP_CQ2QID1_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ2PRIOV(port->id.phys_id),\n+\t\t DLB2_LSP_CQ2PRIOV_RST);\n+}\n+\n+static void dlb2_domain_reset_ldb_port_registers(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\tRTE_SET_USED(iter);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n+\t\t\t__dlb2_domain_reset_ldb_port_registers(hw, port);\n+\t}\n+}\n+\n+static void\n+__dlb2_domain_reset_dir_port_registers(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_dir_pq_pair *port)\n+{\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ2VAS(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ2VAS_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_DSBL(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_DIR_DSBL_RST);\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_OPT_CLR, port->id.phys_id);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_DEPTH(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_DEPTH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_TMR_THRSH(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_TMR_THRSH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_INT_ENB(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_INT_ENB_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_ISR(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_ISR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_WPTR(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_WPTR_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_DIR_TKN_CNT_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_ADDR_L(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_ADDR_L_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_ADDR_U(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_ADDR_U_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_AT(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_AT_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_PASID(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_PASID_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ_FMT(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ_FMT_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_CQ2VF_PF_RO(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_CQ2VF_PF_RO_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(port->id.phys_id),\n+\t\t DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_PP2VAS(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_PP2VAS_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ2VAS(port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ2VAS_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_PP2VDEV(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_PP2VDEV_RST);\n+\n+\tif (port->id.vdev_owned) {\n+\t\tunsigned int offs;\n+\t\tu32 virt_id;\n+\n+\t\t/*\n+\t\t * DLB uses producer port address bits 17:12 to determine the\n+\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n+\t\t * through the PF MMIO window for the physical producer port,\n+\t\t * so for translation purposes the virtual and physical port\n+\t\t * IDs are equal.\n+\t\t */\n+\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\tvirt_id = port->id.virt_id;\n+\t\telse\n+\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\toffs = port->id.vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_VF_DIR_VPP2PP(offs),\n+\t\t\t DLB2_SYS_VF_DIR_VPP2PP_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_VF_DIR_VPP_V(offs),\n+\t\t\t DLB2_SYS_VF_DIR_VPP_V_RST);\n+\t}\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_SYS_DIR_PP_V(port->id.phys_id),\n+\t\t DLB2_SYS_DIR_PP_V_RST);\n+}\n+\n+static void dlb2_domain_reset_dir_port_registers(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter)\n+\t\t__dlb2_domain_reset_dir_port_registers(hw, port);\n+}\n+\n+static void dlb2_domain_reset_ldb_queue_registers(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_queue *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter) {\n+\t\tunsigned int queue_id = queue->id.phys_id;\n+\t\tint i;\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(queue_id),\n+\t\t\t DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(queue_id),\n+\t\t\t DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(queue_id),\n+\t\t\t DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(queue_id),\n+\t\t\t DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_NALDB_MAX_DEPTH(queue_id),\n+\t\t\t DLB2_LSP_QID_NALDB_MAX_DEPTH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_LDB_INFL_LIM(queue_id),\n+\t\t\t DLB2_LSP_QID_LDB_INFL_LIM_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_AQED_ACTIVE_LIM(queue_id),\n+\t\t\t DLB2_LSP_QID_AQED_ACTIVE_LIM_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_ATM_DEPTH_THRSH(queue_id),\n+\t\t\t DLB2_LSP_QID_ATM_DEPTH_THRSH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_NALDB_DEPTH_THRSH(queue_id),\n+\t\t\t DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_LDB_QID_ITS(queue_id),\n+\t\t\t DLB2_SYS_LDB_QID_ITS_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_CHP_ORD_QID_SN(queue_id),\n+\t\t\t DLB2_CHP_ORD_QID_SN_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_CHP_ORD_QID_SN_MAP(queue_id),\n+\t\t\t DLB2_CHP_ORD_QID_SN_MAP_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_LDB_QID_V(queue_id),\n+\t\t\t DLB2_SYS_LDB_QID_V_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_LDB_QID_CFG_V(queue_id),\n+\t\t\t DLB2_SYS_LDB_QID_CFG_V_RST);\n+\n+\t\tif (queue->sn_cfg_valid) {\n+\t\t\tu32 offs[2];\n+\n+\t\t\toffs[0] = DLB2_RO_PIPE_GRP_0_SLT_SHFT(queue->sn_slot);\n+\t\t\toffs[1] = DLB2_RO_PIPE_GRP_1_SLT_SHFT(queue->sn_slot);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t offs[queue->sn_group],\n+\t\t\t\t DLB2_RO_PIPE_GRP_0_SLT_SHFT_RST);\n+\t\t}\n+\n+\t\tfor (i = 0; i < DLB2_LSP_QID2CQIDIX_NUM; i++) {\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_LSP_QID2CQIDIX(queue_id, i),\n+\t\t\t\t DLB2_LSP_QID2CQIDIX_00_RST);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_LSP_QID2CQIDIX2(queue_id, i),\n+\t\t\t\t DLB2_LSP_QID2CQIDIX2_00_RST);\n+\n+\t\t\tDLB2_CSR_WR(hw,\n+\t\t\t\t DLB2_ATM_QID2CQIDIX(queue_id, i),\n+\t\t\t\t DLB2_ATM_QID2CQIDIX_00_RST);\n+\t\t}\n+\t}\n+}\n+\n+static void dlb2_domain_reset_dir_queue_registers(struct dlb2_hw *hw,\n+\t\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *queue;\n+\tRTE_SET_USED(iter);\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, queue, iter) {\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_DIR_MAX_DEPTH(queue->id.phys_id),\n+\t\t\t DLB2_LSP_QID_DIR_MAX_DEPTH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(queue->id.phys_id),\n+\t\t\t DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(queue->id.phys_id),\n+\t\t\t DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_QID_DIR_DEPTH_THRSH(queue->id.phys_id),\n+\t\t\t DLB2_LSP_QID_DIR_DEPTH_THRSH_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_DIR_QID_ITS(queue->id.phys_id),\n+\t\t\t DLB2_SYS_DIR_QID_ITS_RST);\n+\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_SYS_DIR_QID_V(queue->id.phys_id),\n+\t\t\t DLB2_SYS_DIR_QID_V_RST);\n+\t}\n+}\n+\n+static void dlb2_domain_reset_registers(struct dlb2_hw *hw,\n+\t\t\t\t\tstruct dlb2_hw_domain *domain)\n+{\n+\tdlb2_domain_reset_ldb_port_registers(hw, domain);\n+\n+\tdlb2_domain_reset_dir_port_registers(hw, domain);\n+\n+\tdlb2_domain_reset_ldb_queue_registers(hw, domain);\n+\n+\tdlb2_domain_reset_dir_queue_registers(hw, domain);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id),\n+\t\t DLB2_CHP_CFG_LDB_VAS_CRD_RST);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id),\n+\t\t DLB2_CHP_CFG_DIR_VAS_CRD_RST);\n+}\n+\n+static int dlb2_domain_reset_software_state(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_dir_pq_pair *tmp_dir_port;\n+\tstruct dlb2_ldb_queue *tmp_ldb_queue;\n+\tstruct dlb2_ldb_port *tmp_ldb_port;\n+\tstruct dlb2_list_entry *iter1;\n+\tstruct dlb2_list_entry *iter2;\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_dir_pq_pair *dir_port;\n+\tstruct dlb2_ldb_queue *ldb_queue;\n+\tstruct dlb2_ldb_port *ldb_port;\n+\tstruct dlb2_list_head *list;\n+\tint ret, i;\n+\tRTE_SET_USED(tmp_dir_port);\n+\tRTE_SET_USED(tmp_ldb_queue);\n+\tRTE_SET_USED(tmp_ldb_port);\n+\tRTE_SET_USED(iter1);\n+\tRTE_SET_USED(iter2);\n+\n+\trsrcs = domain->parent_func;\n+\n+\t/* Move the domain's ldb queues to the function's avail list */\n+\tlist = &domain->used_ldb_queues;\n+\tDLB2_DOM_LIST_FOR_SAFE(*list, ldb_queue, tmp_ldb_queue, iter1, iter2) {\n+\t\tif (ldb_queue->sn_cfg_valid) {\n+\t\t\tstruct dlb2_sn_group *grp;\n+\n+\t\t\tgrp = &hw->rsrcs.sn_groups[ldb_queue->sn_group];\n+\n+\t\t\tdlb2_sn_group_free_slot(grp, ldb_queue->sn_slot);\n+\t\t\tldb_queue->sn_cfg_valid = false;\n+\t\t}\n+\n+\t\tldb_queue->owned = false;\n+\t\tldb_queue->num_mappings = 0;\n+\t\tldb_queue->num_pending_additions = 0;\n+\n+\t\tdlb2_list_del(&domain->used_ldb_queues,\n+\t\t\t &ldb_queue->domain_list);\n+\t\tdlb2_list_add(&rsrcs->avail_ldb_queues,\n+\t\t\t &ldb_queue->func_list);\n+\t\trsrcs->num_avail_ldb_queues++;\n+\t}\n+\n+\tlist = &domain->avail_ldb_queues;\n+\tDLB2_DOM_LIST_FOR_SAFE(*list, ldb_queue, tmp_ldb_queue, iter1, iter2) {\n+\t\tldb_queue->owned = false;\n+\n+\t\tdlb2_list_del(&domain->avail_ldb_queues,\n+\t\t\t &ldb_queue->domain_list);\n+\t\tdlb2_list_add(&rsrcs->avail_ldb_queues,\n+\t\t\t &ldb_queue->func_list);\n+\t\trsrcs->num_avail_ldb_queues++;\n+\t}\n+\n+\t/* Move the domain's ldb ports to the function's avail list */\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tlist = &domain->used_ldb_ports[i];\n+\t\tDLB2_DOM_LIST_FOR_SAFE(*list, ldb_port, tmp_ldb_port,\n+\t\t\t\t iter1, iter2) {\n+\t\t\tint j;\n+\n+\t\t\tldb_port->owned = false;\n+\t\t\tldb_port->configured = false;\n+\t\t\tldb_port->num_pending_removals = 0;\n+\t\t\tldb_port->num_mappings = 0;\n+\t\t\tldb_port->init_tkn_cnt = 0;\n+\t\t\tfor (j = 0; j < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; j++)\n+\t\t\t\tldb_port->qid_map[j].state =\n+\t\t\t\t\tDLB2_QUEUE_UNMAPPED;\n+\n+\t\t\tdlb2_list_del(&domain->used_ldb_ports[i],\n+\t\t\t\t &ldb_port->domain_list);\n+\t\t\tdlb2_list_add(&rsrcs->avail_ldb_ports[i],\n+\t\t\t\t &ldb_port->func_list);\n+\t\t\trsrcs->num_avail_ldb_ports[i]++;\n+\t\t}\n+\n+\t\tlist = &domain->avail_ldb_ports[i];\n+\t\tDLB2_DOM_LIST_FOR_SAFE(*list, ldb_port, tmp_ldb_port,\n+\t\t\t\t iter1, iter2) {\n+\t\t\tldb_port->owned = false;\n+\n+\t\t\tdlb2_list_del(&domain->avail_ldb_ports[i],\n+\t\t\t\t &ldb_port->domain_list);\n+\t\t\tdlb2_list_add(&rsrcs->avail_ldb_ports[i],\n+\t\t\t\t &ldb_port->func_list);\n+\t\t\trsrcs->num_avail_ldb_ports[i]++;\n+\t\t}\n+\t}\n+\n+\t/* Move the domain's dir ports to the function's avail list */\n+\tlist = &domain->used_dir_pq_pairs;\n+\tDLB2_DOM_LIST_FOR_SAFE(*list, dir_port, tmp_dir_port, iter1, iter2) {\n+\t\tdir_port->owned = false;\n+\t\tdir_port->port_configured = false;\n+\t\tdir_port->init_tkn_cnt = 0;\n+\n+\t\tdlb2_list_del(&domain->used_dir_pq_pairs,\n+\t\t\t &dir_port->domain_list);\n+\n+\t\tdlb2_list_add(&rsrcs->avail_dir_pq_pairs,\n+\t\t\t &dir_port->func_list);\n+\t\trsrcs->num_avail_dir_pq_pairs++;\n+\t}\n+\n+\tlist = &domain->avail_dir_pq_pairs;\n+\tDLB2_DOM_LIST_FOR_SAFE(*list, dir_port, tmp_dir_port, iter1, iter2) {\n+\t\tdir_port->owned = false;\n+\n+\t\tdlb2_list_del(&domain->avail_dir_pq_pairs,\n+\t\t\t &dir_port->domain_list);\n+\n+\t\tdlb2_list_add(&rsrcs->avail_dir_pq_pairs,\n+\t\t\t &dir_port->func_list);\n+\t\trsrcs->num_avail_dir_pq_pairs++;\n+\t}\n+\n+\t/* Return hist list entries to the function */\n+\tret = dlb2_bitmap_set_range(rsrcs->avail_hist_list_entries,\n+\t\t\t\t domain->hist_list_entry_base,\n+\t\t\t\t domain->total_hist_list_entries);\n+\tif (ret) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: domain hist list base doesn't match the function's bitmap.\\n\",\n+\t\t\t __func__);\n+\t\treturn ret;\n+\t}\n+\n+\tdomain->total_hist_list_entries = 0;\n+\tdomain->avail_hist_list_entries = 0;\n+\tdomain->hist_list_entry_base = 0;\n+\tdomain->hist_list_entry_offset = 0;\n+\n+\trsrcs->num_avail_qed_entries += domain->num_ldb_credits;\n+\tdomain->num_ldb_credits = 0;\n+\n+\trsrcs->num_avail_dqed_entries += domain->num_dir_credits;\n+\tdomain->num_dir_credits = 0;\n+\n+\trsrcs->num_avail_aqed_entries += domain->num_avail_aqed_entries;\n+\trsrcs->num_avail_aqed_entries += domain->num_used_aqed_entries;\n+\tdomain->num_avail_aqed_entries = 0;\n+\tdomain->num_used_aqed_entries = 0;\n+\n+\tdomain->num_pending_removals = 0;\n+\tdomain->num_pending_additions = 0;\n+\tdomain->configured = false;\n+\tdomain->started = false;\n+\n+\t/*\n+\t * Move the domain out of the used_domains list and back to the\n+\t * function's avail_domains list.\n+\t */\n+\tdlb2_list_del(&rsrcs->used_domains, &domain->func_list);\n+\tdlb2_list_add(&rsrcs->avail_domains, &domain->func_list);\n+\trsrcs->num_avail_domains++;\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_domain_drain_unmapped_queue(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t\t struct dlb2_ldb_queue *queue)\n+{\n+\tstruct dlb2_ldb_port *port;\n+\tint ret, i;\n+\n+\t/* If a domain has LDB queues, it must have LDB ports */\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tif (!dlb2_list_empty(&domain->used_ldb_ports[i]))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == DLB2_NUM_COS_DOMAINS) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s()] Internal error: No configured LDB ports\\n\",\n+\t\t\t __func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tport = DLB2_DOM_LIST_HEAD(domain->used_ldb_ports[i], typeof(*port));\n+\n+\t/* If necessary, free up a QID slot in this CQ */\n+\tif (port->num_mappings == DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n+\t\tstruct dlb2_ldb_queue *mapped_queue;\n+\n+\t\tmapped_queue = &hw->rsrcs.ldb_queues[port->qid_map[0].qid];\n+\n+\t\tret = dlb2_ldb_port_unmap_qid(hw, port, mapped_queue);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = dlb2_ldb_port_map_qid_dynamic(hw, port, queue, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn dlb2_domain_drain_mapped_queues(hw, domain);\n+}\n+\n+static int dlb2_domain_drain_unmapped_queues(struct dlb2_hw *hw,\n+\t\t\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_ldb_queue *queue;\n+\tint ret;\n+\tRTE_SET_USED(iter);\n+\n+\t/* If the domain hasn't been started, there's no traffic to drain */\n+\tif (!domain->started)\n+\t\treturn 0;\n+\n+\t/*\n+\t * Pre-condition: the unattached queue must not have any outstanding\n+\t * completions. This is ensured by calling dlb2_domain_drain_ldb_cqs()\n+\t * prior to this in dlb2_domain_drain_mapped_queues().\n+\t */\n+\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter) {\n+\t\tif (queue->num_mappings != 0 ||\n+\t\t dlb2_ldb_queue_is_empty(hw, queue))\n+\t\t\tcontinue;\n+\n+\t\tret = dlb2_domain_drain_unmapped_queue(hw, domain, queue);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_reset_domain() - Reset a DLB scheduling domain and its associated\n+ *\thardware resources.\n+ * @hw:\tContains the current state of the DLB2 hardware.\n+ * @domain_id: Domain ID\n+ * @vdev_req: Request came from a virtual device.\n+ * @vdev_id: If vdev_req is true, this contains the virtual device's ID.\n+ *\n+ * Note: User software *must* stop sending to this domain's producer ports\n+ * before invoking this function, otherwise undefined behavior will result.\n+ *\n+ * Return: returns < 0 on error, 0 otherwise.\n+ */\n+int dlb2_reset_domain(struct dlb2_hw *hw,\n+\t\t u32 domain_id,\n+\t\t bool vdev_req,\n+\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tint ret;\n+\n+\tdlb2_log_reset_domain(hw, domain_id, vdev_req, vdev_id);\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n+\n+\tif (!domain || !domain->configured)\n+\t\treturn -EINVAL;\n+\n+\t/* Disable VPPs */\n+\tif (vdev_req) {\n+\t\tdlb2_domain_disable_dir_vpps(hw, domain, vdev_id);\n+\n+\t\tdlb2_domain_disable_ldb_vpps(hw, domain, vdev_id);\n+\t}\n+\n+\t/* Disable CQ interrupts */\n+\tdlb2_domain_disable_dir_port_interrupts(hw, domain);\n+\n+\tdlb2_domain_disable_ldb_port_interrupts(hw, domain);\n+\n+\t/*\n+\t * For each queue owned by this domain, disable its write permissions to\n+\t * cause any traffic sent to it to be dropped. Well-behaved software\n+\t * should not be sending QEs at this point.\n+\t */\n+\tdlb2_domain_disable_dir_queue_write_perms(hw, domain);\n+\n+\tdlb2_domain_disable_ldb_queue_write_perms(hw, domain);\n+\n+\t/* Turn off completion tracking on all the domain's PPs. */\n+\tdlb2_domain_disable_ldb_seq_checks(hw, domain);\n+\n+\t/*\n+\t * Disable the LDB CQs and drain them in order to complete the map and\n+\t * unmap procedures, which require zero CQ inflights and zero QID\n+\t * inflights respectively.\n+\t */\n+\tdlb2_domain_disable_ldb_cqs(hw, domain);\n+\n+\tret = dlb2_domain_drain_ldb_cqs(hw, domain, false);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_domain_wait_for_ldb_cqs_to_empty(hw, domain);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_domain_finish_unmap_qid_procedures(hw, domain);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_domain_finish_map_qid_procedures(hw, domain);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* Re-enable the CQs in order to drain the mapped queues. */\n+\tdlb2_domain_enable_ldb_cqs(hw, domain);\n+\n+\tret = dlb2_domain_drain_mapped_queues(hw, domain);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = dlb2_domain_drain_unmapped_queues(hw, domain);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* Done draining LDB QEs, so disable the CQs. */\n+\tdlb2_domain_disable_ldb_cqs(hw, domain);\n+\n+\tdlb2_domain_drain_dir_queues(hw, domain);\n+\n+\t/* Done draining DIR QEs, so disable the CQs. */\n+\tdlb2_domain_disable_dir_cqs(hw, domain);\n+\n+\t/* Disable PPs */\n+\tdlb2_domain_disable_dir_producer_ports(hw, domain);\n+\n+\tdlb2_domain_disable_ldb_producer_ports(hw, domain);\n+\n+\tret = dlb2_domain_verify_reset_success(hw, domain);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Reset the QID and port state. */\n+\tdlb2_domain_reset_registers(hw, domain);\n+\n+\t/* Hardware reset complete. Reset the domain's software state */\n+\tret = dlb2_domain_reset_software_state(hw, domain);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw)\n+{\n+\tint i, num = 0;\n+\n+\t/* Finish queue unmap jobs for any domain that needs it */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n+\n+\t\tnum += dlb2_domain_finish_unmap_qid_procedures(hw, domain);\n+\t}\n+\n+\treturn num;\n+}\n+\n+unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n+{\n+\tint i, num = 0;\n+\n+\t/* Finish queue map jobs for any domain that needs it */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n+\n+\t\tnum += dlb2_domain_finish_map_qid_procedures(hw, domain);\n+\t}\n+\n+\treturn num;\n+}\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 1c275ff..ca1ad69 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -618,3 +618,17 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n /****** Device configuration ******/\n /**********************************/\n \n+int\n+dlb2_pf_create_sched_domain(struct dlb2_hw *hw,\n+\t\t\t struct dlb2_create_sched_domain_args *args,\n+\t\t\t struct dlb2_cmd_response *resp)\n+{\n+\treturn dlb2_hw_create_sched_domain(hw, args, resp, NOT_VF_REQ,\n+\t\t\t\t\t PF_ID_ZERO);\n+}\n+\n+int\n+dlb2_pf_reset_domain(struct dlb2_hw *hw, u32 id)\n+{\n+\treturn dlb2_reset_domain(hw, id, NOT_VF_REQ, PF_ID_ZERO);\n+}\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 8c5ec20..21f28a4 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -114,16 +114,60 @@ dlb2_pf_get_cq_poll_mode(struct dlb2_hw_dev *handle,\n \treturn 0;\n }\n \n+static int\n+dlb2_pf_sched_domain_create(struct dlb2_hw_dev *handle,\n+\t\t\t struct dlb2_create_sched_domain_args *arg)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\tstruct dlb2_cmd_response response = {0};\n+\tint ret;\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Entering %s()\\n\", __func__);\n+\n+\tif (dlb2_dev->domain_reset_failed) {\n+\t\tresponse.status = DLB2_ST_DOMAIN_RESET_FAILED;\n+\t\tret = -EINVAL;\n+\t\tgoto done;\n+\t}\n+\n+\tret = dlb2_pf_create_sched_domain(&dlb2_dev->hw, arg, &response);\n+\tif (ret)\n+\t\tgoto done;\n+\n+done:\n+\n+\targ->response = response;\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Exiting %s() with ret=%d\\n\",\n+\t\t __func__, ret);\n+\n+\treturn ret;\n+}\n+\n+static void\n+dlb2_pf_domain_reset(struct dlb2_eventdev *dlb2)\n+{\n+\tstruct dlb2_dev *dlb2_dev;\n+\tint ret;\n+\n+\tdlb2_dev = (struct dlb2_dev *)dlb2->qm_instance.pf_dev;\n+\tret = dlb2_pf_reset_domain(&dlb2_dev->hw, dlb2->qm_instance.domain_id);\n+\tif (ret)\n+\t\tDLB2_LOG_ERR(\"dlb2_pf_reset_domain err %d\", ret);\n+}\n+\n static void\n dlb2_pf_iface_fn_ptrs_init(void)\n {\n \n \tdlb2_iface_low_level_io_init = dlb2_pf_low_level_io_init;\n \tdlb2_iface_open = dlb2_pf_open;\n+\tdlb2_iface_domain_reset = dlb2_pf_domain_reset;\n \tdlb2_iface_get_device_version = dlb2_pf_get_device_version;\n \tdlb2_iface_hardware_init = dlb2_pf_hardware_init;\n \tdlb2_iface_get_num_resources = dlb2_pf_get_num_resources;\n \tdlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;\n+\tdlb2_iface_sched_domain_create = dlb2_pf_sched_domain_create;\n }\n \n /* PCI DEV HOOKS */\n", "prefixes": [ "08/22" ] }