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GET /api/patches/77511/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 77511,
    "url": "http://patches.dpdk.org/api/patches/77511/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-6-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599855987-25976-6-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599855987-25976-6-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2020-09-11T20:26:10",
    "name": "[05/22] event/dlb2: add inline functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7a91b2e930ec03de6e5c8f7f8478f4a5353e4255",
    "submitter": {
        "id": 826,
        "url": "http://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599855987-25976-6-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 12164,
            "url": "http://patches.dpdk.org/api/series/12164/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12164",
            "date": "2020-09-11T20:26:05",
            "name": "Add DLB2 PMD",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/12164/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77511/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/77511/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F6AEA04C1;\n\tFri, 11 Sep 2020 22:30:49 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 689921C1C2;\n\tFri, 11 Sep 2020 22:30:23 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id 72A421C194\n for <dev@dpdk.org>; Fri, 11 Sep 2020 22:29:58 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 13:29:54 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga005.jf.intel.com with ESMTP; 11 Sep 2020 13:29:54 -0700"
        ],
        "IronPort-SDR": [
            "\n h/Lz9L1WoNCEyC67q+iZDgmDvuVE7fiQphl9+ZRccF/nUQpklv/qqLA7ffOsZk55pO7vs24G40\n SX+C4rYEOgCQ==",
            "\n nvZMDRLDYia7eRm4TtsY0+U3VjRoLcm/SF/kKNSEKTkKVw0Ds4gCmG1l2nv/t/ehrvuEHmUxBU\n s6QZsJdlDM5A=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9741\"; a=\"156244345\"",
            "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"156244345\"",
            "E=Sophos;i=\"5.76,417,1592895600\"; d=\"scan'208\";a=\"481453495\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com",
        "Date": "Fri, 11 Sep 2020 15:26:10 -0500",
        "Message-Id": "<1599855987-25976-6-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 05/22] event/dlb2: add inline functions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add miscellaneous inline functions that may be called\nfrom multiple files.  These functions include inline\nassembly of new x86 instructions, such as movdir64b,\nsince they are not available as builtin functions in\nthe minimum supported GCC version.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2_inline_fns.h | 85 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 85 insertions(+)\n create mode 100644 drivers/event/dlb2/dlb2_inline_fns.h",
    "diff": "diff --git a/drivers/event/dlb2/dlb2_inline_fns.h b/drivers/event/dlb2/dlb2_inline_fns.h\nnew file mode 100644\nindex 0000000..f2f0935\n--- /dev/null\n+++ b/drivers/event/dlb2/dlb2_inline_fns.h\n@@ -0,0 +1,85 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef _DLB2_INLINE_FNS_H_\n+#define _DLB2_INLINE_FNS_H_\n+\n+/* Inline functions required in more than one source file.\n+ */\n+\n+static inline struct dlb2_eventdev *\n+dlb2_pmd_priv(const struct rte_eventdev *eventdev)\n+{\n+\treturn eventdev->data->dev_private;\n+}\n+\n+static inline void\n+dlb2_umonitor(volatile void *addr)\n+{\n+\t/* TODO: Change to proper assembly when compiler support available */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7\\t\\n\"\n+\t\t\t:\n+\t\t\t: \"D\" (addr));\n+}\n+\n+static inline void\n+dlb2_umwait(int state, uint64_t timeout)\n+{\n+\tuint32_t eax = timeout & UINT32_MAX;\n+\tuint32_t edx = timeout >> 32;\n+\n+\t/* TODO: Change to proper assembly when compiler support available */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7\\t\\n\"\n+\t\t\t:\n+\t\t\t: \"D\" (state),  \"a\" (eax), \"d\" (edx));\n+}\n+\n+static inline void\n+dlb2_movntdq(void *qe4, void *pp_addr)\n+{\n+\t/* Move entire 64B cache line of QEs, 128 bits (16B) at a time. */\n+\tlong long *_qe  = (long long *)qe4;\n+\t__v2di src_data0 = (__v2di){_qe[0], _qe[1]};\n+\t__v2di src_data1 = (__v2di){_qe[2], _qe[3]};\n+\t__v2di src_data2 = (__v2di){_qe[4], _qe[5]};\n+\t__v2di src_data3 = (__v2di){_qe[6], _qe[7]};\n+\n+\t__builtin_ia32_movntdq((__v2di *)pp_addr + 0, (__v2di)src_data0);\n+\trte_wmb();\n+\t__builtin_ia32_movntdq((__v2di *)pp_addr + 1, (__v2di)src_data1);\n+\trte_wmb();\n+\t__builtin_ia32_movntdq((__v2di *)pp_addr + 2, (__v2di)src_data2);\n+\trte_wmb();\n+\t__builtin_ia32_movntdq((__v2di *)pp_addr + 3, (__v2di)src_data3);\n+\trte_wmb();\n+}\n+\n+static inline void\n+dlb2_movntdq_single(void *qe4, void *pp_addr)\n+{\n+\tlong long *_qe  = (long long *)qe4;\n+\t__v2di src_data0 = (__v2di){_qe[0], _qe[1]};\n+\n+\t__builtin_ia32_movntdq((__v2di *)pp_addr, (__v2di)src_data0);\n+}\n+\n+static inline void\n+dlb2_cldemote(void *addr)\n+{\n+\t/* Load addr into RSI, then demote the cache line of the address\n+\t * contained in that register.\n+\t */\n+\tasm volatile(\".byte 0x0f, 0x1c, 0x06\" :: \"S\" (addr));\n+}\n+\n+static inline void\n+dlb2_movdir64b(void *qe4, void *pp_addr)\n+{\n+\t/* TODO: Change to proper assembly when compiler support available */\n+\tasm volatile(\".byte 0x66, 0x0f, 0x38, 0xf8, 0x02\"\n+\t\t     :\n+\t\t     : \"a\" (pp_addr), \"d\" (qe4));\n+}\n+\n+#endif /* _DLB2_INLINE_FNS_H_ */\n",
    "prefixes": [
        "05/22"
    ]
}