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{
    "id": 77490,
    "url": "http://patches.dpdk.org/api/patches/77490/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599851920-16802-7-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599851920-16802-7-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599851920-16802-7-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2020-09-11T19:18:24",
    "name": "[v4,06/22] event/dlb: add probe",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "f69c8c25d3a36a54e1e405619f9bde19e1318066",
    "submitter": {
        "id": 826,
        "url": "http://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599851920-16802-7-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 12163,
            "url": "http://patches.dpdk.org/api/series/12163/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12163",
            "date": "2020-09-11T19:18:18",
            "name": "Add DLB PMD",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/12163/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77490/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/77490/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 051FFA04C1;\n\tFri, 11 Sep 2020 21:23:10 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 418261C1BD;\n\tFri, 11 Sep 2020 21:22:17 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id E5BA11C12B\n for <dev@dpdk.org>; Fri, 11 Sep 2020 21:22:07 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 12:22:07 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 11 Sep 2020 12:22:06 -0700"
        ],
        "IronPort-SDR": [
            "\n cdS9eATiRefvhL2vygmoHq7jDt0dDqQ67dSFeFA2vFSm84XXgTuR0TmwPfdyoECmv4TCi1M3Kr\n 2cmb8/iLLGzQ==",
            "\n kJYi21dbmESh6ZmNuMsdopTRXNaG0jJSEd5OUZkk2YdiIN7/KOCQG3eQLjhfzfJGTRnk4t+4LV\n jdn6vlxrxR1w=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9741\"; a=\"138352258\"",
            "E=Sophos;i=\"5.76,416,1592895600\"; d=\"scan'208\";a=\"138352258\"",
            "E=Sophos;i=\"5.76,416,1592895600\"; d=\"scan'208\";a=\"506375656\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "Anatoly Burakov <anatoly.burakov@intel.com>",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com",
        "Date": "Fri, 11 Sep 2020 14:18:24 -0500",
        "Message-Id": "<1599851920-16802-7-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1599851920-16802-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<1599851920-16802-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4 06/22] event/dlb: add probe",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The DLB hardware is a PCI device. This commit adds\nsupport for probe and other initialization.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb/dlb.c                      |  493 ++++++\n drivers/event/dlb/dlb_iface.c                |   41 +\n drivers/event/dlb/dlb_iface.h                |   27 +\n drivers/event/dlb/dlb_priv.h                 |   20 +-\n drivers/event/dlb/meson.build                |    6 +-\n drivers/event/dlb/pf/base/dlb_hw_types.h     |  334 ++++\n drivers/event/dlb/pf/base/dlb_osdep.h        |  326 ++++\n drivers/event/dlb/pf/base/dlb_osdep_bitmap.h |  441 +++++\n drivers/event/dlb/pf/base/dlb_osdep_list.h   |  131 ++\n drivers/event/dlb/pf/base/dlb_osdep_types.h  |   31 +\n drivers/event/dlb/pf/base/dlb_regs.h         | 2368 ++++++++++++++++++++++++++\n drivers/event/dlb/pf/base/dlb_resource.c     |  302 ++++\n drivers/event/dlb/pf/base/dlb_resource.h     |  876 ++++++++++\n drivers/event/dlb/pf/dlb_main.c              |  591 +++++++\n drivers/event/dlb/pf/dlb_main.h              |   52 +\n drivers/event/dlb/pf/dlb_pf.c                |  232 +++\n 16 files changed, 6254 insertions(+), 17 deletions(-)\n create mode 100644 drivers/event/dlb/dlb.c\n create mode 100644 drivers/event/dlb/dlb_iface.c\n create mode 100644 drivers/event/dlb/dlb_iface.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_hw_types.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_osdep.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_osdep_bitmap.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_osdep_list.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_osdep_types.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_regs.h\n create mode 100644 drivers/event/dlb/pf/base/dlb_resource.c\n create mode 100644 drivers/event/dlb/pf/base/dlb_resource.h\n create mode 100644 drivers/event/dlb/pf/dlb_main.c\n create mode 100644 drivers/event/dlb/pf/dlb_main.h\n create mode 100644 drivers/event/dlb/pf/dlb_pf.c",
    "diff": "diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nnew file mode 100644\nindex 0000000..e2acb61\n--- /dev/null\n+++ b/drivers/event/dlb/dlb.c\n@@ -0,0 +1,493 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <assert.h>\n+#include <errno.h>\n+#include <nmmintrin.h>\n+#include <pthread.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <sys/fcntl.h>\n+#include <sys/mman.h>\n+#include <unistd.h>\n+\n+#include <rte_common.h>\n+#include <rte_config.h>\n+#include <rte_cycles.h>\n+#include <rte_debug.h>\n+#include <rte_dev.h>\n+#include <rte_errno.h>\n+#include <rte_io.h>\n+#include <rte_kvargs.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+#include <rte_mbuf.h>\n+#include <rte_prefetch.h>\n+#include <rte_ring.h>\n+#include <rte_string_fns.h>\n+\n+#include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+\n+#include \"dlb_priv.h\"\n+#include \"dlb_iface.h\"\n+#include \"dlb_inline_fns.h\"\n+\n+/*\n+ * Resources exposed to eventdev.\n+ */\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)\n+#error \"RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member max_event_queues\"\n+#endif\n+static struct rte_event_dev_info evdev_dlb_default_info = {\n+\t.driver_name = \"\", /* probe will set */\n+\t.min_dequeue_timeout_ns = DLB_MIN_DEQUEUE_TIMEOUT_NS,\n+\t.max_dequeue_timeout_ns = DLB_MAX_DEQUEUE_TIMEOUT_NS,\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB_MAX_NUM_LDB_QUEUES)\n+\t.max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,\n+#else\n+\t.max_event_queues = DLB_MAX_NUM_LDB_QUEUES,\n+#endif\n+\t.max_event_queue_flows = DLB_MAX_NUM_FLOWS,\n+\t.max_event_queue_priority_levels = DLB_QID_PRIORITIES,\n+\t.max_event_priority_levels = DLB_QID_PRIORITIES,\n+\t.max_event_ports = DLB_MAX_NUM_LDB_PORTS,\n+\t.max_event_port_dequeue_depth = DLB_MAX_CQ_DEPTH,\n+\t.max_event_port_enqueue_depth = DLB_MAX_ENQUEUE_DEPTH,\n+\t.max_event_port_links = DLB_MAX_NUM_QIDS_PER_LDB_CQ,\n+\t.max_num_events = DLB_MAX_NUM_LDB_CREDITS,\n+\t.max_single_link_event_port_queue_pairs = DLB_MAX_NUM_DIR_PORTS,\n+\t.event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |\n+\t\t\t  RTE_EVENT_DEV_CAP_EVENT_QOS |\n+\t\t\t  RTE_EVENT_DEV_CAP_BURST_MODE |\n+\t\t\t  RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |\n+\t\t\t  RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |\n+\t\t\t  RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),\n+};\n+\n+struct process_local_port_data\n+dlb_port[DLB_MAX_NUM_PORTS][NUM_DLB_PORT_TYPES];\n+\n+static int\n+dlb_hw_query_resources(struct dlb_eventdev *dlb)\n+{\n+\tstruct dlb_hw_dev *handle = &dlb->qm_instance;\n+\tstruct dlb_hw_resource_info *dlb_info = &handle->info;\n+\tint ret;\n+\n+\tret = dlb_iface_get_num_resources(handle,\n+\t\t\t\t\t  &dlb->hw_rsrc_query_results);\n+\tif (ret) {\n+\t\tDLB_LOG_ERR(\"ioctl get dlb num resources, err=%d\\n\",\n+\t\t\t    ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Complete filling in device resource info returned to evdev app,\n+\t * overriding any default values.\n+\t * The capabilities (CAPs) were set at compile time.\n+\t */\n+\n+\tevdev_dlb_default_info.max_event_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues;\n+\n+\tevdev_dlb_default_info.max_event_ports =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_ports;\n+\n+\tevdev_dlb_default_info.max_num_events =\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_ldb_credits;\n+\n+\t/* Save off values used when creating the scheduling domain. */\n+\n+\thandle->info.num_sched_domains =\n+\t\tdlb->hw_rsrc_query_results.num_sched_domains;\n+\n+\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_ldb_credits;\n+\n+\thandle->info.hw_rsrc_max.num_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues +\n+\t\tdlb->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_ports =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_ports;\n+\n+\thandle->info.hw_rsrc_max.num_dir_ports =\n+\t\tdlb->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.reorder_window_size =\n+\t\tdlb->hw_rsrc_query_results.num_hist_list_entries;\n+\n+\trte_memcpy(dlb_info, &handle->info.hw_rsrc_max, sizeof(*dlb_info));\n+\n+\treturn 0;\n+}\n+\n+/* Wrapper for string to int conversion. Substituted for atoi(...), which is\n+ * unsafe.\n+ */\n+#define RTE_BASE_10 10\n+\n+static int\n+dlb_string_to_int(int *result, const char *str)\n+{\n+\tlong ret;\n+\n+\tif (str == NULL || result == NULL)\n+\t\treturn -EINVAL;\n+\n+\terrno = 0;\n+\tret = strtol(str, NULL, RTE_BASE_10);\n+\tif (errno)\n+\t\treturn -errno;\n+\n+\t/* long int and int may be different width for some architectures */\n+\tif (ret < INT_MIN || ret > INT_MAX)\n+\t\treturn -EINVAL;\n+\n+\t*result = ret;\n+\treturn 0;\n+}\n+\n+static int\n+set_numa_node(const char *key __rte_unused, const char *value, void *opaque)\n+{\n+\tint *socket_id = opaque;\n+\tint ret;\n+\n+\tret = dlb_string_to_int(socket_id, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*socket_id > RTE_MAX_NUMA_NODES)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_max_num_events(const char *key __rte_unused,\n+\t\t   const char *value,\n+\t\t   void *opaque)\n+{\n+\tint *max_num_events = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb_string_to_int(max_num_events, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*max_num_events < 0 || *max_num_events > DLB_MAX_NUM_LDB_CREDITS) {\n+\t\tDLB_LOG_ERR(\"dlb: max_num_events must be between 0 and %d\\n\",\n+\t\t\t    DLB_MAX_NUM_LDB_CREDITS);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_num_dir_credits(const char *key __rte_unused,\n+\t\t    const char *value,\n+\t\t    void *opaque)\n+{\n+\tint *num_dir_credits = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb_string_to_int(num_dir_credits, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*num_dir_credits < 0 ||\n+\t    *num_dir_credits > DLB_MAX_NUM_DIR_CREDITS) {\n+\t\tDLB_LOG_ERR(\"dlb: num_dir_credits must be between 0 and %d\\n\",\n+\t\t\t    DLB_MAX_NUM_DIR_CREDITS);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_dev_id(const char *key __rte_unused,\n+\t   const char *value,\n+\t   void *opaque)\n+{\n+\tint *dev_id = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb_string_to_int(dev_id, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_defer_sched(const char *key __rte_unused,\n+\t\tconst char *value,\n+\t\tvoid *opaque)\n+{\n+\tint *defer_sched = opaque;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (strncmp(value, \"on\", 2) != 0) {\n+\t\tDLB_LOG_ERR(\"Invalid defer_sched argument \\\"%s\\\" (expected \\\"on\\\")\\n\",\n+\t\t\t    value);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*defer_sched = 1;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_num_atm_inflights(const char *key __rte_unused,\n+\t\t      const char *value,\n+\t\t      void *opaque)\n+{\n+\tint *num_atm_inflights = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb_string_to_int(num_atm_inflights, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*num_atm_inflights < 0 ||\n+\t    *num_atm_inflights > DLB_MAX_NUM_ATM_INFLIGHTS) {\n+\t\tDLB_LOG_ERR(\"dlb: atm_inflights must be between 0 and %d\\n\",\n+\t\t\t    DLB_MAX_NUM_ATM_INFLIGHTS);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+dlb_entry_points_init(struct rte_eventdev *dev)\n+{\n+\tstatic struct rte_eventdev_ops dlb_eventdev_entry_ops = {\n+\t};\n+\n+\t/* Expose PMD's eventdev interface */\n+\tdev->dev_ops = &dlb_eventdev_entry_ops;\n+\n+}\n+\n+int\n+dlb_primary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t   const char *name,\n+\t\t\t   struct dlb_devargs *dlb_args)\n+{\n+\tstruct dlb_eventdev *dlb;\n+\tint err, i;\n+\n+\tdlb = dev->data->dev_private;\n+\n+\tdlb->event_dev = dev; /* backlink */\n+\n+\tevdev_dlb_default_info.driver_name = name;\n+\n+\tdlb->max_num_events_override = dlb_args->max_num_events;\n+\tdlb->num_dir_credits_override = dlb_args->num_dir_credits_override;\n+\tdlb->qm_instance.device_path_id = dlb_args->dev_id;\n+\tdlb->defer_sched = dlb_args->defer_sched;\n+\tdlb->num_atm_inflights_per_queue = dlb_args->num_atm_inflights;\n+\n+\t/* Open the interface.\n+\t * For vdev mode, this means open the dlb kernel module.\n+\t */\n+\terr = dlb_iface_open(&dlb->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t    err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_iface_get_device_version(&dlb->qm_instance, &dlb->revision);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"dlb: failed to get the device version, err=%d\\n\",\n+\t\t\t    err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_hw_query_resources(dlb);\n+\tif (err) {\n+\t\tDLB_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t    err, name);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_iface_get_cq_poll_mode(&dlb->qm_instance, &dlb->poll_mode);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"dlb: failed to get the poll mode, err=%d\\n\",\n+\t\t\t    err);\n+\t\treturn err;\n+\t}\n+\n+\t/* Initialize each port's token pop mode */\n+\tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++)\n+\t\tdlb->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;\n+\n+\trte_spinlock_init(&dlb->qm_instance.resource_lock);\n+\n+\tdlb_iface_low_level_io_init(dlb);\n+\n+\tdlb_entry_points_init(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+dlb_secondary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t     const char *name)\n+{\n+\tstruct dlb_eventdev *dlb;\n+\tint err;\n+\n+\tdlb = dev->data->dev_private;\n+\n+\tevdev_dlb_default_info.driver_name = name;\n+\n+\terr = dlb_iface_open(&dlb->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t    err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_hw_query_resources(dlb);\n+\tif (err) {\n+\t\tDLB_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t    err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb_iface_low_level_io_init(dlb);\n+\n+\tdlb_entry_points_init(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+dlb_parse_params(const char *params,\n+\t\t const char *name,\n+\t\t struct dlb_devargs *dlb_args)\n+{\n+\tint ret = 0;\n+\tstatic const char * const args[] = { NUMA_NODE_ARG,\n+\t\t\t\t\t     DLB_MAX_NUM_EVENTS,\n+\t\t\t\t\t     DLB_NUM_DIR_CREDITS,\n+\t\t\t\t\t     DEV_ID_ARG,\n+\t\t\t\t\t     DLB_DEFER_SCHED_ARG,\n+\t\t\t\t\t     DLB_NUM_ATM_INFLIGHTS_ARG,\n+\t\t\t\t\t     NULL };\n+\n+\tif (params && params[0] != '\\0') {\n+\t\tstruct rte_kvargs *kvlist = rte_kvargs_parse(params, args);\n+\n+\t\tif (!kvlist) {\n+\t\t\tDLB_LOG_INFO(\"Ignoring unsupported parameters when creating device '%s'\\n\",\n+\t\t\t\t     name);\n+\t\t} else {\n+\t\t\tint ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,\n+\t\t\t\t\t\t     set_numa_node,\n+\t\t\t\t\t\t     &dlb_args->socket_id);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing numa node parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB_MAX_NUM_EVENTS,\n+\t\t\t\t\t\t set_max_num_events,\n+\t\t\t\t\t\t &dlb_args->max_num_events);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing max_num_events parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\tDLB_NUM_DIR_CREDITS,\n+\t\t\t\t\tset_num_dir_credits,\n+\t\t\t\t\t&dlb_args->num_dir_credits_override);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing num_dir_credits parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DEV_ID_ARG,\n+\t\t\t\t\t\t set_dev_id,\n+\t\t\t\t\t\t &dlb_args->dev_id);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing dev_id parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB_DEFER_SCHED_ARG,\n+\t\t\t\t\t\t set_defer_sched,\n+\t\t\t\t\t\t &dlb_args->defer_sched);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing defer_sched parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\t\t DLB_NUM_ATM_INFLIGHTS_ARG,\n+\t\t\t\t\t\t set_num_atm_inflights,\n+\t\t\t\t\t\t &dlb_args->num_atm_inflights);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB_LOG_ERR(\"%s: Error parsing atm_inflights parameter\",\n+\t\t\t\t\t    name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\trte_kvargs_free(kvlist);\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+RTE_LOG_REGISTER(eventdev_dlb_log_level, pmd.event.dlb, NOTICE);\n+\ndiff --git a/drivers/event/dlb/dlb_iface.c b/drivers/event/dlb/dlb_iface.c\nnew file mode 100644\nindex 0000000..3f17bd1\n--- /dev/null\n+++ b/drivers/event/dlb/dlb_iface.c\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdbool.h>\n+#include <stdint.h>\n+\n+#include <rte_debug.h>\n+#include <rte_bus_pci.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_mbuf.h>\n+#include <rte_ring.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+#include <rte_malloc.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_eventdev.h>\n+\n+#include \"dlb_priv.h\"\n+\n+/* DLB PMD Internal interface function pointers.\n+ * If VDEV (bifurcated PMD),  these will resolve to functions that issue ioctls\n+ * serviced by DLB kernel module.\n+ * If PCI (PF PMD),  these will be implemented locally in user mode.\n+ */\n+\n+void (*dlb_iface_low_level_io_init)(struct dlb_eventdev *dlb);\n+\n+int (*dlb_iface_open)(struct dlb_hw_dev *handle, const char *name);\n+\n+int (*dlb_iface_get_device_version)(struct dlb_hw_dev *handle,\n+\t\t\t\t    uint8_t *revision);\n+\n+int (*dlb_iface_get_num_resources)(struct dlb_hw_dev *handle,\n+\t\t\t\t   struct dlb_get_num_resources_args *rsrcs);\n+\n+int (*dlb_iface_get_cq_poll_mode)(struct dlb_hw_dev *handle,\n+\t\t\t\t  enum dlb_cq_poll_modes *mode);\n+\ndiff --git a/drivers/event/dlb/dlb_iface.h b/drivers/event/dlb/dlb_iface.h\nnew file mode 100644\nindex 0000000..416d1b3\n--- /dev/null\n+++ b/drivers/event/dlb/dlb_iface.h\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef _DLB_IFACE_H\n+#define _DLB_IFACE_H\n+\n+/* DLB PMD Internal interface function pointers.\n+ * If VDEV (bifurcated PMD), these will resolve to functions that issue ioctls\n+ * serviced by DLB kernel module.\n+ * If PCI (PF PMD), these will be implemented locally in user mode.\n+ */\n+\n+extern void (*dlb_iface_low_level_io_init)(struct dlb_eventdev *dlb);\n+\n+extern int (*dlb_iface_open)(struct dlb_hw_dev *handle, const char *name);\n+\n+extern int (*dlb_iface_get_device_version)(struct dlb_hw_dev *handle,\n+\t\t\t\t\t   uint8_t *revision);\n+\n+extern int (*dlb_iface_get_num_resources)(struct dlb_hw_dev *handle,\n+\t\t\t\t   struct dlb_get_num_resources_args *rsrcs);\n+\n+extern int (*dlb_iface_get_cq_poll_mode)(struct dlb_hw_dev *handle,\n+\t\t\t\t\t enum dlb_cq_poll_modes *mode);\n+\n+#endif /* _DLB_IFACE_H */\ndiff --git a/drivers/event/dlb/dlb_priv.h b/drivers/event/dlb/dlb_priv.h\nindex 482c5b2..acb8158 100644\n--- a/drivers/event/dlb/dlb_priv.h\n+++ b/drivers/event/dlb/dlb_priv.h\n@@ -527,18 +527,14 @@ int test_dlb_eventdev(void);\n \n int dlb_primary_eventdev_probe(struct rte_eventdev *dev,\n \t\t\t       const char *name,\n-\t\t\t       struct dlb_devargs *dlb_args,\n-\t\t\t       bool is_vdev);\n+\t\t\t       struct dlb_devargs *dlb_args);\n \n int dlb_secondary_eventdev_probe(struct rte_eventdev *dev,\n-\t\t\t\t const char *name,\n-\t\t\t\t bool is_vdev);\n+\t\t\t\t const char *name);\n+\n uint32_t dlb_get_queue_depth(struct dlb_eventdev *dlb,\n \t\t\t     struct dlb_eventdev_queue *queue);\n \n-int set_numa_node(const char *key __rte_unused, const char *value,\n-\t\t  void *opaque);\n-\n int set_dir_ports(const char *key __rte_unused,\n \t\t  const char *value __rte_unused,\n \t\t  void *opaque __rte_unused);\n@@ -547,20 +543,12 @@ int set_dir_queues(const char *key __rte_unused,\n \t\t   const char *value __rte_unused,\n \t\t   void *opaque __rte_unused);\n \n-int set_max_num_events(const char *key __rte_unused, const char *value,\n-\t\t       void *opaque);\n-\n-int set_num_dir_credits(const char *key __rte_unused, const char *value,\n-\t\t\tvoid *opaque);\n-\n void dlb_drain(struct rte_eventdev *dev);\n \n-void dlb_entry_points_init(struct rte_eventdev *dev);\n-\n int dlb_parse_params(const char *params,\n \t\t     const char *name,\n \t\t     struct dlb_devargs *dlb_args);\n \n-int dlb_string_to_int(int *result, const char *str);\n+void dlb_entry_points_init(struct rte_eventdev *dev);\n \n #endif\t/* _DLB_PRIV_H_ */\ndiff --git a/drivers/event/dlb/meson.build b/drivers/event/dlb/meson.build\nindex 54ba2c8..414b3ed 100644\n--- a/drivers/event/dlb/meson.build\n+++ b/drivers/event/dlb/meson.build\n@@ -1,7 +1,11 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2019-2020 Intel Corporation\n \n-sources = files(\n+sources = files('dlb.c',\n+\t\t'dlb_iface.c',\n+\t\t'pf/dlb_main.c',\n+\t\t'pf/dlb_pf.c',\n+\t\t'pf/base/dlb_resource.c'\n )\n \n deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']\ndiff --git a/drivers/event/dlb/pf/base/dlb_hw_types.h b/drivers/event/dlb/pf/base/dlb_hw_types.h\nnew file mode 100644\nindex 0000000..87b83f8\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_hw_types.h\n@@ -0,0 +1,334 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_HW_TYPES_H\n+#define __DLB_HW_TYPES_H\n+\n+#include \"../../dlb_user.h\"\n+#include \"dlb_osdep_types.h\"\n+#include \"dlb_osdep_list.h\"\n+\n+#define DLB_MAX_NUM_DOMAINS 32\n+#define DLB_MAX_NUM_LDB_QUEUES 128\n+#define DLB_MAX_NUM_LDB_PORTS 64\n+#define DLB_MAX_NUM_DIR_PORTS 128\n+#define DLB_MAX_NUM_LDB_CREDITS 16384\n+#define DLB_MAX_NUM_DIR_CREDITS 4096\n+#define DLB_MAX_NUM_LDB_CREDIT_POOLS 64\n+#define DLB_MAX_NUM_DIR_CREDIT_POOLS 64\n+#define DLB_MAX_NUM_HIST_LIST_ENTRIES 5120\n+#define DLB_MAX_NUM_AQOS_ENTRIES 2048\n+#define DLB_MAX_NUM_TOTAL_OUTSTANDING_COMPLETIONS 4096\n+#define DLB_MAX_NUM_QIDS_PER_LDB_CQ 8\n+#define DLB_MAX_NUM_SEQUENCE_NUMBER_GROUPS 4\n+#define DLB_MAX_NUM_SEQUENCE_NUMBER_MODES 6\n+#define DLB_QID_PRIORITIES 8\n+#define DLB_NUM_ARB_WEIGHTS 8\n+#define DLB_MAX_WEIGHT 255\n+#define DLB_MAX_PORT_CREDIT_QUANTUM 1023\n+#define DLB_MAX_CQ_COMP_CHECK_LOOPS 409600\n+#define DLB_MAX_QID_EMPTY_CHECK_LOOPS (32 * 64 * 1024 * (800 / 30))\n+#define DLB_HZ 800000000\n+\n+/* Used for DLB A-stepping workaround for hardware write buffer lock up issue */\n+#define DLB_A_STEP_MAX_PORTS 128\n+\n+#define DLB_PF_DEV_ID 0x270B\n+\n+/* Interrupt related macros */\n+#define DLB_PF_NUM_NON_CQ_INTERRUPT_VECTORS 8\n+#define DLB_PF_NUM_CQ_INTERRUPT_VECTORS\t 64\n+#define DLB_PF_TOTAL_NUM_INTERRUPT_VECTORS \\\n+\t(DLB_PF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n+\t DLB_PF_NUM_CQ_INTERRUPT_VECTORS)\n+#define DLB_PF_NUM_COMPRESSED_MODE_VECTORS \\\n+\t(DLB_PF_NUM_NON_CQ_INTERRUPT_VECTORS + 1)\n+#define DLB_PF_NUM_PACKED_MODE_VECTORS\t DLB_PF_TOTAL_NUM_INTERRUPT_VECTORS\n+#define DLB_PF_COMPRESSED_MODE_CQ_VECTOR_ID DLB_PF_NUM_NON_CQ_INTERRUPT_VECTORS\n+\n+#define DLB_PF_NUM_ALARM_INTERRUPT_VECTORS 4\n+#define DLB_INT_ALARM 0\n+#define DLB_INT_INGRESS_ERROR 3\n+\n+#define DLB_ALARM_HW_SOURCE_SYS 0\n+#define DLB_ALARM_HW_SOURCE_DLB 1\n+\n+#define DLB_ALARM_HW_UNIT_CHP 1\n+#define DLB_ALARM_HW_UNIT_LSP 3\n+\n+#define DLB_ALARM_HW_CHP_AID_OUT_OF_CREDITS 6\n+#define DLB_ALARM_HW_CHP_AID_ILLEGAL_ENQ 7\n+#define DLB_ALARM_HW_LSP_AID_EXCESS_TOKEN_POPS 15\n+#define DLB_ALARM_SYS_AID_ILLEGAL_HCW 0\n+#define DLB_ALARM_SYS_AID_ILLEGAL_QID 3\n+#define DLB_ALARM_SYS_AID_DISABLED_QID 4\n+#define DLB_ALARM_SYS_AID_ILLEGAL_CQID 6\n+\n+/* Hardware-defined base addresses */\n+#define DLB_LDB_PP_BASE 0x2100000\n+#define DLB_LDB_PP_STRIDE 0x1000\n+#define DLB_LDB_PP_BOUND \\\n+\t(DLB_LDB_PP_BASE + DLB_LDB_PP_STRIDE * DLB_MAX_NUM_LDB_PORTS)\n+#define DLB_DIR_PP_BASE 0x2000000\n+#define DLB_DIR_PP_STRIDE 0x1000\n+#define DLB_DIR_PP_BOUND \\\n+\t(DLB_DIR_PP_BASE + DLB_DIR_PP_STRIDE * DLB_MAX_NUM_DIR_PORTS)\n+\n+struct dlb_freelist {\n+\tu32 base;\n+\tu32 bound;\n+\tu32 offset;\n+};\n+\n+static inline u32 dlb_freelist_count(struct dlb_freelist *list)\n+{\n+\treturn (list->bound - list->base) - list->offset;\n+}\n+\n+struct dlb_hcw {\n+\tu64 data;\n+\t/* Word 3 */\n+\tu16 opaque;\n+\tu8 qid;\n+\tu8 sched_type:2;\n+\tu8 priority:3;\n+\tu8 msg_type:3;\n+\t/* Word 4 */\n+\tu16 lock_id;\n+\tu8 meas_lat:1;\n+\tu8 rsvd1:2;\n+\tu8 no_dec:1;\n+\tu8 cmp_id:4;\n+\tu8 cq_token:1;\n+\tu8 qe_comp:1;\n+\tu8 qe_frag:1;\n+\tu8 qe_valid:1;\n+\tu8 int_arm:1;\n+\tu8 error:1;\n+\tu8 rsvd:2;\n+};\n+\n+struct dlb_ldb_queue {\n+\tstruct dlb_list_entry domain_list;\n+\tstruct dlb_list_entry func_list;\n+\tu32 id;\n+\tu32 domain_id;\n+\tu32 num_qid_inflights;\n+\tstruct dlb_freelist aqed_freelist;\n+\tu8 sn_cfg_valid;\n+\tu32 sn_group;\n+\tu32 sn_slot;\n+\tu32 num_mappings;\n+\tu8 num_pending_additions;\n+\tu8 owned;\n+\tu8 configured;\n+};\n+\n+/* Directed ports and queues are paired by nature, so the driver tracks them\n+ * with a single data structure.\n+ */\n+struct dlb_dir_pq_pair {\n+\tstruct dlb_list_entry domain_list;\n+\tstruct dlb_list_entry func_list;\n+\tu32 id;\n+\tu32 domain_id;\n+\tu8 ldb_pool_used;\n+\tu8 dir_pool_used;\n+\tu8 queue_configured;\n+\tu8 port_configured;\n+\tu8 owned;\n+\tu8 enabled;\n+\tu32 ref_cnt;\n+};\n+\n+enum dlb_qid_map_state {\n+\t/* The slot doesn't contain a valid queue mapping */\n+\tDLB_QUEUE_UNMAPPED,\n+\t/* The slot contains a valid queue mapping */\n+\tDLB_QUEUE_MAPPED,\n+\t/* The driver is mapping a queue into this slot */\n+\tDLB_QUEUE_MAP_IN_PROGRESS,\n+\t/* The driver is unmapping a queue from this slot */\n+\tDLB_QUEUE_UNMAP_IN_PROGRESS,\n+\t/* The driver is unmapping a queue from this slot, and once complete\n+\t * will replace it with another mapping.\n+\t */\n+\tDLB_QUEUE_UNMAP_IN_PROGRESS_PENDING_MAP,\n+};\n+\n+struct dlb_ldb_port_qid_map {\n+\tu16 qid;\n+\tu8 priority;\n+\tu16 pending_qid;\n+\tu8 pending_priority;\n+\tenum dlb_qid_map_state state;\n+};\n+\n+struct dlb_ldb_port {\n+\tstruct dlb_list_entry domain_list;\n+\tstruct dlb_list_entry func_list;\n+\tu32 id;\n+\tu32 domain_id;\n+\tu8 ldb_pool_used;\n+\tu8 dir_pool_used;\n+\tu8 init_tkn_cnt;\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_limit;\n+\t/* The qid_map represents the hardware QID mapping state. */\n+\tstruct dlb_ldb_port_qid_map qid_map[DLB_MAX_NUM_QIDS_PER_LDB_CQ];\n+\tu32 ref_cnt;\n+\tu8 num_pending_removals;\n+\tu8 num_mappings;\n+\tu8 owned;\n+\tu8 enabled;\n+\tu8 configured;\n+};\n+\n+struct dlb_credit_pool {\n+\tstruct dlb_list_entry domain_list;\n+\tstruct dlb_list_entry func_list;\n+\tu32 id;\n+\tu32 domain_id;\n+\tu32 total_credits;\n+\tu32 avail_credits;\n+\tu8 owned;\n+\tu8 configured;\n+};\n+\n+struct dlb_sn_group {\n+\tu32 mode;\n+\tu32 sequence_numbers_per_queue;\n+\tu32 slot_use_bitmap;\n+\tu32 id;\n+};\n+\n+static inline bool dlb_sn_group_full(struct dlb_sn_group *group)\n+{\n+\tu32 mask[6] = {\n+\t\t0xffffffff,  /* 32 SNs per queue */\n+\t\t0x0000ffff,  /* 64 SNs per queue */\n+\t\t0x000000ff,  /* 128 SNs per queue */\n+\t\t0x0000000f,  /* 256 SNs per queue */\n+\t\t0x00000003,  /* 512 SNs per queue */\n+\t\t0x00000001}; /* 1024 SNs per queue */\n+\n+\treturn group->slot_use_bitmap == mask[group->mode];\n+}\n+\n+static inline int dlb_sn_group_alloc_slot(struct dlb_sn_group *group)\n+{\n+\tint bound[6] = {32, 16, 8, 4, 2, 1};\n+\tint i;\n+\n+\tfor (i = 0; i < bound[group->mode]; i++) {\n+\t\tif (!(group->slot_use_bitmap & (1 << i))) {\n+\t\t\tgroup->slot_use_bitmap |= 1 << i;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static inline void dlb_sn_group_free_slot(struct dlb_sn_group *group, int slot)\n+{\n+\tgroup->slot_use_bitmap &= ~(1 << slot);\n+}\n+\n+static inline int dlb_sn_group_used_slots(struct dlb_sn_group *group)\n+{\n+\tint i, cnt = 0;\n+\n+\tfor (i = 0; i < 32; i++)\n+\t\tcnt += !!(group->slot_use_bitmap & (1 << i));\n+\n+\treturn cnt;\n+}\n+\n+struct dlb_domain {\n+\tstruct dlb_function_resources *parent_func;\n+\tstruct dlb_list_entry func_list;\n+\tstruct dlb_list_head used_ldb_queues;\n+\tstruct dlb_list_head used_ldb_ports;\n+\tstruct dlb_list_head used_dir_pq_pairs;\n+\tstruct dlb_list_head used_ldb_credit_pools;\n+\tstruct dlb_list_head used_dir_credit_pools;\n+\tstruct dlb_list_head avail_ldb_queues;\n+\tstruct dlb_list_head avail_ldb_ports;\n+\tstruct dlb_list_head avail_dir_pq_pairs;\n+\tstruct dlb_list_head avail_ldb_credit_pools;\n+\tstruct dlb_list_head avail_dir_credit_pools;\n+\tu32 total_hist_list_entries;\n+\tu32 avail_hist_list_entries;\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_offset;\n+\tstruct dlb_freelist qed_freelist;\n+\tstruct dlb_freelist dqed_freelist;\n+\tstruct dlb_freelist aqed_freelist;\n+\tu32 id;\n+\tint num_pending_removals;\n+\tint num_pending_additions;\n+\tu8 configured;\n+\tu8 started;\n+};\n+\n+struct dlb_bitmap;\n+\n+struct dlb_function_resources {\n+\tu32 num_avail_domains;\n+\tstruct dlb_list_head avail_domains;\n+\tstruct dlb_list_head used_domains;\n+\tu32 num_avail_ldb_queues;\n+\tstruct dlb_list_head avail_ldb_queues;\n+\tu32 num_avail_ldb_ports;\n+\tstruct dlb_list_head avail_ldb_ports;\n+\tu32 num_avail_dir_pq_pairs;\n+\tstruct dlb_list_head avail_dir_pq_pairs;\n+\tstruct dlb_bitmap *avail_hist_list_entries;\n+\tstruct dlb_bitmap *avail_qed_freelist_entries;\n+\tstruct dlb_bitmap *avail_dqed_freelist_entries;\n+\tstruct dlb_bitmap *avail_aqed_freelist_entries;\n+\tu32 num_avail_ldb_credit_pools;\n+\tstruct dlb_list_head avail_ldb_credit_pools;\n+\tu32 num_avail_dir_credit_pools;\n+\tstruct dlb_list_head avail_dir_credit_pools;\n+\tu32 num_enabled_ldb_ports;\n+};\n+\n+/* After initialization, each resource in dlb_hw_resources is located in one of\n+ * the following lists:\n+ * -- The PF's available resources list. These are unconfigured resources owned\n+ *\tby the PF and not allocated to a DLB scheduling domain.\n+ * -- A domain's available resources list. These are domain-owned unconfigured\n+ *\tresources.\n+ * -- A domain's used resources list. These are are domain-owned configured\n+ *\tresources.\n+ *\n+ * A resource moves to a new list when a domain is created or destroyed, or\n+ * when the resource is configured.\n+ */\n+struct dlb_hw_resources {\n+\tstruct dlb_ldb_queue ldb_queues[DLB_MAX_NUM_LDB_QUEUES];\n+\tstruct dlb_ldb_port ldb_ports[DLB_MAX_NUM_LDB_PORTS];\n+\tstruct dlb_dir_pq_pair dir_pq_pairs[DLB_MAX_NUM_DIR_PORTS];\n+\tstruct dlb_credit_pool ldb_credit_pools[DLB_MAX_NUM_LDB_CREDIT_POOLS];\n+\tstruct dlb_credit_pool dir_credit_pools[DLB_MAX_NUM_DIR_CREDIT_POOLS];\n+\tstruct dlb_sn_group sn_groups[DLB_MAX_NUM_SEQUENCE_NUMBER_GROUPS];\n+};\n+\n+struct dlb_hw {\n+\t/* BAR 0 address */\n+\tvoid  *csr_kva;\n+\tunsigned long csr_phys_addr;\n+\t/* BAR 2 address */\n+\tvoid  *func_kva;\n+\tunsigned long func_phys_addr;\n+\n+\t/* Resource tracking */\n+\tstruct dlb_hw_resources rsrcs;\n+\tstruct dlb_function_resources pf;\n+\tstruct dlb_domain domains[DLB_MAX_NUM_DOMAINS];\n+};\n+\n+#endif /* __DLB_HW_TYPES_H */\ndiff --git a/drivers/event/dlb/pf/base/dlb_osdep.h b/drivers/event/dlb/pf/base/dlb_osdep.h\nnew file mode 100644\nindex 0000000..a6eef2f\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_osdep.h\n@@ -0,0 +1,326 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_OSDEP_H__\n+#define __DLB_OSDEP_H__\n+\n+#include <string.h>\n+#include <time.h>\n+#include <unistd.h>\n+#include <cpuid.h>\n+#include <pthread.h>\n+#include <rte_string_fns.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_spinlock.h>\n+#include \"../dlb_main.h\"\n+#include \"dlb_resource.h\"\n+#include \"../../dlb_log.h\"\n+#include \"../../dlb_user.h\"\n+\n+\n+#define DLB_PCI_REG_READ(reg)        rte_read32((void *)reg)\n+#define DLB_PCI_REG_WRITE(reg, val)   rte_write32(val, (void *)reg)\n+\n+#define DLB_CSR_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->csr_kva + (reg)))\n+#define DLB_CSR_RD(hw, reg) \\\n+\tDLB_PCI_REG_READ(DLB_CSR_REG_ADDR((hw), (reg)))\n+#define DLB_CSR_WR(hw, reg, val) \\\n+\tDLB_PCI_REG_WRITE(DLB_CSR_REG_ADDR((hw), (reg)), (val))\n+\n+#define DLB_FUNC_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->func_kva + (reg)))\n+#define DLB_FUNC_RD(hw, reg) \\\n+\tDLB_PCI_REG_READ(DLB_FUNC_REG_ADDR((hw), (reg)))\n+#define DLB_FUNC_WR(hw, reg, val) \\\n+\tDLB_PCI_REG_WRITE(DLB_FUNC_REG_ADDR((hw), (reg)), (val))\n+\n+extern unsigned int dlb_unregister_timeout_s;\n+/**\n+ * os_queue_unregister_timeout_s() - timeout (in seconds) to wait for queue\n+ *                                   unregister acknowledgments.\n+ */\n+static inline unsigned int os_queue_unregister_timeout_s(void)\n+{\n+\treturn dlb_unregister_timeout_s;\n+}\n+\n+static inline size_t os_strlcpy(char *dst, const char *src, size_t sz)\n+{\n+\treturn rte_strlcpy(dst, src, sz);\n+}\n+\n+/**\n+ * os_udelay() - busy-wait for a number of microseconds\n+ * @usecs: delay duration.\n+ */\n+static inline void os_udelay(int usecs)\n+{\n+\trte_delay_us(usecs);\n+}\n+\n+/**\n+ * os_msleep() - sleep for a number of milliseconds\n+ * @usecs: delay duration.\n+ */\n+\n+static inline void os_msleep(int msecs)\n+{\n+\trte_delay_ms(msecs);\n+}\n+\n+#define DLB_PP_BASE(__is_ldb) ((__is_ldb) ? DLB_LDB_PP_BASE : DLB_DIR_PP_BASE)\n+/**\n+ * os_map_producer_port() - map a producer port into the caller's address space\n+ * @hw: dlb_hw handle for a particular device.\n+ * @port_id: port ID\n+ * @is_ldb: true for load-balanced port, false for a directed port\n+ *\n+ * This function maps the requested producer port memory into the caller's\n+ * address space.\n+ *\n+ * Return:\n+ * Returns the base address at which the PP memory was mapped, else NULL.\n+ */\n+static inline void *os_map_producer_port(struct dlb_hw *hw,\n+\t\t\t\t\t u8 port_id,\n+\t\t\t\t\t bool is_ldb)\n+{\n+\tuint64_t addr;\n+\tuint64_t pp_dma_base;\n+\n+\n+\tpp_dma_base = (uintptr_t)hw->func_kva + DLB_PP_BASE(is_ldb);\n+\taddr = (pp_dma_base + (PAGE_SIZE * port_id));\n+\n+\treturn (void *)(uintptr_t)addr;\n+\n+}\n+/**\n+ * os_unmap_producer_port() - unmap a producer port\n+ * @addr: mapped producer port address\n+ *\n+ * This function undoes os_map_producer_port() by unmapping the producer port\n+ * memory from the caller's address space.\n+ *\n+ * Return:\n+ * Returns the base address at which the PP memory was mapped, else NULL.\n+ */\n+\n+/* PFPMD - Nothing to do here, since memory was not actually mapped by us */\n+static inline void os_unmap_producer_port(struct dlb_hw *hw, void *addr)\n+{\n+\tRTE_SET_USED(hw);\n+\tRTE_SET_USED(addr);\n+}\n+/**\n+ * os_enqueue_four_hcws() - enqueue four HCWs to DLB\n+ * @hw: dlb_hw handle for a particular device.\n+ * @hcw: pointer to the 64B-aligned contiguous HCW memory\n+ * @addr: producer port address\n+ */\n+static inline void os_enqueue_four_hcws(struct dlb_hw *hw,\n+\t\t\t\t\tstruct dlb_hcw *hcw,\n+\t\t\t\t\tvoid *addr)\n+{\n+\tstruct dlb_dev *dlb_dev;\n+\n+\tdlb_dev = container_of(hw, struct dlb_dev, hw);\n+\n+\tdlb_dev->enqueue_four(hcw, addr);\n+}\n+\n+/**\n+ * os_fence_hcw() - fence an HCW to ensure it arrives at the device\n+ * @hw: dlb_hw handle for a particular device.\n+ * @pp_addr: producer port address\n+ */\n+static inline void os_fence_hcw(struct dlb_hw *hw, u64 *pp_addr)\n+{\n+\tRTE_SET_USED(hw);\n+\n+\t/* To ensure outstanding HCWs reach the device, read the PP address. IA\n+\t * memory ordering prevents reads from passing older writes, and the\n+\t * mfence also ensures this.\n+\t */\n+\trte_mb();\n+\n+\t*(volatile u64 *)pp_addr;\n+}\n+\n+/* Map to PMDs logging interface */\n+#define DLB_ERR(dev, fmt, args...) \\\n+\tDLB_LOG_ERR(fmt, ## args)\n+\n+#define DLB_INFO(dev, fmt, args...) \\\n+\tDLB_LOG_INFO(fmt, ## args)\n+\n+#define DLB_DEBUG(dev, fmt, args...) \\\n+\tDLB_LOG_DEBUG(fmt, ## args)\n+\n+/**\n+ * DLB_HW_ERR() - log an error message\n+ * @dlb: dlb_hw handle for a particular device.\n+ * @...: variable string args.\n+ */\n+#define DLB_HW_ERR(dlb, ...) do {\t\\\n+\tRTE_SET_USED(dlb);\t\t\\\n+\tDLB_ERR(dlb, __VA_ARGS__);\t\\\n+} while (0)\n+\n+/**\n+ * DLB_HW_INFO() - log an info message\n+ * @dlb: dlb_hw handle for a particular device.\n+ * @...: variable string args.\n+ */\n+#define DLB_HW_INFO(dlb, ...) do {\t\\\n+\tRTE_SET_USED(dlb);\t\t\\\n+\tDLB_INFO(dlb, __VA_ARGS__);\t\\\n+} while (0)\n+\n+/*** scheduling functions ***/\n+\n+/* The callback runs until it completes all outstanding QID->CQ\n+ * map and unmap requests. To prevent deadlock, this function gives other\n+ * threads a chance to grab the resource mutex and configure hardware.\n+ */\n+static void *dlb_complete_queue_map_unmap(void *__args)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)__args;\n+\tint ret;\n+\n+\twhile (1) {\n+\t\trte_spinlock_lock(&dlb_dev->resource_mutex);\n+\n+\t\tret = dlb_finish_unmap_qid_procedures(&dlb_dev->hw);\n+\t\tret += dlb_finish_map_qid_procedures(&dlb_dev->hw);\n+\n+\t\tif (ret != 0) {\n+\t\t\trte_spinlock_unlock(&dlb_dev->resource_mutex);\n+\t\t\t/* Relinquish the CPU so the application can process\n+\t\t\t * its CQs, so this function does not deadlock.\n+\t\t\t */\n+\t\t\tsched_yield();\n+\t\t} else\n+\t\t\tbreak;\n+\t}\n+\n+\tdlb_dev->worker_launched = false;\n+\n+\trte_spinlock_unlock(&dlb_dev->resource_mutex);\n+\n+\treturn NULL;\n+}\n+\n+\n+/**\n+ * os_schedule_work() - launch a thread to process pending map and unmap work\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function launches a thread that will run until all pending\n+ * map and unmap procedures are complete.\n+ */\n+static inline void os_schedule_work(struct dlb_hw *hw)\n+{\n+\tstruct dlb_dev *dlb_dev;\n+\tpthread_t complete_queue_map_unmap_thread;\n+\tint ret;\n+\n+\tdlb_dev = container_of(hw, struct dlb_dev, hw);\n+\n+\tret = rte_ctrl_thread_create(&complete_queue_map_unmap_thread,\n+\t\t\t\t     \"dlb_queue_unmap_waiter\",\n+\t\t\t\t     NULL,\n+\t\t\t\t     dlb_complete_queue_map_unmap,\n+\t\t\t\t     dlb_dev);\n+\tif (ret)\n+\t\tDLB_ERR(dlb_dev,\n+\t\t\"Could not create queue complete map/unmap thread, err=%d\\n\",\n+\t\t\t  ret);\n+\telse\n+\t\tdlb_dev->worker_launched = true;\n+}\n+\n+/**\n+ * os_worker_active() - query whether the map/unmap worker thread is active\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function returns a boolean indicating whether a thread (launched by\n+ * os_schedule_work()) is active. This function is used to determine\n+ * whether or not to launch a worker thread.\n+ */\n+static inline bool os_worker_active(struct dlb_hw *hw)\n+{\n+\tstruct dlb_dev *dlb_dev;\n+\n+\tdlb_dev = container_of(hw, struct dlb_dev, hw);\n+\n+\treturn dlb_dev->worker_launched;\n+}\n+\n+/**\n+ * os_notify_user_space() - notify user space\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: ID of domain to notify.\n+ * @alert_id: alert ID.\n+ * @aux_alert_data: additional alert data.\n+ *\n+ * This function notifies user space of an alert (such as a remote queue\n+ * unregister or hardware alarm).\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ */\n+static inline int os_notify_user_space(struct dlb_hw *hw,\n+\t\t\t\t       u32 domain_id,\n+\t\t\t\t       u64 alert_id,\n+\t\t\t\t       u64 aux_alert_data)\n+{\n+\tRTE_SET_USED(hw);\n+\tRTE_SET_USED(domain_id);\n+\tRTE_SET_USED(alert_id);\n+\tRTE_SET_USED(aux_alert_data);\n+\n+\t/* Not called for PF PMD */\n+\treturn -1;\n+}\n+\n+enum dlb_dev_revision {\n+\tDLB_A0,\n+\tDLB_A1,\n+\tDLB_A2,\n+\tDLB_A3,\n+\tDLB_B0,\n+};\n+\n+/**\n+ * os_get_dev_revision() - query the device_revision\n+ * @hw: dlb_hw handle for a particular device.\n+ */\n+static inline enum dlb_dev_revision os_get_dev_revision(struct dlb_hw *hw)\n+{\n+\tuint32_t a, b, c, d, stepping;\n+\n+\tRTE_SET_USED(hw);\n+\n+\t__cpuid(0x1, a, b, c, d);\n+\n+\tstepping = a & 0xf;\n+\n+\tswitch (stepping) {\n+\tcase 0:\n+\t\treturn DLB_A0;\n+\tcase 1:\n+\t\treturn DLB_A1;\n+\tcase 2:\n+\t\treturn DLB_A2;\n+\tcase 3:\n+\t\treturn DLB_A3;\n+\tdefault:\n+\t\t/* Treat all revisions >= 4 as B0 */\n+\t\treturn DLB_B0;\n+\t}\n+}\n+\n+#endif /*  __DLB_OSDEP_H__ */\ndiff --git a/drivers/event/dlb/pf/base/dlb_osdep_bitmap.h b/drivers/event/dlb/pf/base/dlb_osdep_bitmap.h\nnew file mode 100644\nindex 0000000..3ebd4ea\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_osdep_bitmap.h\n@@ -0,0 +1,441 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_OSDEP_BITMAP_H__\n+#define __DLB_OSDEP_BITMAP_H__\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <rte_bitmap.h>\n+#include <rte_string_fns.h>\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+#include \"../dlb_main.h\"\n+\n+/*************************/\n+/*** Bitmap operations ***/\n+/*************************/\n+struct dlb_bitmap {\n+\tstruct rte_bitmap *map;\n+\tunsigned int len;\n+\tstruct dlb_hw *hw;\n+};\n+\n+/**\n+ * dlb_bitmap_alloc() - alloc a bitmap data structure\n+ * @bitmap: pointer to dlb_bitmap structure pointer.\n+ * @len: number of entries in the bitmap.\n+ *\n+ * This function allocates a bitmap and initializes it with length @len. All\n+ * entries are initially zero.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or len is 0.\n+ * ENOMEM - could not allocate memory for the bitmap data structure.\n+ */\n+static inline int dlb_bitmap_alloc(struct dlb_hw *hw,\n+\t\t\t\t   struct dlb_bitmap **bitmap,\n+\t\t\t\t   unsigned int len)\n+{\n+\tstruct dlb_bitmap *bm;\n+\tvoid *mem;\n+\tuint32_t alloc_size;\n+\tuint32_t nbits = (uint32_t) len;\n+\tRTE_SET_USED(hw);\n+\n+\tif (!bitmap || nbits == 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate DLB bitmap control struct */\n+\tbm = rte_malloc(\"DLB_PF\",\n+\t\tsizeof(struct dlb_bitmap),\n+\t\tRTE_CACHE_LINE_SIZE);\n+\n+\tif (!bm)\n+\t\treturn -ENOMEM;\n+\n+\t/* Allocate bitmap memory */\n+\talloc_size = rte_bitmap_get_memory_footprint(nbits);\n+\tmem = rte_malloc(\"DLB_PF_BITMAP\", alloc_size, RTE_CACHE_LINE_SIZE);\n+\tif (!mem) {\n+\t\trte_free(bm);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbm->map = rte_bitmap_init(len, mem, alloc_size);\n+\tif (!bm->map) {\n+\t\trte_free(mem);\n+\t\trte_free(bm);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbm->len = len;\n+\n+\t*bitmap = bm;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_free() - free a previously allocated bitmap data structure\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * This function frees a bitmap that was allocated with dlb_bitmap_alloc().\n+ */\n+static inline void dlb_bitmap_free(struct dlb_bitmap *bitmap)\n+{\n+\tif (!bitmap)\n+\t\treturn;\n+\n+\trte_free(bitmap->map);\n+\trte_free(bitmap);\n+}\n+\n+/**\n+ * dlb_bitmap_fill() - fill a bitmap with all 1s\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * This function sets all bitmap values to 1.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb_bitmap_fill(struct dlb_bitmap *bitmap)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != bitmap->len; i++)\n+\t\trte_bitmap_set(bitmap->map, i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_fill() - fill a bitmap with all 0s\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * This function sets all bitmap values to 0.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb_bitmap_zero(struct dlb_bitmap *bitmap)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_reset(bitmap->map);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_set() - set a bitmap entry\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ * @bit: bit index.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the\n+ *\t    bitmap length.\n+ */\n+static inline int dlb_bitmap_set(struct dlb_bitmap *bitmap,\n+\t\t\t\t unsigned int bit)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_set(bitmap->map, bit);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_set_range() - set a range of bitmap entries\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ * @bit: starting bit index.\n+ * @len: length of the range.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the bitmap\n+ *\t    length.\n+ */\n+static inline int dlb_bitmap_set_range(struct dlb_bitmap *bitmap,\n+\t\t\t\t       unsigned int bit,\n+\t\t\t\t       unsigned int len)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != len; i++)\n+\t\trte_bitmap_set(bitmap->map, bit + i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_clear() - clear a bitmap entry\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ * @bit: bit index.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the\n+ *\t    bitmap length.\n+ */\n+static inline int dlb_bitmap_clear(struct dlb_bitmap *bitmap,\n+\t\t\t\t   unsigned int bit)\n+{\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\trte_bitmap_clear(bitmap->map, bit);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_clear_range() - clear a range of bitmap entries\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ * @bit: starting bit index.\n+ * @len: length of the range.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the bitmap\n+ *\t    length.\n+ */\n+static inline int dlb_bitmap_clear_range(struct dlb_bitmap *bitmap,\n+\t\t\t\t\t unsigned int bit,\n+\t\t\t\t\t unsigned int len)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap || !bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len <= bit)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != len; i++)\n+\t\trte_bitmap_clear(bitmap->map, bit + i);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb_bitmap_find_set_bit_range() - find a range of set bits\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ * @len: length of the range.\n+ *\n+ * This function looks for a range of set bits of length @len.\n+ *\n+ * Return:\n+ * Returns the base bit index upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * ENOENT - unable to find a length *len* range of set bits.\n+ * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.\n+ */\n+static inline int dlb_bitmap_find_set_bit_range(struct dlb_bitmap *bitmap,\n+\t\t\t\t\t\tunsigned int len)\n+{\n+\tunsigned int i, j = 0;\n+\n+\tif (!bitmap || !bitmap->map || len == 0)\n+\t\treturn -EINVAL;\n+\n+\tif (bitmap->len < len)\n+\t\treturn -ENOENT;\n+\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i)) {\n+\t\t\tif (++j == len)\n+\t\t\t\treturn i - j + 1;\n+\t\t} else\n+\t\t\tj = 0;\n+\t}\n+\n+\t/* No set bit range of length len? */\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * dlb_bitmap_find_set_bit() - find the first set bit\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * This function looks for a single set bit.\n+ *\n+ * Return:\n+ * Returns the base bit index upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * ENOENT - the bitmap contains no set bits.\n+ * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.\n+ */\n+static inline int dlb_bitmap_find_set_bit(struct dlb_bitmap *bitmap)\n+{\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i))\n+\t\t\treturn i;\n+\t}\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * dlb_bitmap_count() - returns the number of set bits\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * This function looks for a single set bit.\n+ *\n+ * Return:\n+ * Returns the number of set bits upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb_bitmap_count(struct dlb_bitmap *bitmap)\n+{\n+\tint weight = 0;\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i))\n+\t\t\tweight++;\n+\t}\n+\treturn weight;\n+}\n+\n+/**\n+ * dlb_bitmap_longest_set_range() - returns longest contiguous range of set bits\n+ * @bitmap: pointer to dlb_bitmap structure.\n+ *\n+ * Return:\n+ * Returns the bitmap's longest contiguous range of of set bits upon success,\n+ * <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - bitmap is NULL or is uninitialized.\n+ */\n+static inline int dlb_bitmap_longest_set_range(struct dlb_bitmap *bitmap)\n+{\n+\tint max_len = 0, len = 0;\n+\tunsigned int i;\n+\n+\tif (!bitmap)\n+\t\treturn -EINVAL;\n+\n+\tif (!bitmap->map)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i != bitmap->len; i++) {\n+\t\tif  (rte_bitmap_get(bitmap->map, i)) {\n+\t\t\tlen++;\n+\t\t} else {\n+\t\t\tif (len > max_len)\n+\t\t\t\tmax_len = len;\n+\t\t\tlen = 0;\n+\t\t}\n+\t}\n+\n+\tif (len > max_len)\n+\t\tmax_len = len;\n+\n+\treturn max_len;\n+}\n+\n+/**\n+ * dlb_bitmap_or() - store the logical 'or' of two bitmaps into a third\n+ * @dest: pointer to dlb_bitmap structure, which will contain the results of\n+ *\t  the 'or' of src1 and src2.\n+ * @src1: pointer to dlb_bitmap structure, will be 'or'ed with src2.\n+ * @src2: pointer to dlb_bitmap structure, will be 'or'ed with src1.\n+ *\n+ * This function 'or's two bitmaps together and stores the result in a third\n+ * bitmap. The source and destination bitmaps can be the same.\n+ *\n+ * Return:\n+ * Returns the number of set bits upon success, <0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - One of the bitmaps is NULL or is uninitialized.\n+ */\n+static inline int dlb_bitmap_or(struct dlb_bitmap *dest,\n+\t\t\t\tstruct dlb_bitmap *src1,\n+\t\t\t\tstruct dlb_bitmap *src2)\n+{\n+\tunsigned int i, min;\n+\tint numset = 0;\n+\n+\tif (!dest || !dest->map ||\n+\t    !src1 || !src1->map ||\n+\t    !src2 || !src2->map)\n+\t\treturn -EINVAL;\n+\n+\tmin = dest->len;\n+\tmin = (min > src1->len) ? src1->len : min;\n+\tmin = (min > src2->len) ? src2->len : min;\n+\n+\tfor (i = 0; i != min; i++) {\n+\t\tif  (rte_bitmap_get(src1->map, i) ||\n+\t\t\t\trte_bitmap_get(src2->map, i)) {\n+\t\t\trte_bitmap_set(dest->map, i);\n+\t\t\tnumset++;\n+\t\t} else\n+\t\t\trte_bitmap_clear(dest->map, i);\n+\t}\n+\n+\treturn numset;\n+}\n+\n+#endif /*  __DLB_OSDEP_BITMAP_H__ */\ndiff --git a/drivers/event/dlb/pf/base/dlb_osdep_list.h b/drivers/event/dlb/pf/base/dlb_osdep_list.h\nnew file mode 100644\nindex 0000000..a53b362\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_osdep_list.h\n@@ -0,0 +1,131 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_OSDEP_LIST_H__\n+#define __DLB_OSDEP_LIST_H__\n+\n+#include <rte_tailq.h>\n+\n+struct dlb_list_entry {\n+\tTAILQ_ENTRY(dlb_list_entry) node;\n+};\n+\n+/* Dummy - just a struct definition */\n+TAILQ_HEAD(dlb_list_head, dlb_list_entry);\n+\n+/* =================\n+ * TAILQ Supplements\n+ * =================\n+ */\n+\n+#ifndef TAILQ_FOREACH_ENTRY\n+#define TAILQ_FOREACH_ENTRY(ptr, head, name, iter)\t\t\\\n+\tfor ((iter) = TAILQ_FIRST(&head);\t\t\t\\\n+\t    (iter)\t\t\t\t\t\t\\\n+\t\t&& (ptr = container_of(iter, typeof(*(ptr)), name)); \\\n+\t    (iter) = TAILQ_NEXT((iter), node))\n+#endif\n+\n+#ifndef TAILQ_FOREACH_ENTRY_SAFE\n+#define TAILQ_FOREACH_ENTRY_SAFE(ptr, head, name, iter, tvar)\t\\\n+\tfor ((iter) = TAILQ_FIRST(&head);\t\t\t\\\n+\t    (iter) &&\t\t\t\t\t\t\\\n+\t\t(ptr = container_of(iter, typeof(*(ptr)), name)) &&\\\n+\t\t((tvar) = TAILQ_NEXT((iter), node), 1);\t\\\n+\t    (iter) = (tvar))\n+#endif\n+\n+/* =========\n+ * DLB Lists\n+ * =========\n+ */\n+\n+/**\n+ * dlb_list_init_head() - initialize the head of a list\n+ * @head: list head\n+ */\n+static inline void dlb_list_init_head(struct dlb_list_head *head)\n+{\n+\tTAILQ_INIT(head);\n+}\n+\n+/**\n+ * dlb_list_add() - add an entry to a list\n+ * @head: new entry will be added after this list header\n+ * @entry: new list entry to be added\n+ */\n+static inline void dlb_list_add(struct dlb_list_head *head,\n+\t\t\t\tstruct dlb_list_entry *entry)\n+{\n+\tTAILQ_INSERT_TAIL(head, entry, node);\n+}\n+\n+/**\n+ * @head: list head\n+ * @entry: list entry to be deleted\n+ */\n+static inline void dlb_list_del(struct dlb_list_head *head,\n+\t\t\t\tstruct dlb_list_entry *entry)\n+{\n+\tTAILQ_REMOVE(head, entry, node);\n+}\n+\n+/**\n+ * dlb_list_empty() - check if a list is empty\n+ * @head: list head\n+ *\n+ * Return:\n+ * Returns 1 if empty, 0 if not.\n+ */\n+static inline bool dlb_list_empty(struct dlb_list_head *head)\n+{\n+\treturn TAILQ_EMPTY(head);\n+}\n+\n+/**\n+ * dlb_list_empty() - check if a list is empty\n+ * @src_head: list to be added\n+ * @ head: where src_head will be inserted\n+ */\n+static inline void dlb_list_splice(struct dlb_list_head *src_head,\n+\t\t\t\t   struct dlb_list_head *head)\n+{\n+\tTAILQ_CONCAT(head, src_head, node);\n+}\n+\n+/**\n+ * DLB_LIST_HEAD() - retrieve the head of the list\n+ * @head: list head\n+ * @type: type of the list variable\n+ * @name: name of the dlb_list within the struct\n+ */\n+#define DLB_LIST_HEAD(head, type, name)\t\t\t\t\\\n+\t(TAILQ_FIRST(&head) ?\t\t\t\t\t\\\n+\t\tcontainer_of(TAILQ_FIRST(&head), type, name) :\t\\\n+\t\tNULL)\n+\n+/**\n+ * DLB_LIST_FOR_EACH() - iterate over a list\n+ * @head: list head\n+ * @ptr: pointer to struct containing a struct dlb_list_entry\n+ * @name: name of the dlb_list_entry field within the containing struct\n+ * @iter: iterator variable\n+ */\n+#define DLB_LIST_FOR_EACH(head, ptr, name, tmp_iter) \\\n+\tTAILQ_FOREACH_ENTRY(ptr, head, name, tmp_iter)\n+\n+/**\n+ * DLB_LIST_FOR_EACH_SAFE() - iterate over a list. This loop works even if\n+ * an element is removed from the list while processing it.\n+ * @ptr: pointer to struct containing a struct dlb_list_entry\n+ * @ptr_tmp: pointer to struct containing a struct dlb_list_entry (temporary)\n+ * @head: list head\n+ * @name: name of the dlb_list_entry field within the containing struct\n+ * @iter: iterator variable\n+ * @iter_tmp: iterator variable (temporary)\n+ */\n+#define DLB_LIST_FOR_EACH_SAFE(head, ptr, ptr_tmp, name, tmp_iter, saf_iter) \\\n+\tTAILQ_FOREACH_ENTRY_SAFE(ptr, head, name, tmp_iter, saf_iter)\n+\n+#endif /*  __DLB_OSDEP_LIST_H__ */\ndiff --git a/drivers/event/dlb/pf/base/dlb_osdep_types.h b/drivers/event/dlb/pf/base/dlb_osdep_types.h\nnew file mode 100644\nindex 0000000..2e9d7d8\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_osdep_types.h\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_OSDEP_TYPES_H\n+#define __DLB_OSDEP_TYPES_H\n+\n+#include <linux/types.h>\n+\n+#include <inttypes.h>\n+#include <ctype.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <errno.h>\n+\n+/* Types for user mode PF PMD */\n+typedef uint8_t         u8;\n+typedef int8_t          s8;\n+typedef uint16_t        u16;\n+typedef int16_t         s16;\n+typedef uint32_t        u32;\n+typedef int32_t         s32;\n+typedef uint64_t        u64;\n+\n+#define __iomem\n+\n+/* END types for user mode PF PMD */\n+\n+#endif /* __DLB_OSDEP_TYPES_H */\ndiff --git a/drivers/event/dlb/pf/base/dlb_regs.h b/drivers/event/dlb/pf/base/dlb_regs.h\nnew file mode 100644\nindex 0000000..a1c63f3\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_regs.h\n@@ -0,0 +1,2368 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_REGS_H\n+#define __DLB_REGS_H\n+\n+#include \"dlb_osdep_types.h\"\n+\n+#define DLB_MSIX_MEM_VECTOR_CTRL(x) \\\n+\t(0x100000c + (x) * 0x10)\n+#define DLB_MSIX_MEM_VECTOR_CTRL_RST 0x1\n+union dlb_msix_mem_vector_ctrl {\n+\tstruct {\n+\t\tu32 vec_mask : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_TOTAL_VAS 0x124\n+#define DLB_SYS_TOTAL_VAS_RST 0x20\n+union dlb_sys_total_vas {\n+\tstruct {\n+\t\tu32 total_vas : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_ALARM_PF_SYND2 0x508\n+#define DLB_SYS_ALARM_PF_SYND2_RST 0x0\n+union dlb_sys_alarm_pf_synd2 {\n+\tstruct {\n+\t\tu32 lock_id : 16;\n+\t\tu32 meas : 1;\n+\t\tu32 debug : 7;\n+\t\tu32 cq_pop : 1;\n+\t\tu32 qe_uhl : 1;\n+\t\tu32 qe_orsp : 1;\n+\t\tu32 qe_valid : 1;\n+\t\tu32 cq_int_rearm : 1;\n+\t\tu32 dsi_error : 1;\n+\t\tu32 rsvd0 : 2;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_ALARM_PF_SYND1 0x504\n+#define DLB_SYS_ALARM_PF_SYND1_RST 0x0\n+union dlb_sys_alarm_pf_synd1 {\n+\tstruct {\n+\t\tu32 dsi : 16;\n+\t\tu32 qid : 8;\n+\t\tu32 qtype : 2;\n+\t\tu32 qpri : 3;\n+\t\tu32 msg_type : 3;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_ALARM_PF_SYND0 0x500\n+#define DLB_SYS_ALARM_PF_SYND0_RST 0x0\n+union dlb_sys_alarm_pf_synd0 {\n+\tstruct {\n+\t\tu32 syndrome : 8;\n+\t\tu32 rtype : 2;\n+\t\tu32 rsvd0 : 2;\n+\t\tu32 from_dmv : 1;\n+\t\tu32 is_ldb : 1;\n+\t\tu32 cls : 2;\n+\t\tu32 aid : 6;\n+\t\tu32 unit : 4;\n+\t\tu32 source : 4;\n+\t\tu32 more : 1;\n+\t\tu32 valid : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_VASQID_V(x) \\\n+\t(0xf60 + (x) * 0x1000)\n+#define DLB_SYS_LDB_VASQID_V_RST 0x0\n+union dlb_sys_ldb_vasqid_v {\n+\tstruct {\n+\t\tu32 vasqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_VASQID_V(x) \\\n+\t(0xf68 + (x) * 0x1000)\n+#define DLB_SYS_DIR_VASQID_V_RST 0x0\n+union dlb_sys_dir_vasqid_v {\n+\tstruct {\n+\t\tu32 vasqid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_WBUF_DIR_FLAGS(x) \\\n+\t(0xf70 + (x) * 0x1000)\n+#define DLB_SYS_WBUF_DIR_FLAGS_RST 0x0\n+union dlb_sys_wbuf_dir_flags {\n+\tstruct {\n+\t\tu32 wb_v : 4;\n+\t\tu32 cl : 1;\n+\t\tu32 busy : 1;\n+\t\tu32 opt : 1;\n+\t\tu32 rsvd0 : 25;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_WBUF_LDB_FLAGS(x) \\\n+\t(0xf78 + (x) * 0x1000)\n+#define DLB_SYS_WBUF_LDB_FLAGS_RST 0x0\n+union dlb_sys_wbuf_ldb_flags {\n+\tstruct {\n+\t\tu32 wb_v : 4;\n+\t\tu32 cl : 1;\n+\t\tu32 busy : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_QID_V(x) \\\n+\t(0x8000034 + (x) * 0x1000)\n+#define DLB_SYS_LDB_QID_V_RST 0x0\n+union dlb_sys_ldb_qid_v {\n+\tstruct {\n+\t\tu32 qid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_QID_CFG_V(x) \\\n+\t(0x8000030 + (x) * 0x1000)\n+#define DLB_SYS_LDB_QID_CFG_V_RST 0x0\n+union dlb_sys_ldb_qid_cfg_v {\n+\tstruct {\n+\t\tu32 sn_cfg_v : 1;\n+\t\tu32 fid_cfg_v : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_QID_V(x) \\\n+\t(0x8000040 + (x) * 0x1000)\n+#define DLB_SYS_DIR_QID_V_RST 0x0\n+union dlb_sys_dir_qid_v {\n+\tstruct {\n+\t\tu32 qid_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_POOL_ENBLD(x) \\\n+\t(0x8000070 + (x) * 0x1000)\n+#define DLB_SYS_LDB_POOL_ENBLD_RST 0x0\n+union dlb_sys_ldb_pool_enbld {\n+\tstruct {\n+\t\tu32 pool_enabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_POOL_ENBLD(x) \\\n+\t(0x8000080 + (x) * 0x1000)\n+#define DLB_SYS_DIR_POOL_ENBLD_RST 0x0\n+union dlb_sys_dir_pool_enbld {\n+\tstruct {\n+\t\tu32 pool_enabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP2VPP(x) \\\n+\t(0x8000090 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP2VPP_RST 0x0\n+union dlb_sys_ldb_pp2vpp {\n+\tstruct {\n+\t\tu32 vpp : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP2VPP(x) \\\n+\t(0x8000094 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP2VPP_RST 0x0\n+union dlb_sys_dir_pp2vpp {\n+\tstruct {\n+\t\tu32 vpp : 7;\n+\t\tu32 rsvd0 : 25;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP_V(x) \\\n+\t(0x8000128 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP_V_RST 0x0\n+union dlb_sys_ldb_pp_v {\n+\tstruct {\n+\t\tu32 pp_v : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ_ISR(x) \\\n+\t(0x8000124 + (x) * 0x1000)\n+#define DLB_SYS_LDB_CQ_ISR_RST 0x0\n+/* CQ Interrupt Modes */\n+#define DLB_CQ_ISR_MODE_DIS  0\n+#define DLB_CQ_ISR_MODE_MSI  1\n+#define DLB_CQ_ISR_MODE_MSIX 2\n+union dlb_sys_ldb_cq_isr {\n+\tstruct {\n+\t\tu32 vector : 6;\n+\t\tu32 vf : 4;\n+\t\tu32 en_code : 2;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ2VF_PF(x) \\\n+\t(0x8000120 + (x) * 0x1000)\n+#define DLB_SYS_LDB_CQ2VF_PF_RST 0x0\n+union dlb_sys_ldb_cq2vf_pf {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP2VAS(x) \\\n+\t(0x800011c + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP2VAS_RST 0x0\n+union dlb_sys_ldb_pp2vas {\n+\tstruct {\n+\t\tu32 vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP2LDBPOOL(x) \\\n+\t(0x8000118 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP2LDBPOOL_RST 0x0\n+union dlb_sys_ldb_pp2ldbpool {\n+\tstruct {\n+\t\tu32 ldbpool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP2DIRPOOL(x) \\\n+\t(0x8000114 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP2DIRPOOL_RST 0x0\n+union dlb_sys_ldb_pp2dirpool {\n+\tstruct {\n+\t\tu32 dirpool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP2VF_PF(x) \\\n+\t(0x8000110 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP2VF_PF_RST 0x0\n+union dlb_sys_ldb_pp2vf_pf {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP_ADDR_U(x) \\\n+\t(0x800010c + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP_ADDR_U_RST 0x0\n+union dlb_sys_ldb_pp_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_PP_ADDR_L(x) \\\n+\t(0x8000108 + (x) * 0x1000)\n+#define DLB_SYS_LDB_PP_ADDR_L_RST 0x0\n+union dlb_sys_ldb_pp_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 7;\n+\t\tu32 addr_l : 25;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ_ADDR_U(x) \\\n+\t(0x8000104 + (x) * 0x1000)\n+#define DLB_SYS_LDB_CQ_ADDR_U_RST 0x0\n+union dlb_sys_ldb_cq_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ_ADDR_L(x) \\\n+\t(0x8000100 + (x) * 0x1000)\n+#define DLB_SYS_LDB_CQ_ADDR_L_RST 0x0\n+union dlb_sys_ldb_cq_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 6;\n+\t\tu32 addr_l : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP_V(x) \\\n+\t(0x8000228 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP_V_RST 0x0\n+union dlb_sys_dir_pp_v {\n+\tstruct {\n+\t\tu32 pp_v : 1;\n+\t\tu32 mb_dm : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_ISR(x) \\\n+\t(0x8000224 + (x) * 0x1000)\n+#define DLB_SYS_DIR_CQ_ISR_RST 0x0\n+union dlb_sys_dir_cq_isr {\n+\tstruct {\n+\t\tu32 vector : 6;\n+\t\tu32 vf : 4;\n+\t\tu32 en_code : 2;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ2VF_PF(x) \\\n+\t(0x8000220 + (x) * 0x1000)\n+#define DLB_SYS_DIR_CQ2VF_PF_RST 0x0\n+union dlb_sys_dir_cq2vf_pf {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP2VAS(x) \\\n+\t(0x800021c + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP2VAS_RST 0x0\n+union dlb_sys_dir_pp2vas {\n+\tstruct {\n+\t\tu32 vas : 5;\n+\t\tu32 rsvd0 : 27;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP2LDBPOOL(x) \\\n+\t(0x8000218 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP2LDBPOOL_RST 0x0\n+union dlb_sys_dir_pp2ldbpool {\n+\tstruct {\n+\t\tu32 ldbpool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP2DIRPOOL(x) \\\n+\t(0x8000214 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP2DIRPOOL_RST 0x0\n+union dlb_sys_dir_pp2dirpool {\n+\tstruct {\n+\t\tu32 dirpool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP2VF_PF(x) \\\n+\t(0x8000210 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP2VF_PF_RST 0x0\n+union dlb_sys_dir_pp2vf_pf {\n+\tstruct {\n+\t\tu32 vf : 4;\n+\t\tu32 is_pf : 1;\n+\t\tu32 is_hw_dsi : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP_ADDR_U(x) \\\n+\t(0x800020c + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP_ADDR_U_RST 0x0\n+union dlb_sys_dir_pp_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_PP_ADDR_L(x) \\\n+\t(0x8000208 + (x) * 0x1000)\n+#define DLB_SYS_DIR_PP_ADDR_L_RST 0x0\n+union dlb_sys_dir_pp_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 7;\n+\t\tu32 addr_l : 25;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_ADDR_U(x) \\\n+\t(0x8000204 + (x) * 0x1000)\n+#define DLB_SYS_DIR_CQ_ADDR_U_RST 0x0\n+union dlb_sys_dir_cq_addr_u {\n+\tstruct {\n+\t\tu32 addr_u : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_ADDR_L(x) \\\n+\t(0x8000200 + (x) * 0x1000)\n+#define DLB_SYS_DIR_CQ_ADDR_L_RST 0x0\n+union dlb_sys_dir_cq_addr_l {\n+\tstruct {\n+\t\tu32 rsvd0 : 6;\n+\t\tu32 addr_l : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_INGRESS_ALARM_ENBL 0x300\n+#define DLB_SYS_INGRESS_ALARM_ENBL_RST 0x0\n+union dlb_sys_ingress_alarm_enbl {\n+\tstruct {\n+\t\tu32 illegal_hcw : 1;\n+\t\tu32 illegal_pp : 1;\n+\t\tu32 disabled_pp : 1;\n+\t\tu32 illegal_qid : 1;\n+\t\tu32 disabled_qid : 1;\n+\t\tu32 illegal_ldb_qid_cfg : 1;\n+\t\tu32 illegal_cqid : 1;\n+\t\tu32 rsvd0 : 25;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_CQ_MODE 0x30c\n+#define DLB_SYS_CQ_MODE_RST 0x0\n+union dlb_sys_cq_mode {\n+\tstruct {\n+\t\tu32 ldb_cq64 : 1;\n+\t\tu32 dir_cq64 : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_MSIX_ACK 0x400\n+#define DLB_SYS_MSIX_ACK_RST 0x0\n+union dlb_sys_msix_ack {\n+\tstruct {\n+\t\tu32 msix_0_ack : 1;\n+\t\tu32 msix_1_ack : 1;\n+\t\tu32 msix_2_ack : 1;\n+\t\tu32 msix_3_ack : 1;\n+\t\tu32 msix_4_ack : 1;\n+\t\tu32 msix_5_ack : 1;\n+\t\tu32 msix_6_ack : 1;\n+\t\tu32 msix_7_ack : 1;\n+\t\tu32 msix_8_ack : 1;\n+\t\tu32 rsvd0 : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_MSIX_PASSTHRU 0x404\n+#define DLB_SYS_MSIX_PASSTHRU_RST 0x0\n+union dlb_sys_msix_passthru {\n+\tstruct {\n+\t\tu32 msix_0_passthru : 1;\n+\t\tu32 msix_1_passthru : 1;\n+\t\tu32 msix_2_passthru : 1;\n+\t\tu32 msix_3_passthru : 1;\n+\t\tu32 msix_4_passthru : 1;\n+\t\tu32 msix_5_passthru : 1;\n+\t\tu32 msix_6_passthru : 1;\n+\t\tu32 msix_7_passthru : 1;\n+\t\tu32 msix_8_passthru : 1;\n+\t\tu32 rsvd0 : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_MSIX_MODE 0x408\n+#define DLB_SYS_MSIX_MODE_RST 0x0\n+/* MSI-X Modes */\n+#define DLB_MSIX_MODE_PACKED     0\n+#define DLB_MSIX_MODE_COMPRESSED 1\n+union dlb_sys_msix_mode {\n+\tstruct {\n+\t\tu32 mode : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_31_0_OCC_INT_STS 0x440\n+#define DLB_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0\n+union dlb_sys_dir_cq_31_0_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_0_occ_int : 1;\n+\t\tu32 cq_1_occ_int : 1;\n+\t\tu32 cq_2_occ_int : 1;\n+\t\tu32 cq_3_occ_int : 1;\n+\t\tu32 cq_4_occ_int : 1;\n+\t\tu32 cq_5_occ_int : 1;\n+\t\tu32 cq_6_occ_int : 1;\n+\t\tu32 cq_7_occ_int : 1;\n+\t\tu32 cq_8_occ_int : 1;\n+\t\tu32 cq_9_occ_int : 1;\n+\t\tu32 cq_10_occ_int : 1;\n+\t\tu32 cq_11_occ_int : 1;\n+\t\tu32 cq_12_occ_int : 1;\n+\t\tu32 cq_13_occ_int : 1;\n+\t\tu32 cq_14_occ_int : 1;\n+\t\tu32 cq_15_occ_int : 1;\n+\t\tu32 cq_16_occ_int : 1;\n+\t\tu32 cq_17_occ_int : 1;\n+\t\tu32 cq_18_occ_int : 1;\n+\t\tu32 cq_19_occ_int : 1;\n+\t\tu32 cq_20_occ_int : 1;\n+\t\tu32 cq_21_occ_int : 1;\n+\t\tu32 cq_22_occ_int : 1;\n+\t\tu32 cq_23_occ_int : 1;\n+\t\tu32 cq_24_occ_int : 1;\n+\t\tu32 cq_25_occ_int : 1;\n+\t\tu32 cq_26_occ_int : 1;\n+\t\tu32 cq_27_occ_int : 1;\n+\t\tu32 cq_28_occ_int : 1;\n+\t\tu32 cq_29_occ_int : 1;\n+\t\tu32 cq_30_occ_int : 1;\n+\t\tu32 cq_31_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_63_32_OCC_INT_STS 0x444\n+#define DLB_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0\n+union dlb_sys_dir_cq_63_32_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_32_occ_int : 1;\n+\t\tu32 cq_33_occ_int : 1;\n+\t\tu32 cq_34_occ_int : 1;\n+\t\tu32 cq_35_occ_int : 1;\n+\t\tu32 cq_36_occ_int : 1;\n+\t\tu32 cq_37_occ_int : 1;\n+\t\tu32 cq_38_occ_int : 1;\n+\t\tu32 cq_39_occ_int : 1;\n+\t\tu32 cq_40_occ_int : 1;\n+\t\tu32 cq_41_occ_int : 1;\n+\t\tu32 cq_42_occ_int : 1;\n+\t\tu32 cq_43_occ_int : 1;\n+\t\tu32 cq_44_occ_int : 1;\n+\t\tu32 cq_45_occ_int : 1;\n+\t\tu32 cq_46_occ_int : 1;\n+\t\tu32 cq_47_occ_int : 1;\n+\t\tu32 cq_48_occ_int : 1;\n+\t\tu32 cq_49_occ_int : 1;\n+\t\tu32 cq_50_occ_int : 1;\n+\t\tu32 cq_51_occ_int : 1;\n+\t\tu32 cq_52_occ_int : 1;\n+\t\tu32 cq_53_occ_int : 1;\n+\t\tu32 cq_54_occ_int : 1;\n+\t\tu32 cq_55_occ_int : 1;\n+\t\tu32 cq_56_occ_int : 1;\n+\t\tu32 cq_57_occ_int : 1;\n+\t\tu32 cq_58_occ_int : 1;\n+\t\tu32 cq_59_occ_int : 1;\n+\t\tu32 cq_60_occ_int : 1;\n+\t\tu32 cq_61_occ_int : 1;\n+\t\tu32 cq_62_occ_int : 1;\n+\t\tu32 cq_63_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_95_64_OCC_INT_STS 0x448\n+#define DLB_SYS_DIR_CQ_95_64_OCC_INT_STS_RST 0x0\n+union dlb_sys_dir_cq_95_64_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_64_occ_int : 1;\n+\t\tu32 cq_65_occ_int : 1;\n+\t\tu32 cq_66_occ_int : 1;\n+\t\tu32 cq_67_occ_int : 1;\n+\t\tu32 cq_68_occ_int : 1;\n+\t\tu32 cq_69_occ_int : 1;\n+\t\tu32 cq_70_occ_int : 1;\n+\t\tu32 cq_71_occ_int : 1;\n+\t\tu32 cq_72_occ_int : 1;\n+\t\tu32 cq_73_occ_int : 1;\n+\t\tu32 cq_74_occ_int : 1;\n+\t\tu32 cq_75_occ_int : 1;\n+\t\tu32 cq_76_occ_int : 1;\n+\t\tu32 cq_77_occ_int : 1;\n+\t\tu32 cq_78_occ_int : 1;\n+\t\tu32 cq_79_occ_int : 1;\n+\t\tu32 cq_80_occ_int : 1;\n+\t\tu32 cq_81_occ_int : 1;\n+\t\tu32 cq_82_occ_int : 1;\n+\t\tu32 cq_83_occ_int : 1;\n+\t\tu32 cq_84_occ_int : 1;\n+\t\tu32 cq_85_occ_int : 1;\n+\t\tu32 cq_86_occ_int : 1;\n+\t\tu32 cq_87_occ_int : 1;\n+\t\tu32 cq_88_occ_int : 1;\n+\t\tu32 cq_89_occ_int : 1;\n+\t\tu32 cq_90_occ_int : 1;\n+\t\tu32 cq_91_occ_int : 1;\n+\t\tu32 cq_92_occ_int : 1;\n+\t\tu32 cq_93_occ_int : 1;\n+\t\tu32 cq_94_occ_int : 1;\n+\t\tu32 cq_95_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_DIR_CQ_127_96_OCC_INT_STS 0x44c\n+#define DLB_SYS_DIR_CQ_127_96_OCC_INT_STS_RST 0x0\n+union dlb_sys_dir_cq_127_96_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_96_occ_int : 1;\n+\t\tu32 cq_97_occ_int : 1;\n+\t\tu32 cq_98_occ_int : 1;\n+\t\tu32 cq_99_occ_int : 1;\n+\t\tu32 cq_100_occ_int : 1;\n+\t\tu32 cq_101_occ_int : 1;\n+\t\tu32 cq_102_occ_int : 1;\n+\t\tu32 cq_103_occ_int : 1;\n+\t\tu32 cq_104_occ_int : 1;\n+\t\tu32 cq_105_occ_int : 1;\n+\t\tu32 cq_106_occ_int : 1;\n+\t\tu32 cq_107_occ_int : 1;\n+\t\tu32 cq_108_occ_int : 1;\n+\t\tu32 cq_109_occ_int : 1;\n+\t\tu32 cq_110_occ_int : 1;\n+\t\tu32 cq_111_occ_int : 1;\n+\t\tu32 cq_112_occ_int : 1;\n+\t\tu32 cq_113_occ_int : 1;\n+\t\tu32 cq_114_occ_int : 1;\n+\t\tu32 cq_115_occ_int : 1;\n+\t\tu32 cq_116_occ_int : 1;\n+\t\tu32 cq_117_occ_int : 1;\n+\t\tu32 cq_118_occ_int : 1;\n+\t\tu32 cq_119_occ_int : 1;\n+\t\tu32 cq_120_occ_int : 1;\n+\t\tu32 cq_121_occ_int : 1;\n+\t\tu32 cq_122_occ_int : 1;\n+\t\tu32 cq_123_occ_int : 1;\n+\t\tu32 cq_124_occ_int : 1;\n+\t\tu32 cq_125_occ_int : 1;\n+\t\tu32 cq_126_occ_int : 1;\n+\t\tu32 cq_127_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ_31_0_OCC_INT_STS 0x460\n+#define DLB_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0\n+union dlb_sys_ldb_cq_31_0_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_0_occ_int : 1;\n+\t\tu32 cq_1_occ_int : 1;\n+\t\tu32 cq_2_occ_int : 1;\n+\t\tu32 cq_3_occ_int : 1;\n+\t\tu32 cq_4_occ_int : 1;\n+\t\tu32 cq_5_occ_int : 1;\n+\t\tu32 cq_6_occ_int : 1;\n+\t\tu32 cq_7_occ_int : 1;\n+\t\tu32 cq_8_occ_int : 1;\n+\t\tu32 cq_9_occ_int : 1;\n+\t\tu32 cq_10_occ_int : 1;\n+\t\tu32 cq_11_occ_int : 1;\n+\t\tu32 cq_12_occ_int : 1;\n+\t\tu32 cq_13_occ_int : 1;\n+\t\tu32 cq_14_occ_int : 1;\n+\t\tu32 cq_15_occ_int : 1;\n+\t\tu32 cq_16_occ_int : 1;\n+\t\tu32 cq_17_occ_int : 1;\n+\t\tu32 cq_18_occ_int : 1;\n+\t\tu32 cq_19_occ_int : 1;\n+\t\tu32 cq_20_occ_int : 1;\n+\t\tu32 cq_21_occ_int : 1;\n+\t\tu32 cq_22_occ_int : 1;\n+\t\tu32 cq_23_occ_int : 1;\n+\t\tu32 cq_24_occ_int : 1;\n+\t\tu32 cq_25_occ_int : 1;\n+\t\tu32 cq_26_occ_int : 1;\n+\t\tu32 cq_27_occ_int : 1;\n+\t\tu32 cq_28_occ_int : 1;\n+\t\tu32 cq_29_occ_int : 1;\n+\t\tu32 cq_30_occ_int : 1;\n+\t\tu32 cq_31_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_LDB_CQ_63_32_OCC_INT_STS 0x464\n+#define DLB_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0\n+union dlb_sys_ldb_cq_63_32_occ_int_sts {\n+\tstruct {\n+\t\tu32 cq_32_occ_int : 1;\n+\t\tu32 cq_33_occ_int : 1;\n+\t\tu32 cq_34_occ_int : 1;\n+\t\tu32 cq_35_occ_int : 1;\n+\t\tu32 cq_36_occ_int : 1;\n+\t\tu32 cq_37_occ_int : 1;\n+\t\tu32 cq_38_occ_int : 1;\n+\t\tu32 cq_39_occ_int : 1;\n+\t\tu32 cq_40_occ_int : 1;\n+\t\tu32 cq_41_occ_int : 1;\n+\t\tu32 cq_42_occ_int : 1;\n+\t\tu32 cq_43_occ_int : 1;\n+\t\tu32 cq_44_occ_int : 1;\n+\t\tu32 cq_45_occ_int : 1;\n+\t\tu32 cq_46_occ_int : 1;\n+\t\tu32 cq_47_occ_int : 1;\n+\t\tu32 cq_48_occ_int : 1;\n+\t\tu32 cq_49_occ_int : 1;\n+\t\tu32 cq_50_occ_int : 1;\n+\t\tu32 cq_51_occ_int : 1;\n+\t\tu32 cq_52_occ_int : 1;\n+\t\tu32 cq_53_occ_int : 1;\n+\t\tu32 cq_54_occ_int : 1;\n+\t\tu32 cq_55_occ_int : 1;\n+\t\tu32 cq_56_occ_int : 1;\n+\t\tu32 cq_57_occ_int : 1;\n+\t\tu32 cq_58_occ_int : 1;\n+\t\tu32 cq_59_occ_int : 1;\n+\t\tu32 cq_60_occ_int : 1;\n+\t\tu32 cq_61_occ_int : 1;\n+\t\tu32 cq_62_occ_int : 1;\n+\t\tu32 cq_63_occ_int : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_ALARM_HW_SYND 0x50c\n+#define DLB_SYS_ALARM_HW_SYND_RST 0x0\n+union dlb_sys_alarm_hw_synd {\n+\tstruct {\n+\t\tu32 syndrome : 8;\n+\t\tu32 rtype : 2;\n+\t\tu32 rsvd0 : 2;\n+\t\tu32 from_dmv : 1;\n+\t\tu32 is_ldb : 1;\n+\t\tu32 cls : 2;\n+\t\tu32 aid : 6;\n+\t\tu32 unit : 4;\n+\t\tu32 source : 4;\n+\t\tu32 more : 1;\n+\t\tu32 valid : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_SYS_SYS_ALARM_INT_ENABLE 0xc001048\n+#define DLB_SYS_SYS_ALARM_INT_ENABLE_RST 0x7fffff\n+union dlb_sys_sys_alarm_int_enable {\n+\tstruct {\n+\t\tu32 cq_addr_overflow_error : 1;\n+\t\tu32 ingress_perr : 1;\n+\t\tu32 egress_perr : 1;\n+\t\tu32 alarm_perr : 1;\n+\t\tu32 vf_to_pf_isr_pend_error : 1;\n+\t\tu32 pf_to_vf_isr_pend_error : 1;\n+\t\tu32 timeout_error : 1;\n+\t\tu32 dmvw_sm_error : 1;\n+\t\tu32 pptr_sm_par_error : 1;\n+\t\tu32 pptr_sm_len_error : 1;\n+\t\tu32 sch_sm_error : 1;\n+\t\tu32 wbuf_flag_error : 1;\n+\t\tu32 dmvw_cl_error : 1;\n+\t\tu32 dmvr_cl_error : 1;\n+\t\tu32 cmpl_data_error : 1;\n+\t\tu32 cmpl_error : 1;\n+\t\tu32 fifo_underflow : 1;\n+\t\tu32 fifo_overflow : 1;\n+\t\tu32 sb_ep_parity_err : 1;\n+\t\tu32 ti_parity_err : 1;\n+\t\tu32 ri_parity_err : 1;\n+\t\tu32 cfgm_ppw_err : 1;\n+\t\tu32 system_csr_perr : 1;\n+\t\tu32 rsvd0 : 9;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNT_CTRL(x) \\\n+\t(0x20000000 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNT_CTRL_RST 0x0\n+union dlb_lsp_cq_ldb_tot_sch_cnt_ctrl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_DSBL(x) \\\n+\t(0x20000124 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_DSBL_RST 0x1\n+union dlb_lsp_cq_ldb_dsbl {\n+\tstruct {\n+\t\tu32 disabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n+\t(0x20000120 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0\n+union dlb_lsp_cq_ldb_tot_sch_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n+\t(0x2000011c + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0\n+union dlb_lsp_cq_ldb_tot_sch_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n+\t(0x20000118 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0\n+union dlb_lsp_cq_ldb_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 ignore_depth : 1;\n+\t\tu32 enab_shallow_cq : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_TKN_CNT(x) \\\n+\t(0x20000114 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_TKN_CNT_RST 0x0\n+union dlb_lsp_cq_ldb_tkn_cnt {\n+\tstruct {\n+\t\tu32 token_count : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_INFL_LIM(x) \\\n+\t(0x20000110 + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_INFL_LIM_RST 0x0\n+union dlb_lsp_cq_ldb_infl_lim {\n+\tstruct {\n+\t\tu32 limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_LDB_INFL_CNT(x) \\\n+\t(0x2000010c + (x) * 0x1000)\n+#define DLB_LSP_CQ_LDB_INFL_CNT_RST 0x0\n+union dlb_lsp_cq_ldb_infl_cnt {\n+\tstruct {\n+\t\tu32 count : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ2QID(x, y) \\\n+\t(0x20000104 + (x) * 0x1000 + (y) * 0x4)\n+#define DLB_LSP_CQ2QID_RST 0x0\n+union dlb_lsp_cq2qid {\n+\tstruct {\n+\t\tu32 qid_p0 : 7;\n+\t\tu32 rsvd3 : 1;\n+\t\tu32 qid_p1 : 7;\n+\t\tu32 rsvd2 : 1;\n+\t\tu32 qid_p2 : 7;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 qid_p3 : 7;\n+\t\tu32 rsvd0 : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ2PRIOV(x) \\\n+\t(0x20000100 + (x) * 0x1000)\n+#define DLB_LSP_CQ2PRIOV_RST 0x0\n+union dlb_lsp_cq2priov {\n+\tstruct {\n+\t\tu32 prio : 24;\n+\t\tu32 v : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_DIR_DSBL(x) \\\n+\t(0x20000310 + (x) * 0x1000)\n+#define DLB_LSP_CQ_DIR_DSBL_RST 0x1\n+union dlb_lsp_cq_dir_dsbl {\n+\tstruct {\n+\t\tu32 disabled : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n+\t(0x2000030c + (x) * 0x1000)\n+#define DLB_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0\n+union dlb_lsp_cq_dir_tkn_depth_sel_dsi {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 disable_wb_opt : 1;\n+\t\tu32 ignore_depth : 1;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n+\t(0x20000308 + (x) * 0x1000)\n+#define DLB_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0\n+union dlb_lsp_cq_dir_tot_sch_cnth {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n+\t(0x20000304 + (x) * 0x1000)\n+#define DLB_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0\n+union dlb_lsp_cq_dir_tot_sch_cntl {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CQ_DIR_TKN_CNT(x) \\\n+\t(0x20000300 + (x) * 0x1000)\n+#define DLB_LSP_CQ_DIR_TKN_CNT_RST 0x0\n+union dlb_lsp_cq_dir_tkn_cnt {\n+\tstruct {\n+\t\tu32 count : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_QID2CQIDX(x, y) \\\n+\t(0x20000400 + (x) * 0x1000 + (y) * 0x4)\n+#define DLB_LSP_QID_LDB_QID2CQIDX_RST 0x0\n+union dlb_lsp_qid_ldb_qid2cqidx {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_QID2CQIDX2(x, y) \\\n+\t(0x20000500 + (x) * 0x1000 + (y) * 0x4)\n+#define DLB_LSP_QID_LDB_QID2CQIDX2_RST 0x0\n+union dlb_lsp_qid_ldb_qid2cqidx2 {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_ATQ_ENQUEUE_CNT(x) \\\n+\t(0x2000066c + (x) * 0x1000)\n+#define DLB_LSP_QID_ATQ_ENQUEUE_CNT_RST 0x0\n+union dlb_lsp_qid_atq_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 15;\n+\t\tu32 rsvd0 : 17;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_INFL_LIM(x) \\\n+\t(0x2000064c + (x) * 0x1000)\n+#define DLB_LSP_QID_LDB_INFL_LIM_RST 0x0\n+union dlb_lsp_qid_ldb_infl_lim {\n+\tstruct {\n+\t\tu32 limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_INFL_CNT(x) \\\n+\t(0x2000062c + (x) * 0x1000)\n+#define DLB_LSP_QID_LDB_INFL_CNT_RST 0x0\n+union dlb_lsp_qid_ldb_infl_cnt {\n+\tstruct {\n+\t\tu32 count : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_AQED_ACTIVE_LIM(x) \\\n+\t(0x20000628 + (x) * 0x1000)\n+#define DLB_LSP_QID_AQED_ACTIVE_LIM_RST 0x0\n+union dlb_lsp_qid_aqed_active_lim {\n+\tstruct {\n+\t\tu32 limit : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_AQED_ACTIVE_CNT(x) \\\n+\t(0x20000624 + (x) * 0x1000)\n+#define DLB_LSP_QID_AQED_ACTIVE_CNT_RST 0x0\n+union dlb_lsp_qid_aqed_active_cnt {\n+\tstruct {\n+\t\tu32 count : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_ENQUEUE_CNT(x) \\\n+\t(0x20000604 + (x) * 0x1000)\n+#define DLB_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0\n+union dlb_lsp_qid_ldb_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 15;\n+\t\tu32 rsvd0 : 17;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_LDB_REPLAY_CNT(x) \\\n+\t(0x20000600 + (x) * 0x1000)\n+#define DLB_LSP_QID_LDB_REPLAY_CNT_RST 0x0\n+union dlb_lsp_qid_ldb_replay_cnt {\n+\tstruct {\n+\t\tu32 count : 15;\n+\t\tu32 rsvd0 : 17;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_QID_DIR_ENQUEUE_CNT(x) \\\n+\t(0x20000700 + (x) * 0x1000)\n+#define DLB_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0\n+union dlb_lsp_qid_dir_enqueue_cnt {\n+\tstruct {\n+\t\tu32 count : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CTRL_CONFIG_0 0x2800002c\n+#define DLB_LSP_CTRL_CONFIG_0_RST 0x12cc\n+union dlb_lsp_ctrl_config_0 {\n+\tstruct {\n+\t\tu32 atm_cq_qid_priority_prot : 1;\n+\t\tu32 ldb_arb_ignore_empty : 1;\n+\t\tu32 ldb_arb_mode : 2;\n+\t\tu32 ldb_arb_threshold : 18;\n+\t\tu32 cfg_cq_sla_upd_always : 1;\n+\t\tu32 cfg_cq_wcn_upd_always : 1;\n+\t\tu32 spare : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0x28000028\n+#define DLB_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0\n+union dlb_lsp_cfg_arb_weight_atm_nalb_qid_1 {\n+\tstruct {\n+\t\tu32 slot4_weight : 8;\n+\t\tu32 slot5_weight : 8;\n+\t\tu32 slot6_weight : 8;\n+\t\tu32 slot7_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0x28000024\n+#define DLB_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0\n+union dlb_lsp_cfg_arb_weight_atm_nalb_qid_0 {\n+\tstruct {\n+\t\tu32 slot0_weight : 8;\n+\t\tu32 slot1_weight : 8;\n+\t\tu32 slot2_weight : 8;\n+\t\tu32 slot3_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CFG_ARB_WEIGHT_LDB_QID_1 0x28000020\n+#define DLB_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0\n+union dlb_lsp_cfg_arb_weight_ldb_qid_1 {\n+\tstruct {\n+\t\tu32 slot4_weight : 8;\n+\t\tu32 slot5_weight : 8;\n+\t\tu32 slot6_weight : 8;\n+\t\tu32 slot7_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_CFG_ARB_WEIGHT_LDB_QID_0 0x2800001c\n+#define DLB_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0\n+union dlb_lsp_cfg_arb_weight_ldb_qid_0 {\n+\tstruct {\n+\t\tu32 slot0_weight : 8;\n+\t\tu32 slot1_weight : 8;\n+\t\tu32 slot2_weight : 8;\n+\t\tu32 slot3_weight : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_LDB_SCHED_CTRL 0x28100000\n+#define DLB_LSP_LDB_SCHED_CTRL_RST 0x0\n+union dlb_lsp_ldb_sched_ctrl {\n+\tstruct {\n+\t\tu32 cq : 8;\n+\t\tu32 qidix : 3;\n+\t\tu32 value : 1;\n+\t\tu32 nalb_haswork_v : 1;\n+\t\tu32 rlist_haswork_v : 1;\n+\t\tu32 slist_haswork_v : 1;\n+\t\tu32 inflight_ok_v : 1;\n+\t\tu32 aqed_nfull_v : 1;\n+\t\tu32 spare0 : 15;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_DIR_SCH_CNT_H 0x2820000c\n+#define DLB_LSP_DIR_SCH_CNT_H_RST 0x0\n+union dlb_lsp_dir_sch_cnt_h {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_DIR_SCH_CNT_L 0x28200008\n+#define DLB_LSP_DIR_SCH_CNT_L_RST 0x0\n+union dlb_lsp_dir_sch_cnt_l {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_LDB_SCH_CNT_H 0x28200004\n+#define DLB_LSP_LDB_SCH_CNT_H_RST 0x0\n+union dlb_lsp_ldb_sch_cnt_h {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_LSP_LDB_SCH_CNT_L 0x28200000\n+#define DLB_LSP_LDB_SCH_CNT_L_RST 0x0\n+union dlb_lsp_ldb_sch_cnt_l {\n+\tstruct {\n+\t\tu32 count : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_DP_DIR_CSR_CTRL 0x38000018\n+#define DLB_DP_DIR_CSR_CTRL_RST 0xc0000000\n+union dlb_dp_dir_csr_ctrl {\n+\tstruct {\n+\t\tu32 cfg_int_dis : 1;\n+\t\tu32 cfg_int_dis_sbe : 1;\n+\t\tu32 cfg_int_dis_mbe : 1;\n+\t\tu32 spare0 : 27;\n+\t\tu32 cfg_vasr_dis : 1;\n+\t\tu32 cfg_int_dis_synd : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_DIR_1 0x38000014\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_DIR_1_RST 0xfffefdfc\n+union dlb_dp_cfg_ctrl_arb_weights_tqpri_dir_1 {\n+\tstruct {\n+\t\tu32 pri4 : 8;\n+\t\tu32 pri5 : 8;\n+\t\tu32 pri6 : 8;\n+\t\tu32 pri7 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_DIR_0 0x38000010\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfbfaf9f8\n+union dlb_dp_cfg_ctrl_arb_weights_tqpri_dir_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_1 0x3800000c\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0xfffefdfc\n+union dlb_dp_cfg_ctrl_arb_weights_tqpri_replay_1 {\n+\tstruct {\n+\t\tu32 pri4 : 8;\n+\t\tu32 pri5 : 8;\n+\t\tu32 pri6 : 8;\n+\t\tu32 pri7 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_0 0x38000008\n+#define DLB_DP_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfbfaf9f8\n+union dlb_dp_cfg_ctrl_arb_weights_tqpri_replay_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CTRL_ARB_WEIGHTS_TQPRI_NALB_1 0x6800001c\n+#define DLB_NALB_PIPE_CTRL_ARB_WEIGHTS_TQPRI_NALB_1_RST 0xfffefdfc\n+union dlb_nalb_pipe_ctrl_arb_weights_tqpri_nalb_1 {\n+\tstruct {\n+\t\tu32 pri4 : 8;\n+\t\tu32 pri5 : 8;\n+\t\tu32 pri6 : 8;\n+\t\tu32 pri7 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CTRL_ARB_WEIGHTS_TQPRI_NALB_0 0x68000018\n+#define DLB_NALB_PIPE_CTRL_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfbfaf9f8\n+union dlb_nalb_pipe_ctrl_arb_weights_tqpri_nalb_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATQ_1 0x68000014\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0xfffefdfc\n+union dlb_nalb_pipe_cfg_ctrl_arb_weights_tqpri_atq_1 {\n+\tstruct {\n+\t\tu32 pri4 : 8;\n+\t\tu32 pri5 : 8;\n+\t\tu32 pri6 : 8;\n+\t\tu32 pri7 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATQ_0 0x68000010\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfbfaf9f8\n+union dlb_nalb_pipe_cfg_ctrl_arb_weights_tqpri_atq_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_1 0x6800000c\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0xfffefdfc\n+union dlb_nalb_pipe_cfg_ctrl_arb_weights_tqpri_replay_1 {\n+\tstruct {\n+\t\tu32 pri4 : 8;\n+\t\tu32 pri5 : 8;\n+\t\tu32 pri6 : 8;\n+\t\tu32 pri7 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_0 0x68000008\n+#define DLB_NALB_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfbfaf9f8\n+union dlb_nalb_pipe_cfg_ctrl_arb_weights_tqpri_replay_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_ATM_PIPE_QID_LDB_QID2CQIDX(x, y) \\\n+\t(0x70000000 + (x) * 0x1000 + (y) * 0x4)\n+#define DLB_ATM_PIPE_QID_LDB_QID2CQIDX_RST 0x0\n+union dlb_atm_pipe_qid_ldb_qid2cqidx {\n+\tstruct {\n+\t\tu32 cq_p0 : 8;\n+\t\tu32 cq_p1 : 8;\n+\t\tu32 cq_p2 : 8;\n+\t\tu32 cq_p3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_ATM_PIPE_CFG_CTRL_ARB_WEIGHTS_SCHED_BIN 0x7800000c\n+#define DLB_ATM_PIPE_CFG_CTRL_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc\n+union dlb_atm_pipe_cfg_ctrl_arb_weights_sched_bin {\n+\tstruct {\n+\t\tu32 bin0 : 8;\n+\t\tu32 bin1 : 8;\n+\t\tu32 bin2 : 8;\n+\t\tu32 bin3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_ATM_PIPE_CTRL_ARB_WEIGHTS_RDY_BIN 0x78000008\n+#define DLB_ATM_PIPE_CTRL_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc\n+union dlb_atm_pipe_ctrl_arb_weights_rdy_bin {\n+\tstruct {\n+\t\tu32 bin0 : 8;\n+\t\tu32 bin1 : 8;\n+\t\tu32 bin2 : 8;\n+\t\tu32 bin3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_QID_FID_LIM(x) \\\n+\t(0x80000014 + (x) * 0x1000)\n+#define DLB_AQED_PIPE_QID_FID_LIM_RST 0x7ff\n+union dlb_aqed_pipe_qid_fid_lim {\n+\tstruct {\n+\t\tu32 qid_fid_limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_FL_POP_PTR(x) \\\n+\t(0x80000010 + (x) * 0x1000)\n+#define DLB_AQED_PIPE_FL_POP_PTR_RST 0x0\n+union dlb_aqed_pipe_fl_pop_ptr {\n+\tstruct {\n+\t\tu32 pop_ptr : 11;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_FL_PUSH_PTR(x) \\\n+\t(0x8000000c + (x) * 0x1000)\n+#define DLB_AQED_PIPE_FL_PUSH_PTR_RST 0x0\n+union dlb_aqed_pipe_fl_push_ptr {\n+\tstruct {\n+\t\tu32 push_ptr : 11;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_FL_BASE(x) \\\n+\t(0x80000008 + (x) * 0x1000)\n+#define DLB_AQED_PIPE_FL_BASE_RST 0x0\n+union dlb_aqed_pipe_fl_base {\n+\tstruct {\n+\t\tu32 base : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_FL_LIM(x) \\\n+\t(0x80000004 + (x) * 0x1000)\n+#define DLB_AQED_PIPE_FL_LIM_RST 0x800\n+union dlb_aqed_pipe_fl_lim {\n+\tstruct {\n+\t\tu32 limit : 11;\n+\t\tu32 freelist_disable : 1;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_AQED_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATM_0 0x88000008\n+#define DLB_AQED_PIPE_CFG_CTRL_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfffe\n+union dlb_aqed_pipe_cfg_ctrl_arb_weights_tqpri_atm_0 {\n+\tstruct {\n+\t\tu32 pri0 : 8;\n+\t\tu32 pri1 : 8;\n+\t\tu32 pri2 : 8;\n+\t\tu32 pri3 : 8;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_RO_PIPE_QID2GRPSLT(x) \\\n+\t(0x90000000 + (x) * 0x1000)\n+#define DLB_RO_PIPE_QID2GRPSLT_RST 0x0\n+union dlb_ro_pipe_qid2grpslt {\n+\tstruct {\n+\t\tu32 slot : 5;\n+\t\tu32 rsvd1 : 3;\n+\t\tu32 group : 2;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_RO_PIPE_GRP_SN_MODE 0x98000008\n+#define DLB_RO_PIPE_GRP_SN_MODE_RST 0x0\n+union dlb_ro_pipe_grp_sn_mode {\n+\tstruct {\n+\t\tu32 sn_mode_0 : 3;\n+\t\tu32 reserved0 : 5;\n+\t\tu32 sn_mode_1 : 3;\n+\t\tu32 reserved1 : 5;\n+\t\tu32 sn_mode_2 : 3;\n+\t\tu32 reserved2 : 5;\n+\t\tu32 sn_mode_3 : 3;\n+\t\tu32 reserved3 : 5;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_CFG_DIR_PP_SW_ALARM_EN(x) \\\n+\t(0xa000003c + (x) * 0x1000)\n+#define DLB_CHP_CFG_DIR_PP_SW_ALARM_EN_RST 0x1\n+union dlb_chp_cfg_dir_pp_sw_alarm_en {\n+\tstruct {\n+\t\tu32 alarm_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_WD_ENB(x) \\\n+\t(0xa0000038 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_WD_ENB_RST 0x0\n+union dlb_chp_dir_cq_wd_enb {\n+\tstruct {\n+\t\tu32 wd_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_LDB_PP2POOL(x) \\\n+\t(0xa0000034 + (x) * 0x1000)\n+#define DLB_CHP_DIR_LDB_PP2POOL_RST 0x0\n+union dlb_chp_dir_ldb_pp2pool {\n+\tstruct {\n+\t\tu32 pool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_DIR_PP2POOL(x) \\\n+\t(0xa0000030 + (x) * 0x1000)\n+#define DLB_CHP_DIR_DIR_PP2POOL_RST 0x0\n+union dlb_chp_dir_dir_pp2pool {\n+\tstruct {\n+\t\tu32 pool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_LDB_CRD_CNT(x) \\\n+\t(0xa000002c + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_LDB_CRD_CNT_RST 0x0\n+union dlb_chp_dir_pp_ldb_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_DIR_CRD_CNT(x) \\\n+\t(0xa0000028 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_DIR_CRD_CNT_RST 0x0\n+union dlb_chp_dir_pp_dir_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_TMR_THRESHOLD(x) \\\n+\t(0xa0000024 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_TMR_THRESHOLD_RST 0x0\n+union dlb_chp_dir_cq_tmr_threshold {\n+\tstruct {\n+\t\tu32 timer_thrsh : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INT_ENB(x) \\\n+\t(0xa0000020 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_INT_ENB_RST 0x0\n+union dlb_chp_dir_cq_int_enb {\n+\tstruct {\n+\t\tu32 en_tim : 1;\n+\t\tu32 en_depth : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0xa000001c + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0\n+union dlb_chp_dir_cq_int_depth_thrsh {\n+\tstruct {\n+\t\tu32 depth_threshold : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0xa0000018 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0\n+union dlb_chp_dir_cq_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_LDB_MIN_CRD_QNT(x) \\\n+\t(0xa0000014 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_LDB_MIN_CRD_QNT_RST 0x1\n+union dlb_chp_dir_pp_ldb_min_crd_qnt {\n+\tstruct {\n+\t\tu32 quanta : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_DIR_MIN_CRD_QNT(x) \\\n+\t(0xa0000010 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_DIR_MIN_CRD_QNT_RST 0x1\n+union dlb_chp_dir_pp_dir_min_crd_qnt {\n+\tstruct {\n+\t\tu32 quanta : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_LDB_CRD_LWM(x) \\\n+\t(0xa000000c + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_LDB_CRD_LWM_RST 0x0\n+union dlb_chp_dir_pp_ldb_crd_lwm {\n+\tstruct {\n+\t\tu32 lwm : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_LDB_CRD_HWM(x) \\\n+\t(0xa0000008 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_LDB_CRD_HWM_RST 0x0\n+union dlb_chp_dir_pp_ldb_crd_hwm {\n+\tstruct {\n+\t\tu32 hwm : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_DIR_CRD_LWM(x) \\\n+\t(0xa0000004 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_DIR_CRD_LWM_RST 0x0\n+union dlb_chp_dir_pp_dir_crd_lwm {\n+\tstruct {\n+\t\tu32 lwm : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_DIR_CRD_HWM(x) \\\n+\t(0xa0000000 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_DIR_CRD_HWM_RST 0x0\n+union dlb_chp_dir_pp_dir_crd_hwm {\n+\tstruct {\n+\t\tu32 hwm : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_CFG_LDB_PP_SW_ALARM_EN(x) \\\n+\t(0xa0000148 + (x) * 0x1000)\n+#define DLB_CHP_CFG_LDB_PP_SW_ALARM_EN_RST 0x1\n+union dlb_chp_cfg_ldb_pp_sw_alarm_en {\n+\tstruct {\n+\t\tu32 alarm_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_WD_ENB(x) \\\n+\t(0xa0000144 + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_WD_ENB_RST 0x0\n+union dlb_chp_ldb_cq_wd_enb {\n+\tstruct {\n+\t\tu32 wd_enable : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_SN_CHK_ENBL(x) \\\n+\t(0xa0000140 + (x) * 0x1000)\n+#define DLB_CHP_SN_CHK_ENBL_RST 0x0\n+union dlb_chp_sn_chk_enbl {\n+\tstruct {\n+\t\tu32 en : 1;\n+\t\tu32 rsvd0 : 31;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_HIST_LIST_BASE(x) \\\n+\t(0xa000013c + (x) * 0x1000)\n+#define DLB_CHP_HIST_LIST_BASE_RST 0x0\n+union dlb_chp_hist_list_base {\n+\tstruct {\n+\t\tu32 base : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_HIST_LIST_LIM(x) \\\n+\t(0xa0000138 + (x) * 0x1000)\n+#define DLB_CHP_HIST_LIST_LIM_RST 0x0\n+union dlb_chp_hist_list_lim {\n+\tstruct {\n+\t\tu32 limit : 13;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_LDB_PP2POOL(x) \\\n+\t(0xa0000134 + (x) * 0x1000)\n+#define DLB_CHP_LDB_LDB_PP2POOL_RST 0x0\n+union dlb_chp_ldb_ldb_pp2pool {\n+\tstruct {\n+\t\tu32 pool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_DIR_PP2POOL(x) \\\n+\t(0xa0000130 + (x) * 0x1000)\n+#define DLB_CHP_LDB_DIR_PP2POOL_RST 0x0\n+union dlb_chp_ldb_dir_pp2pool {\n+\tstruct {\n+\t\tu32 pool : 6;\n+\t\tu32 rsvd0 : 26;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_LDB_CRD_CNT(x) \\\n+\t(0xa000012c + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_LDB_CRD_CNT_RST 0x0\n+union dlb_chp_ldb_pp_ldb_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_DIR_CRD_CNT(x) \\\n+\t(0xa0000128 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_DIR_CRD_CNT_RST 0x0\n+union dlb_chp_ldb_pp_dir_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_TMR_THRESHOLD(x) \\\n+\t(0xa0000124 + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_TMR_THRESHOLD_RST 0x0\n+union dlb_chp_ldb_cq_tmr_threshold {\n+\tstruct {\n+\t\tu32 thrsh : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_INT_ENB(x) \\\n+\t(0xa0000120 + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_INT_ENB_RST 0x0\n+union dlb_chp_ldb_cq_int_enb {\n+\tstruct {\n+\t\tu32 en_tim : 1;\n+\t\tu32 en_depth : 1;\n+\t\tu32 rsvd0 : 30;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0xa000011c + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0\n+union dlb_chp_ldb_cq_int_depth_thrsh {\n+\tstruct {\n+\t\tu32 depth_threshold : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0xa0000118 + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0\n+union dlb_chp_ldb_cq_tkn_depth_sel {\n+\tstruct {\n+\t\tu32 token_depth_select : 4;\n+\t\tu32 rsvd0 : 28;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_LDB_MIN_CRD_QNT(x) \\\n+\t(0xa0000114 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_LDB_MIN_CRD_QNT_RST 0x1\n+union dlb_chp_ldb_pp_ldb_min_crd_qnt {\n+\tstruct {\n+\t\tu32 quanta : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_DIR_MIN_CRD_QNT(x) \\\n+\t(0xa0000110 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_DIR_MIN_CRD_QNT_RST 0x1\n+union dlb_chp_ldb_pp_dir_min_crd_qnt {\n+\tstruct {\n+\t\tu32 quanta : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_LDB_CRD_LWM(x) \\\n+\t(0xa000010c + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_LDB_CRD_LWM_RST 0x0\n+union dlb_chp_ldb_pp_ldb_crd_lwm {\n+\tstruct {\n+\t\tu32 lwm : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_LDB_CRD_HWM(x) \\\n+\t(0xa0000108 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_LDB_CRD_HWM_RST 0x0\n+union dlb_chp_ldb_pp_ldb_crd_hwm {\n+\tstruct {\n+\t\tu32 hwm : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_DIR_CRD_LWM(x) \\\n+\t(0xa0000104 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_DIR_CRD_LWM_RST 0x0\n+union dlb_chp_ldb_pp_dir_crd_lwm {\n+\tstruct {\n+\t\tu32 lwm : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_DIR_CRD_HWM(x) \\\n+\t(0xa0000100 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_DIR_CRD_HWM_RST 0x0\n+union dlb_chp_ldb_pp_dir_crd_hwm {\n+\tstruct {\n+\t\tu32 hwm : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_DEPTH(x) \\\n+\t(0xa0000218 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_DEPTH_RST 0x0\n+union dlb_chp_dir_cq_depth {\n+\tstruct {\n+\t\tu32 cq_depth : 11;\n+\t\tu32 rsvd0 : 21;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_WPTR(x) \\\n+\t(0xa0000214 + (x) * 0x1000)\n+#define DLB_CHP_DIR_CQ_WPTR_RST 0x0\n+union dlb_chp_dir_cq_wptr {\n+\tstruct {\n+\t\tu32 write_pointer : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_LDB_PUSH_PTR(x) \\\n+\t(0xa0000210 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_LDB_PUSH_PTR_RST 0x0\n+union dlb_chp_dir_pp_ldb_push_ptr {\n+\tstruct {\n+\t\tu32 push_pointer : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_DIR_PUSH_PTR(x) \\\n+\t(0xa000020c + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_DIR_PUSH_PTR_RST 0x0\n+union dlb_chp_dir_pp_dir_push_ptr {\n+\tstruct {\n+\t\tu32 push_pointer : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_STATE_RESET(x) \\\n+\t(0xa0000204 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_STATE_RESET_RST 0x0\n+union dlb_chp_dir_pp_state_reset {\n+\tstruct {\n+\t\tu32 rsvd1 : 7;\n+\t\tu32 dir_type : 1;\n+\t\tu32 rsvd0 : 23;\n+\t\tu32 reset_pp_state : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_PP_CRD_REQ_STATE(x) \\\n+\t(0xa0000200 + (x) * 0x1000)\n+#define DLB_CHP_DIR_PP_CRD_REQ_STATE_RST 0x0\n+union dlb_chp_dir_pp_crd_req_state {\n+\tstruct {\n+\t\tu32 dir_crd_req_active_valid : 1;\n+\t\tu32 dir_crd_req_active_check : 1;\n+\t\tu32 dir_crd_req_active_busy : 1;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 ldb_crd_req_active_valid : 1;\n+\t\tu32 ldb_crd_req_active_check : 1;\n+\t\tu32 ldb_crd_req_active_busy : 1;\n+\t\tu32 rsvd0 : 1;\n+\t\tu32 no_pp_credit_update : 1;\n+\t\tu32 crd_req_state : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_DEPTH(x) \\\n+\t(0xa0000320 + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_DEPTH_RST 0x0\n+union dlb_chp_ldb_cq_depth {\n+\tstruct {\n+\t\tu32 depth : 11;\n+\t\tu32 reserved : 2;\n+\t\tu32 rsvd0 : 19;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_WPTR(x) \\\n+\t(0xa000031c + (x) * 0x1000)\n+#define DLB_CHP_LDB_CQ_WPTR_RST 0x0\n+union dlb_chp_ldb_cq_wptr {\n+\tstruct {\n+\t\tu32 write_pointer : 10;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_LDB_PUSH_PTR(x) \\\n+\t(0xa0000318 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_LDB_PUSH_PTR_RST 0x0\n+union dlb_chp_ldb_pp_ldb_push_ptr {\n+\tstruct {\n+\t\tu32 push_pointer : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_DIR_PUSH_PTR(x) \\\n+\t(0xa0000314 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_DIR_PUSH_PTR_RST 0x0\n+union dlb_chp_ldb_pp_dir_push_ptr {\n+\tstruct {\n+\t\tu32 push_pointer : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_HIST_LIST_POP_PTR(x) \\\n+\t(0xa000030c + (x) * 0x1000)\n+#define DLB_CHP_HIST_LIST_POP_PTR_RST 0x0\n+union dlb_chp_hist_list_pop_ptr {\n+\tstruct {\n+\t\tu32 pop_ptr : 13;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_HIST_LIST_PUSH_PTR(x) \\\n+\t(0xa0000308 + (x) * 0x1000)\n+#define DLB_CHP_HIST_LIST_PUSH_PTR_RST 0x0\n+union dlb_chp_hist_list_push_ptr {\n+\tstruct {\n+\t\tu32 push_ptr : 13;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_STATE_RESET(x) \\\n+\t(0xa0000304 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_STATE_RESET_RST 0x0\n+union dlb_chp_ldb_pp_state_reset {\n+\tstruct {\n+\t\tu32 rsvd1 : 7;\n+\t\tu32 dir_type : 1;\n+\t\tu32 rsvd0 : 23;\n+\t\tu32 reset_pp_state : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_PP_CRD_REQ_STATE(x) \\\n+\t(0xa0000300 + (x) * 0x1000)\n+#define DLB_CHP_LDB_PP_CRD_REQ_STATE_RST 0x0\n+union dlb_chp_ldb_pp_crd_req_state {\n+\tstruct {\n+\t\tu32 dir_crd_req_active_valid : 1;\n+\t\tu32 dir_crd_req_active_check : 1;\n+\t\tu32 dir_crd_req_active_busy : 1;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 ldb_crd_req_active_valid : 1;\n+\t\tu32 ldb_crd_req_active_check : 1;\n+\t\tu32 ldb_crd_req_active_busy : 1;\n+\t\tu32 rsvd0 : 1;\n+\t\tu32 no_pp_credit_update : 1;\n+\t\tu32 crd_req_state : 23;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_ORD_QID_SN(x) \\\n+\t(0xa0000408 + (x) * 0x1000)\n+#define DLB_CHP_ORD_QID_SN_RST 0x0\n+union dlb_chp_ord_qid_sn {\n+\tstruct {\n+\t\tu32 sn : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_ORD_QID_SN_MAP(x) \\\n+\t(0xa0000404 + (x) * 0x1000)\n+#define DLB_CHP_ORD_QID_SN_MAP_RST 0x0\n+union dlb_chp_ord_qid_sn_map {\n+\tstruct {\n+\t\tu32 mode : 3;\n+\t\tu32 slot : 5;\n+\t\tu32 grp : 2;\n+\t\tu32 rsvd0 : 22;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_POOL_CRD_CNT(x) \\\n+\t(0xa000050c + (x) * 0x1000)\n+#define DLB_CHP_LDB_POOL_CRD_CNT_RST 0x0\n+union dlb_chp_ldb_pool_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_QED_FL_BASE(x) \\\n+\t(0xa0000508 + (x) * 0x1000)\n+#define DLB_CHP_QED_FL_BASE_RST 0x0\n+union dlb_chp_qed_fl_base {\n+\tstruct {\n+\t\tu32 base : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_QED_FL_LIM(x) \\\n+\t(0xa0000504 + (x) * 0x1000)\n+#define DLB_CHP_QED_FL_LIM_RST 0x8000\n+union dlb_chp_qed_fl_lim {\n+\tstruct {\n+\t\tu32 limit : 14;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 freelist_disable : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_POOL_CRD_LIM(x) \\\n+\t(0xa0000500 + (x) * 0x1000)\n+#define DLB_CHP_LDB_POOL_CRD_LIM_RST 0x0\n+union dlb_chp_ldb_pool_crd_lim {\n+\tstruct {\n+\t\tu32 limit : 16;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_QED_FL_POP_PTR(x) \\\n+\t(0xa0000604 + (x) * 0x1000)\n+#define DLB_CHP_QED_FL_POP_PTR_RST 0x0\n+union dlb_chp_qed_fl_pop_ptr {\n+\tstruct {\n+\t\tu32 pop_ptr : 14;\n+\t\tu32 reserved0 : 1;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_QED_FL_PUSH_PTR(x) \\\n+\t(0xa0000600 + (x) * 0x1000)\n+#define DLB_CHP_QED_FL_PUSH_PTR_RST 0x0\n+union dlb_chp_qed_fl_push_ptr {\n+\tstruct {\n+\t\tu32 push_ptr : 14;\n+\t\tu32 reserved0 : 1;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 16;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_POOL_CRD_CNT(x) \\\n+\t(0xa000070c + (x) * 0x1000)\n+#define DLB_CHP_DIR_POOL_CRD_CNT_RST 0x0\n+union dlb_chp_dir_pool_crd_cnt {\n+\tstruct {\n+\t\tu32 count : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DQED_FL_BASE(x) \\\n+\t(0xa0000708 + (x) * 0x1000)\n+#define DLB_CHP_DQED_FL_BASE_RST 0x0\n+union dlb_chp_dqed_fl_base {\n+\tstruct {\n+\t\tu32 base : 12;\n+\t\tu32 rsvd0 : 20;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DQED_FL_LIM(x) \\\n+\t(0xa0000704 + (x) * 0x1000)\n+#define DLB_CHP_DQED_FL_LIM_RST 0x2000\n+union dlb_chp_dqed_fl_lim {\n+\tstruct {\n+\t\tu32 limit : 12;\n+\t\tu32 rsvd1 : 1;\n+\t\tu32 freelist_disable : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_POOL_CRD_LIM(x) \\\n+\t(0xa0000700 + (x) * 0x1000)\n+#define DLB_CHP_DIR_POOL_CRD_LIM_RST 0x0\n+union dlb_chp_dir_pool_crd_lim {\n+\tstruct {\n+\t\tu32 limit : 14;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DQED_FL_POP_PTR(x) \\\n+\t(0xa0000804 + (x) * 0x1000)\n+#define DLB_CHP_DQED_FL_POP_PTR_RST 0x0\n+union dlb_chp_dqed_fl_pop_ptr {\n+\tstruct {\n+\t\tu32 pop_ptr : 12;\n+\t\tu32 reserved0 : 1;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DQED_FL_PUSH_PTR(x) \\\n+\t(0xa0000800 + (x) * 0x1000)\n+#define DLB_CHP_DQED_FL_PUSH_PTR_RST 0x0\n+union dlb_chp_dqed_fl_push_ptr {\n+\tstruct {\n+\t\tu32 push_ptr : 12;\n+\t\tu32 reserved0 : 1;\n+\t\tu32 generation : 1;\n+\t\tu32 rsvd0 : 18;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_CTRL_DIAG_02 0xa8000154\n+#define DLB_CHP_CTRL_DIAG_02_RST 0x0\n+union dlb_chp_ctrl_diag_02 {\n+\tstruct {\n+\t\tu32 control : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_CFG_CHP_CSR_CTRL 0xa8000130\n+#define DLB_CHP_CFG_CHP_CSR_CTRL_RST 0xc0003fff\n+#define DLB_CHP_CFG_EXCESS_TOKENS_SHIFT 12\n+union dlb_chp_cfg_chp_csr_ctrl {\n+\tstruct {\n+\t\tu32 int_inf_alarm_enable_0 : 1;\n+\t\tu32 int_inf_alarm_enable_1 : 1;\n+\t\tu32 int_inf_alarm_enable_2 : 1;\n+\t\tu32 int_inf_alarm_enable_3 : 1;\n+\t\tu32 int_inf_alarm_enable_4 : 1;\n+\t\tu32 int_inf_alarm_enable_5 : 1;\n+\t\tu32 int_inf_alarm_enable_6 : 1;\n+\t\tu32 int_inf_alarm_enable_7 : 1;\n+\t\tu32 int_inf_alarm_enable_8 : 1;\n+\t\tu32 int_inf_alarm_enable_9 : 1;\n+\t\tu32 int_inf_alarm_enable_10 : 1;\n+\t\tu32 int_inf_alarm_enable_11 : 1;\n+\t\tu32 int_inf_alarm_enable_12 : 1;\n+\t\tu32 int_cor_alarm_enable : 1;\n+\t\tu32 csr_control_spare : 14;\n+\t\tu32 cfg_vasr_dis : 1;\n+\t\tu32 counter_clear : 1;\n+\t\tu32 blk_cor_report : 1;\n+\t\tu32 blk_cor_synd : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_INTR_ARMED1 0xa8000068\n+#define DLB_CHP_LDB_CQ_INTR_ARMED1_RST 0x0\n+union dlb_chp_ldb_cq_intr_armed1 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_LDB_CQ_INTR_ARMED0 0xa8000064\n+#define DLB_CHP_LDB_CQ_INTR_ARMED0_RST 0x0\n+union dlb_chp_ldb_cq_intr_armed0 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INTR_ARMED3 0xa8000024\n+#define DLB_CHP_DIR_CQ_INTR_ARMED3_RST 0x0\n+union dlb_chp_dir_cq_intr_armed3 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INTR_ARMED2 0xa8000020\n+#define DLB_CHP_DIR_CQ_INTR_ARMED2_RST 0x0\n+union dlb_chp_dir_cq_intr_armed2 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INTR_ARMED1 0xa800001c\n+#define DLB_CHP_DIR_CQ_INTR_ARMED1_RST 0x0\n+union dlb_chp_dir_cq_intr_armed1 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CHP_DIR_CQ_INTR_ARMED0 0xa8000018\n+#define DLB_CHP_DIR_CQ_INTR_ARMED0_RST 0x0\n+union dlb_chp_dir_cq_intr_armed0 {\n+\tstruct {\n+\t\tu32 armed : 32;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CFG_MSTR_DIAG_RESET_STS 0xb8000004\n+#define DLB_CFG_MSTR_DIAG_RESET_STS_RST 0x1ff\n+union dlb_cfg_mstr_diag_reset_sts {\n+\tstruct {\n+\t\tu32 chp_pf_reset_done : 1;\n+\t\tu32 rop_pf_reset_done : 1;\n+\t\tu32 lsp_pf_reset_done : 1;\n+\t\tu32 nalb_pf_reset_done : 1;\n+\t\tu32 ap_pf_reset_done : 1;\n+\t\tu32 dp_pf_reset_done : 1;\n+\t\tu32 qed_pf_reset_done : 1;\n+\t\tu32 dqed_pf_reset_done : 1;\n+\t\tu32 aqed_pf_reset_done : 1;\n+\t\tu32 rsvd1 : 6;\n+\t\tu32 pf_reset_active : 1;\n+\t\tu32 chp_vf_reset_done : 1;\n+\t\tu32 rop_vf_reset_done : 1;\n+\t\tu32 lsp_vf_reset_done : 1;\n+\t\tu32 nalb_vf_reset_done : 1;\n+\t\tu32 ap_vf_reset_done : 1;\n+\t\tu32 dp_vf_reset_done : 1;\n+\t\tu32 qed_vf_reset_done : 1;\n+\t\tu32 dqed_vf_reset_done : 1;\n+\t\tu32 aqed_vf_reset_done : 1;\n+\t\tu32 rsvd0 : 6;\n+\t\tu32 vf_reset_active : 1;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#define DLB_CFG_MSTR_BCAST_RESET_VF_START 0xc8100000\n+#define DLB_CFG_MSTR_BCAST_RESET_VF_START_RST 0x0\n+/* HW Reset Types */\n+#define VF_RST_TYPE_CQ_LDB   0\n+#define VF_RST_TYPE_QID_LDB  1\n+#define VF_RST_TYPE_POOL_LDB 2\n+#define VF_RST_TYPE_CQ_DIR   8\n+#define VF_RST_TYPE_QID_DIR  9\n+#define VF_RST_TYPE_POOL_DIR 10\n+union dlb_cfg_mstr_bcast_reset_vf_start {\n+\tstruct {\n+\t\tu32 vf_reset_start : 1;\n+\t\tu32 reserved : 3;\n+\t\tu32 vf_reset_type : 4;\n+\t\tu32 vf_reset_id : 24;\n+\t} field;\n+\tu32 val;\n+};\n+\n+#endif /* __DLB_REGS_H */\ndiff --git a/drivers/event/dlb/pf/base/dlb_resource.c b/drivers/event/dlb/pf/base/dlb_resource.c\nnew file mode 100644\nindex 0000000..9c4267b\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_resource.c\n@@ -0,0 +1,302 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include \"dlb_hw_types.h\"\n+#include \"../../dlb_user.h\"\n+#include \"dlb_resource.h\"\n+#include \"dlb_osdep.h\"\n+#include \"dlb_osdep_bitmap.h\"\n+#include \"dlb_osdep_types.h\"\n+#include \"dlb_regs.h\"\n+\n+void dlb_disable_dp_vasr_feature(struct dlb_hw *hw)\n+{\n+\tunion dlb_dp_dir_csr_ctrl r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_DP_DIR_CSR_CTRL);\n+\n+\tr0.field.cfg_vasr_dis = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_DP_DIR_CSR_CTRL, r0.val);\n+}\n+\n+void dlb_enable_excess_tokens_alarm(struct dlb_hw *hw)\n+{\n+\tunion dlb_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.val |= 1 << DLB_CHP_CFG_EXCESS_TOKENS_SHIFT;\n+\n+\tDLB_CSR_WR(hw, DLB_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+void dlb_hw_enable_sparse_ldb_cq_mode(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_cq_mode r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_CQ_MODE);\n+\n+\tr0.field.ldb_cq64 = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_CQ_MODE, r0.val);\n+}\n+\n+void dlb_hw_enable_sparse_dir_cq_mode(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_cq_mode r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_CQ_MODE);\n+\n+\tr0.field.dir_cq64 = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_CQ_MODE, r0.val);\n+}\n+\n+void dlb_hw_disable_pf_to_vf_isr_pend_err(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_sys_alarm_int_enable r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_SYS_ALARM_INT_ENABLE);\n+\n+\tr0.field.pf_to_vf_isr_pend_error = 0;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_SYS_ALARM_INT_ENABLE, r0.val);\n+}\n+\n+void dlb_hw_get_num_resources(struct dlb_hw *hw,\n+\t\t\t      struct dlb_get_num_resources_args *arg)\n+{\n+\tstruct dlb_function_resources *rsrcs;\n+\tstruct dlb_bitmap *map;\n+\n+\trsrcs = &hw->pf;\n+\n+\targ->num_sched_domains = rsrcs->num_avail_domains;\n+\n+\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n+\n+\targ->num_ldb_ports = rsrcs->num_avail_ldb_ports;\n+\n+\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n+\n+\tmap = rsrcs->avail_aqed_freelist_entries;\n+\n+\targ->num_atomic_inflights = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_atomic_inflights =\n+\t\tdlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_hist_list_entries;\n+\n+\targ->num_hist_list_entries = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_hist_list_entries =\n+\t\tdlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_qed_freelist_entries;\n+\n+\targ->num_ldb_credits = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_ldb_credits = dlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_dqed_freelist_entries;\n+\n+\targ->num_dir_credits = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_dir_credits = dlb_bitmap_longest_set_range(map);\n+\n+\targ->num_ldb_credit_pools = rsrcs->num_avail_ldb_credit_pools;\n+\n+\targ->num_dir_credit_pools = rsrcs->num_avail_dir_credit_pools;\n+}\n+\n+static void dlb_init_fn_rsrc_lists(struct dlb_function_resources *rsrc)\n+{\n+\tdlb_list_init_head(&rsrc->avail_domains);\n+\tdlb_list_init_head(&rsrc->used_domains);\n+\tdlb_list_init_head(&rsrc->avail_ldb_queues);\n+\tdlb_list_init_head(&rsrc->avail_ldb_ports);\n+\tdlb_list_init_head(&rsrc->avail_dir_pq_pairs);\n+\tdlb_list_init_head(&rsrc->avail_ldb_credit_pools);\n+\tdlb_list_init_head(&rsrc->avail_dir_credit_pools);\n+}\n+\n+static void dlb_init_domain_rsrc_lists(struct dlb_domain *domain)\n+{\n+\tdlb_list_init_head(&domain->used_ldb_queues);\n+\tdlb_list_init_head(&domain->used_ldb_ports);\n+\tdlb_list_init_head(&domain->used_dir_pq_pairs);\n+\tdlb_list_init_head(&domain->used_ldb_credit_pools);\n+\tdlb_list_init_head(&domain->used_dir_credit_pools);\n+\tdlb_list_init_head(&domain->avail_ldb_queues);\n+\tdlb_list_init_head(&domain->avail_ldb_ports);\n+\tdlb_list_init_head(&domain->avail_dir_pq_pairs);\n+\tdlb_list_init_head(&domain->avail_ldb_credit_pools);\n+\tdlb_list_init_head(&domain->avail_dir_credit_pools);\n+}\n+\n+int dlb_resource_init(struct dlb_hw *hw)\n+{\n+\tstruct dlb_list_entry *list;\n+\tunsigned int i;\n+\n+\t/* For optimal load-balancing, ports that map to one or more QIDs in\n+\t * common should not be in numerical sequence. This is application\n+\t * dependent, but the driver interleaves port IDs as much as possible\n+\t * to reduce the likelihood of this. This initial allocation maximizes\n+\t * the average distance between an ID and its immediate neighbors (i.e.\n+\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n+\t * 3, etc.).\n+\t */\n+\tu32 init_ldb_port_allocation[DLB_MAX_NUM_LDB_PORTS] = {\n+\t\t0,  31, 62, 29, 60, 27, 58, 25, 56, 23, 54, 21, 52, 19, 50, 17,\n+\t\t48, 15, 46, 13, 44, 11, 42,  9, 40,  7, 38,  5, 36,  3, 34, 1,\n+\t\t32, 63, 30, 61, 28, 59, 26, 57, 24, 55, 22, 53, 20, 51, 18, 49,\n+\t\t16, 47, 14, 45, 12, 43, 10, 41,  8, 39,  6, 37,  4, 35,  2, 33\n+\t};\n+\n+\t/* Zero-out resource tracking data structures */\n+\tmemset(&hw->rsrcs, 0, sizeof(hw->rsrcs));\n+\tmemset(&hw->pf, 0, sizeof(hw->pf));\n+\n+\tdlb_init_fn_rsrc_lists(&hw->pf);\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DOMAINS; i++) {\n+\t\tmemset(&hw->domains[i], 0, sizeof(hw->domains[i]));\n+\t\tdlb_init_domain_rsrc_lists(&hw->domains[i]);\n+\t\thw->domains[i].parent_func = &hw->pf;\n+\t}\n+\n+\t/* Give all resources to the PF driver */\n+\thw->pf.num_avail_domains = DLB_MAX_NUM_DOMAINS;\n+\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n+\t\tlist = &hw->domains[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_domains, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_queues = DLB_MAX_NUM_LDB_QUEUES;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n+\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_queues, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_ports = DLB_MAX_NUM_LDB_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_ports; i++) {\n+\t\tstruct dlb_ldb_port *port;\n+\n+\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_ports, &port->func_list);\n+\t}\n+\n+\thw->pf.num_avail_dir_pq_pairs = DLB_MAX_NUM_DIR_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n+\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_dir_pq_pairs, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_credit_pools = DLB_MAX_NUM_LDB_CREDIT_POOLS;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_credit_pools; i++) {\n+\t\tlist = &hw->rsrcs.ldb_credit_pools[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_credit_pools, list);\n+\t}\n+\n+\thw->pf.num_avail_dir_credit_pools = DLB_MAX_NUM_DIR_CREDIT_POOLS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_credit_pools; i++) {\n+\t\tlist = &hw->rsrcs.dir_credit_pools[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_dir_credit_pools, list);\n+\t}\n+\n+\t/* There are 5120 history list entries, which allows us to overprovision\n+\t * the inflight limit (4096) by 1k.\n+\t */\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t     &hw->pf.avail_hist_list_entries,\n+\t\t\t     DLB_MAX_NUM_HIST_LIST_ENTRIES))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_hist_list_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t     &hw->pf.avail_qed_freelist_entries,\n+\t\t\t     DLB_MAX_NUM_LDB_CREDITS))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_qed_freelist_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t     &hw->pf.avail_dqed_freelist_entries,\n+\t\t\t     DLB_MAX_NUM_DIR_CREDITS))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_dqed_freelist_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t     &hw->pf.avail_aqed_freelist_entries,\n+\t\t\t     DLB_MAX_NUM_AQOS_ENTRIES))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_aqed_freelist_entries))\n+\t\treturn -1;\n+\n+\t/* Initialize the hardware resource IDs */\n+\tfor (i = 0; i < DLB_MAX_NUM_DOMAINS; i++)\n+\t\thw->domains[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_QUEUES; i++)\n+\t\thw->rsrcs.ldb_queues[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_PORTS; i++)\n+\t\thw->rsrcs.ldb_ports[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DIR_PORTS; i++)\n+\t\thw->rsrcs.dir_pq_pairs[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_CREDIT_POOLS; i++)\n+\t\thw->rsrcs.ldb_credit_pools[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DIR_CREDIT_POOLS; i++)\n+\t\thw->rsrcs.dir_credit_pools[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\thw->rsrcs.sn_groups[i].id = i;\n+\t\t/* Default mode (0) is 32 sequence numbers per queue */\n+\t\thw->rsrcs.sn_groups[i].mode = 0;\n+\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 32;\n+\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void dlb_resource_free(struct dlb_hw *hw)\n+{\n+\tdlb_bitmap_free(hw->pf.avail_hist_list_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_qed_freelist_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_dqed_freelist_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_aqed_freelist_entries);\n+}\n+\n+void dlb_hw_disable_vf_to_pf_isr_pend_err(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_sys_alarm_int_enable r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_SYS_ALARM_INT_ENABLE);\n+\n+\tr0.field.vf_to_pf_isr_pend_error = 0;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_SYS_ALARM_INT_ENABLE, r0.val);\n+}\ndiff --git a/drivers/event/dlb/pf/base/dlb_resource.h b/drivers/event/dlb/pf/base/dlb_resource.h\nnew file mode 100644\nindex 0000000..4f48b73\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_resource.h\n@@ -0,0 +1,876 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_RESOURCE_H\n+#define __DLB_RESOURCE_H\n+\n+#include \"dlb_hw_types.h\"\n+#include \"dlb_osdep_types.h\"\n+\n+/**\n+ * dlb_resource_init() - initialize the device\n+ * @hw: pointer to struct dlb_hw.\n+ *\n+ * This function initializes the device's software state (pointed to by the hw\n+ * argument) and programs global scheduling QoS registers. This function should\n+ * be called during driver initialization.\n+ *\n+ * The dlb_hw struct must be unique per DLB device and persist until the device\n+ * is reset.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -1 otherwise.\n+ */\n+int dlb_resource_init(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_resource_free() - free device state memory\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function frees software state pointed to by dlb_hw. This function\n+ * should be called when resetting the device or unloading the driver.\n+ */\n+void dlb_resource_free(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_resource_reset() - reset in-use resources to their initial state\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function resets in-use resources, and makes them available for use.\n+ */\n+void dlb_resource_reset(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_create_sched_domain() - create a scheduling domain\n+ * @hw: dlb_hw handle for a particular device.\n+ * @args: scheduling domain creation arguments.\n+ * @resp: response structure.\n+ *\n+ * This function creates a scheduling domain containing the resources specified\n+ * in args. The individual resources (queues, ports, credit pools) can be\n+ * configured after creating a scheduling domain.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the domain ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, or the requested domain name\n+ *\t    is already in use.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_sched_domain(struct dlb_hw *hw,\n+\t\t\t       struct dlb_create_sched_domain_args *args,\n+\t\t\t       struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_ldb_pool() - create a load-balanced credit pool\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: credit pool creation arguments.\n+ * @resp: response structure.\n+ *\n+ * This function creates a load-balanced credit pool containing the number of\n+ * requested credits.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the pool ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_ldb_pool(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_create_ldb_pool_args *args,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_dir_pool() - create a directed credit pool\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: credit pool creation arguments.\n+ * @resp: response structure.\n+ *\n+ * This function creates a directed credit pool containing the number of\n+ * requested credits.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the pool ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_dir_pool(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_create_dir_pool_args *args,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_ldb_queue() - create a load-balanced queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue creation arguments.\n+ * @resp: response structure.\n+ *\n+ * This function creates a load-balanced queue.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    the domain has already been started, or the requested queue name is\n+ *\t    already in use.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_ldb_queue(struct dlb_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb_create_ldb_queue_args *args,\n+\t\t\t    struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_dir_queue() - create a directed queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue creation arguments.\n+ * @resp: response structure.\n+ *\n+ * This function creates a directed queue.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t    or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_dir_queue(struct dlb_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb_create_dir_queue_args *args,\n+\t\t\t    struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_dir_port() - create a directed port\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @pop_count_dma_base: base address of the pop count memory. This can be\n+ *\t\t\ta PA or an IOVA.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ *\n+ * This function creates a directed port.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t    pool ID is invalid, a pointer address is not properly aligned, the\n+ *\t    domain is not configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_dir_port(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_create_dir_port_args *args,\n+\t\t\t   u64 pop_count_dma_base,\n+\t\t\t   u64 cq_dma_base,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_create_ldb_port() - create a load-balanced port\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @pop_count_dma_base: base address of the pop count memory. This can be\n+ *\t\t\t a PA or an IOVA.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ *\n+ * This function creates a load-balanced port.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t    pool ID is invalid, a pointer address is not properly aligned, the\n+ *\t    domain is not configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_create_ldb_port(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_create_ldb_port_args *args,\n+\t\t\t   u64 pop_count_dma_base,\n+\t\t\t   u64 cq_dma_base,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_start_domain() - start a scheduling domain\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: start domain arguments.\n+ * @resp: response structure.\n+ *\n+ * This function starts a scheduling domain, which allows applications to send\n+ * traffic through it. Once a domain is started, its resources can no longer be\n+ * configured (besides QID remapping and port enable/disable).\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - the domain is not configured, or the domain is already started.\n+ */\n+int dlb_hw_start_domain(struct dlb_hw *hw,\n+\t\t\tu32 domain_id,\n+\t\t\tstruct dlb_start_domain_args *args,\n+\t\t\tstruct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_map_qid() - map a load-balanced queue to a load-balanced port\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: map QID arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to schedule QEs from the specified queue to\n+ * the specified port. Each load-balanced port can be mapped to up to 8 queues;\n+ * each load-balanced queue can potentially map to all the load-balanced ports.\n+ *\n+ * A successful return does not necessarily mean the mapping was configured. If\n+ * this function is unable to immediately map the queue to the port, it will\n+ * add the requested operation to a per-port list of pending map/unmap\n+ * operations, and (if it's not already running) launch a kernel thread that\n+ * periodically attempts to process all pending operations. In a sense, this is\n+ * an asynchronous function.\n+ *\n+ * This asynchronicity creates two views of the state of hardware: the actual\n+ * hardware state and the requested state (as if every request completed\n+ * immediately). If there are any pending map/unmap operations, the requested\n+ * state will differ from the actual state. All validation is performed with\n+ * respect to the pending state; for instance, if there are 8 pending map\n+ * operations for port X, a request for a 9th will fail because a load-balanced\n+ * port can only map up to 8 queues.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, invalid port or queue ID, or\n+ *\t    the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_map_qid(struct dlb_hw *hw,\n+\t\t   u32 domain_id,\n+\t\t   struct dlb_map_qid_args *args,\n+\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_unmap_qid() - Unmap a load-balanced queue from a load-balanced port\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: unmap QID arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to stop scheduling QEs from the specified\n+ * queue to the specified port.\n+ *\n+ * A successful return does not necessarily mean the mapping was removed. If\n+ * this function is unable to immediately unmap the queue from the port, it\n+ * will add the requested operation to a per-port list of pending map/unmap\n+ * operations, and (if it's not already running) launch a kernel thread that\n+ * periodically attempts to process all pending operations. See\n+ * dlb_hw_map_qid() for more details.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, invalid port or queue ID, or\n+ *\t    the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_unmap_qid(struct dlb_hw *hw,\n+\t\t     u32 domain_id,\n+\t\t     struct dlb_unmap_qid_args *args,\n+\t\t     struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_finish_unmap_qid_procedures() - finish any pending unmap procedures\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding unmap procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb_finish_unmap_qid_procedures(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_finish_map_qid_procedures() - finish any pending map procedures\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding map procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb_finish_map_qid_procedures(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_enable_ldb_port() - enable a load-balanced port for scheduling\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port enable arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to schedule QEs to a load-balanced port.\n+ * Ports are enabled by default.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_enable_ldb_port(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_enable_ldb_port_args *args,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_disable_ldb_port() - disable a load-balanced port for scheduling\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port disable arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to stop scheduling QEs to a load-balanced\n+ * port. Ports are enabled by default.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_disable_ldb_port(struct dlb_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb_disable_ldb_port_args *args,\n+\t\t\t    struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_enable_dir_port() - enable a directed port for scheduling\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port enable arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to schedule QEs to a directed port.\n+ * Ports are enabled by default.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_enable_dir_port(struct dlb_hw *hw,\n+\t\t\t   u32 domain_id,\n+\t\t\t   struct dlb_enable_dir_port_args *args,\n+\t\t\t   struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_disable_dir_port() - disable a directed port for scheduling\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port disable arguments.\n+ * @resp: response structure.\n+ *\n+ * This function configures the DLB to stop scheduling QEs to a directed port.\n+ * Ports are enabled by default.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid or the domain is not configured.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb_hw_disable_dir_port(struct dlb_hw *hw,\n+\t\t\t    u32 domain_id,\n+\t\t\t    struct dlb_disable_dir_port_args *args,\n+\t\t\t    struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_configure_ldb_cq_interrupt() - configure load-balanced CQ for interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ * @port_id: load-balancd port ID.\n+ * @vector: interrupt vector ID. Should be 0 for MSI or compressed MSI-X mode,\n+ *\t    else a value up to 64.\n+ * @mode: interrupt type (DLB_CQ_ISR_MODE_MSI or DLB_CQ_ISR_MODE_MSIX)\n+ * @threshold: the minimum CQ depth at which the interrupt can fire. Must be\n+ *\tgreater than 0.\n+ *\n+ * This function configures the DLB registers for load-balanced CQ's interrupts.\n+ * This doesn't enable the CQ's interrupt; that can be done with\n+ * dlb_arm_cq_interrupt() or through an interrupt arm QE.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid.\n+ */\n+int dlb_configure_ldb_cq_interrupt(struct dlb_hw *hw,\n+\t\t\t\t   int port_id,\n+\t\t\t\t   int vector,\n+\t\t\t\t   int mode,\n+\t\t\t\t   u16 threshold);\n+\n+/**\n+ * dlb_configure_dir_cq_interrupt() - configure directed CQ for interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ * @port_id: load-balancd port ID.\n+ * @vector: interrupt vector ID. Should be 0 for MSI or compressed MSI-X mode,\n+ *\t    else a value up to 64.\n+ * @mode: interrupt type (DLB_CQ_ISR_MODE_MSI or DLB_CQ_ISR_MODE_MSIX)\n+ * @threshold: the minimum CQ depth at which the interrupt can fire. Must be\n+ *\tgreater than 0.\n+ *\n+ * This function configures the DLB registers for directed CQ's interrupts.\n+ * This doesn't enable the CQ's interrupt; that can be done with\n+ * dlb_arm_cq_interrupt() or through an interrupt arm QE.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - The port ID is invalid.\n+ */\n+int dlb_configure_dir_cq_interrupt(struct dlb_hw *hw,\n+\t\t\t\t   int port_id,\n+\t\t\t\t   int vector,\n+\t\t\t\t   int mode,\n+\t\t\t\t   u16 threshold);\n+\n+/**\n+ * dlb_enable_alarm_interrupts() - enable certain hardware alarm interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function configures the ingress error alarm. (Other alarms are enabled\n+ * by default.)\n+ */\n+void dlb_enable_alarm_interrupts(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_disable_alarm_interrupts() - disable certain hardware alarm interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function configures the ingress error alarm. (Other alarms are disabled\n+ * by default.)\n+ */\n+void dlb_disable_alarm_interrupts(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_set_msix_mode() - enable certain hardware alarm interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ * @mode: MSI-X mode (DLB_MSIX_MODE_PACKED or DLB_MSIX_MODE_COMPRESSED)\n+ *\n+ * This function configures the hardware to use either packed or compressed\n+ * mode. This function should not be called if using MSI interrupts.\n+ */\n+void dlb_set_msix_mode(struct dlb_hw *hw, int mode);\n+\n+/**\n+ * dlb_arm_cq_interrupt() - arm a CQ's interrupt\n+ * @hw: dlb_hw handle for a particular device.\n+ * @port_id: port ID\n+ * @is_ldb: true for load-balanced port, false for a directed port\n+ *\n+ * This function arms the CQ's interrupt. The CQ must be configured prior to\n+ * calling this function.\n+ *\n+ * The function does no parameter validation; that is the caller's\n+ * responsibility.\n+ *\n+ * Return: returns 0 upon success, <0 otherwise.\n+ *\n+ * EINVAL - Invalid port ID.\n+ */\n+int dlb_arm_cq_interrupt(struct dlb_hw *hw, int port_id, bool is_ldb);\n+\n+/**\n+ * dlb_read_compressed_cq_intr_status() - read compressed CQ interrupt status\n+ * @hw: dlb_hw handle for a particular device.\n+ * @ldb_interrupts: 2-entry array of u32 bitmaps\n+ * @dir_interrupts: 4-entry array of u32 bitmaps\n+ *\n+ * This function can be called from a compressed CQ interrupt handler to\n+ * determine which CQ interrupts have fired. The caller should take appropriate\n+ * (such as waking threads blocked on a CQ's interrupt) then ack the interrupts\n+ * with dlb_ack_compressed_cq_intr().\n+ */\n+void dlb_read_compressed_cq_intr_status(struct dlb_hw *hw,\n+\t\t\t\t\tu32 *ldb_interrupts,\n+\t\t\t\t\tu32 *dir_interrupts);\n+\n+/**\n+ * dlb_ack_compressed_cq_intr_status() - ack compressed CQ interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ * @ldb_interrupts: 2-entry array of u32 bitmaps\n+ * @dir_interrupts: 4-entry array of u32 bitmaps\n+ *\n+ * This function ACKs compressed CQ interrupts. Its arguments should be the\n+ * same ones passed to dlb_read_compressed_cq_intr_status().\n+ */\n+void dlb_ack_compressed_cq_intr(struct dlb_hw *hw,\n+\t\t\t\tu32 *ldb_interrupts,\n+\t\t\t\tu32 *dir_interrupts);\n+\n+/**\n+ * dlb_process_alarm_interrupt() - process an alarm interrupt\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function reads the alarm syndrome, logs its, and acks the interrupt.\n+ * This function should be called from the alarm interrupt handler when\n+ * interrupt vector DLB_INT_ALARM fires.\n+ */\n+void dlb_process_alarm_interrupt(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_process_ingress_error_interrupt() - process ingress error interrupts\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function reads the alarm syndrome, logs it, notifies user-space, and\n+ * acks the interrupt. This function should be called from the alarm interrupt\n+ * handler when interrupt vector DLB_INT_INGRESS_ERROR fires.\n+ */\n+void dlb_process_ingress_error_interrupt(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_get_group_sequence_numbers() - return a group's number of SNs per queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the configured number of sequence numbers per queue\n+ * for the specified group.\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.\n+ */\n+int dlb_get_group_sequence_numbers(struct dlb_hw *hw, unsigned int group_id);\n+\n+/**\n+ * dlb_get_group_sequence_number_occupancy() - return a group's in-use slots\n+ * @hw: dlb_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the group's number of in-use slots (i.e. load-balanced\n+ * queues using the specified group).\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's occupancy.\n+ */\n+int dlb_get_group_sequence_number_occupancy(struct dlb_hw *hw,\n+\t\t\t\t\t    unsigned int group_id);\n+\n+/**\n+ * dlb_set_group_sequence_numbers() - assign a group's number of SNs per queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ * @val: requested amount of sequence numbers per queue.\n+ *\n+ * This function configures the group's number of sequence numbers per queue.\n+ * val can be a power-of-two between 32 and 1024, inclusive. This setting can\n+ * be configured until the first ordered load-balanced queue is configured, at\n+ * which point the configuration is locked.\n+ *\n+ * Return:\n+ * Returns 0 upon success; -EINVAL if group_id or val is invalid, -EPERM if an\n+ * ordered queue is configured.\n+ */\n+int dlb_set_group_sequence_numbers(struct dlb_hw *hw,\n+\t\t\t\t   unsigned int group_id,\n+\t\t\t\t   unsigned long val);\n+\n+/**\n+ * dlb_reset_domain() - reset a scheduling domain\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ *\n+ * This function resets and frees a DLB scheduling domain and its associated\n+ * resources.\n+ *\n+ * Pre-condition: the driver must ensure software has stopped sending QEs\n+ * through this domain's producer ports before invoking this function, or\n+ * undefined behavior will result.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -1 otherwise.\n+ *\n+ * EINVAL - Invalid domain ID, or the domain is not configured.\n+ * EFAULT - Internal error. (Possibly caused if software is the pre-condition\n+ *\t    is not met.)\n+ * ETIMEDOUT - Hardware component didn't reset in the expected time.\n+ */\n+int dlb_reset_domain(struct dlb_hw *hw, u32 domain_id);\n+\n+/**\n+ * dlb_ldb_port_owned_by_domain() - query whether a port is owned by a domain\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @port_id: port ID.\n+ *\n+ * This function returns whether a load-balanced port is owned by a specified\n+ * domain.\n+ *\n+ * Return:\n+ * Returns 0 if false, 1 if true, <0 otherwise.\n+ *\n+ * EINVAL - Invalid domain or port ID, or the domain is not configured.\n+ */\n+int dlb_ldb_port_owned_by_domain(struct dlb_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t u32 port_id);\n+\n+/**\n+ * dlb_dir_port_owned_by_domain() - query whether a port is owned by a domain\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @port_id: port ID.\n+ *\n+ * This function returns whether a directed port is owned by a specified\n+ * domain.\n+ *\n+ * Return:\n+ * Returns 0 if false, 1 if true, <0 otherwise.\n+ *\n+ * EINVAL - Invalid domain or port ID, or the domain is not configured.\n+ */\n+int dlb_dir_port_owned_by_domain(struct dlb_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t u32 port_id);\n+\n+/**\n+ * dlb_hw_get_num_resources() - query the PCI function's available resources\n+ * @arg: pointer to resource counts.\n+ *\n+ * This function returns the number of available resources for the PF.\n+ */\n+void dlb_hw_get_num_resources(struct dlb_hw *hw,\n+\t\t\t      struct dlb_get_num_resources_args *arg);\n+\n+/**\n+ * dlb_hw_get_num_used_resources() - query the PCI function's used resources\n+ * @arg: pointer to resource counts.\n+ *\n+ * This function returns the number of resources in use by the PF. It fills in\n+ * the fields that args points to, except the following:\n+ * - max_contiguous_atomic_inflights\n+ * - max_contiguous_hist_list_entries\n+ * - max_contiguous_ldb_credits\n+ * - max_contiguous_dir_credits\n+ */\n+void dlb_hw_get_num_used_resources(struct dlb_hw *hw,\n+\t\t\t\t   struct dlb_get_num_resources_args *arg);\n+\n+/**\n+ * dlb_disable_dp_vasr_feature() - disable directed pipe VAS reset hardware\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function disables certain hardware in the directed pipe,\n+ * necessary to workaround a DLB VAS reset issue.\n+ */\n+void dlb_disable_dp_vasr_feature(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_enable_excess_tokens_alarm() - enable interrupts for the excess token\n+ * pop alarm\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function enables the PF ingress error alarm interrupt to fire when an\n+ * excess token pop occurs.\n+ */\n+void dlb_enable_excess_tokens_alarm(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_disable_excess_tokens_alarm() - disable interrupts for the excess token\n+ * pop alarm\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function disables the PF ingress error alarm interrupt to fire when an\n+ * excess token pop occurs.\n+ */\n+void dlb_disable_excess_tokens_alarm(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_get_ldb_queue_depth() - returns the depth of a load-balanced queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue depth args\n+ *\n+ * This function returns the depth of a load-balanced queue.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the depth.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid domain ID or queue ID.\n+ */\n+int dlb_hw_get_ldb_queue_depth(struct dlb_hw *hw,\n+\t\t\t       u32 domain_id,\n+\t\t\t       struct dlb_get_ldb_queue_depth_args *args,\n+\t\t\t       struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_get_dir_queue_depth() - returns the depth of a directed queue\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue depth args\n+ *\n+ * This function returns the depth of a directed queue.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the depth.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid domain ID or queue ID.\n+ */\n+int dlb_hw_get_dir_queue_depth(struct dlb_hw *hw,\n+\t\t\t       u32 domain_id,\n+\t\t\t       struct dlb_get_dir_queue_depth_args *args,\n+\t\t\t       struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_pending_port_unmaps() - returns the number of unmap operations in\n+ *\tprogress for a load-balanced port.\n+ * @hw: dlb_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: number of unmaps in progress args\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb_error. If successful, resp->id\n+ * contains the number of unmaps in progress.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid port ID.\n+ */\n+int dlb_hw_pending_port_unmaps(struct dlb_hw *hw,\n+\t\t\t       u32 domain_id,\n+\t\t\t       struct dlb_pending_port_unmaps_args *args,\n+\t\t\t       struct dlb_cmd_response *resp);\n+\n+/**\n+ * dlb_hw_enable_sparse_ldb_cq_mode() - enable sparse mode for load-balanced\n+ *\tports.\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb_hw_enable_sparse_ldb_cq_mode(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_enable_sparse_dir_cq_mode() - enable sparse mode for directed ports\n+ * @hw: dlb_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb_hw_enable_sparse_dir_cq_mode(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_set_qe_arbiter_weights() - program QE arbiter weights\n+ * @hw: dlb_hw handle for a particular device.\n+ * @weight: 8-entry array of arbiter weights.\n+ *\n+ * weight[N] programs priority N's weight. In cases where the 8 priorities are\n+ * reduced to 4 bins, the mapping is:\n+ * - weight[1] programs bin 0\n+ * - weight[3] programs bin 1\n+ * - weight[5] programs bin 2\n+ * - weight[7] programs bin 3\n+ */\n+void dlb_hw_set_qe_arbiter_weights(struct dlb_hw *hw, u8 weight[8]);\n+\n+/**\n+ * dlb_hw_set_qid_arbiter_weights() - program QID arbiter weights\n+ * @hw: dlb_hw handle for a particular device.\n+ * @weight: 8-entry array of arbiter weights.\n+ *\n+ * weight[N] programs priority N's weight. In cases where the 8 priorities are\n+ * reduced to 4 bins, the mapping is:\n+ * - weight[1] programs bin 0\n+ * - weight[3] programs bin 1\n+ * - weight[5] programs bin 2\n+ * - weight[7] programs bin 3\n+ */\n+void dlb_hw_set_qid_arbiter_weights(struct dlb_hw *hw, u8 weight[8]);\n+\n+/**\n+ * dlb_hw_enable_pp_sw_alarms() - enable out-of-credit alarm for all producer\n+ * ports\n+ * @hw: dlb_hw handle for a particular device.\n+ */\n+void dlb_hw_enable_pp_sw_alarms(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_disable_pp_sw_alarms() - disable out-of-credit alarm for all producer\n+ * ports\n+ * @hw: dlb_hw handle for a particular device.\n+ */\n+void dlb_hw_disable_pp_sw_alarms(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_disable_pf_to_vf_isr_pend_err() - disable alarm triggered by PF\n+ *\taccess to VF's ISR pending register\n+ * @hw: dlb_hw handle for a particular device.\n+ */\n+void dlb_hw_disable_pf_to_vf_isr_pend_err(struct dlb_hw *hw);\n+\n+/**\n+ * dlb_hw_disable_vf_to_pf_isr_pend_err() - disable alarm triggered by VF\n+ *\taccess to PF's ISR pending register\n+ * @hw: dlb_hw handle for a particular device.\n+ */\n+void dlb_hw_disable_vf_to_pf_isr_pend_err(struct dlb_hw *hw);\n+\n+#endif /* __DLB_RESOURCE_H */\ndiff --git a/drivers/event/dlb/pf/dlb_main.c b/drivers/event/dlb/pf/dlb_main.c\nnew file mode 100644\nindex 0000000..7a55140\n--- /dev/null\n+++ b/drivers/event/dlb/pf/dlb_main.c\n@@ -0,0 +1,591 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+\n+#include \"base/dlb_resource.h\"\n+#include \"base/dlb_osdep.h\"\n+#include \"base/dlb_regs.h\"\n+#include \"../dlb_priv.h\"\n+#include \"../dlb_inline_fns.h\"\n+#include \"../dlb_user.h\"\n+#include \"dlb_main.h\"\n+\n+unsigned int dlb_unregister_timeout_s = DLB_DEFAULT_UNREGISTER_TIMEOUT_S;\n+\n+#define DLB_PCI_CFG_SPACE_SIZE 256\n+#define DLB_PCI_CAP_POINTER 0x34\n+#define DLB_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC)\n+#define DLB_PCI_CAP_ID(hdr) ((hdr) & 0xFF)\n+#define DLB_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC)\n+#define DLB_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF)\n+#define DLB_PCI_EXT_CAP_ID_ERR 1\n+#define DLB_PCI_ERR_UNCOR_MASK 8\n+#define DLB_PCI_ERR_UNC_UNSUP  0x00100000\n+\n+#define DLB_PCI_EXP_DEVCTL 8\n+#define DLB_PCI_LNKCTL 16\n+#define DLB_PCI_SLTCTL 24\n+#define DLB_PCI_RTCTL 28\n+#define DLB_PCI_EXP_DEVCTL2 40\n+#define DLB_PCI_LNKCTL2 48\n+#define DLB_PCI_SLTCTL2 56\n+#define DLB_PCI_CMD 4\n+#define DLB_PCI_X_CMD 2\n+#define DLB_PCI_EXP_DEVSTA 10\n+#define DLB_PCI_EXP_DEVSTA_TRPND 0x20\n+#define DLB_PCI_EXP_DEVCTL_BCR_FLR 0x8000\n+#define DLB_PCI_PASID_CTRL 6\n+#define DLB_PCI_PASID_CAP 4\n+\n+#define DLB_PCI_CAP_ID_EXP       0x10\n+#define DLB_PCI_CAP_ID_MSIX      0x11\n+#define DLB_PCI_EXT_CAP_ID_PAS   0x1B\n+#define DLB_PCI_EXT_CAP_ID_PRI   0x13\n+#define DLB_PCI_EXT_CAP_ID_ACS   0xD\n+\n+#define DLB_PCI_PASID_CAP_EXEC          0x2\n+#define DLB_PCI_PASID_CAP_PRIV          0x4\n+#define DLB_PCI_PASID_CTRL_ENABLE       0x1\n+#define DLB_PCI_PRI_CTRL_ENABLE         0x1\n+#define DLB_PCI_PRI_ALLOC_REQ           0xC\n+#define DLB_PCI_PRI_CTRL                0x4\n+#define DLB_PCI_MSIX_FLAGS              0x2\n+#define DLB_PCI_MSIX_FLAGS_ENABLE       0x8000\n+#define DLB_PCI_MSIX_FLAGS_MASKALL      0x4000\n+#define DLB_PCI_ERR_ROOT_STATUS         0x30\n+#define DLB_PCI_ERR_COR_STATUS          0x10\n+#define DLB_PCI_ERR_UNCOR_STATUS        0x4\n+#define DLB_PCI_COMMAND_INTX_DISABLE    0x400\n+#define DLB_PCI_ACS_CAP                 0x4\n+#define DLB_PCI_ACS_CTRL                0x6\n+#define DLB_PCI_ACS_SV                  0x1\n+#define DLB_PCI_ACS_RR                  0x4\n+#define DLB_PCI_ACS_CR                  0x8\n+#define DLB_PCI_ACS_UF                  0x10\n+#define DLB_PCI_ACS_EC                  0x20\n+\n+static int dlb_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)\n+{\n+\tuint32_t hdr;\n+\tsize_t sz;\n+\tint pos;\n+\n+\tpos = DLB_PCI_CFG_SPACE_SIZE;\n+\tsz = sizeof(hdr);\n+\n+\twhile (pos > 0xFF) {\n+\t\tif (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz)\n+\t\t\treturn -1;\n+\n+\t\tif (DLB_PCI_EXT_CAP_ID(hdr) == id)\n+\t\t\treturn pos;\n+\n+\t\tpos = DLB_PCI_EXT_CAP_NEXT(hdr);\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static int dlb_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)\n+{\n+\tuint8_t pos;\n+\tint ret;\n+\tuint16_t hdr;\n+\n+\tret = rte_pci_read_config(pdev, &pos, 1, DLB_PCI_CAP_POINTER);\n+\tpos &= 0xFC;\n+\n+\tif (ret != 1)\n+\t\treturn -1;\n+\n+\twhile (pos > 0x3F) {\n+\t\tret = rte_pci_read_config(pdev, &hdr, 2, pos);\n+\t\tif (ret != 2)\n+\t\t\treturn -1;\n+\n+\t\tif (DLB_PCI_CAP_ID(hdr) == id)\n+\t\t\treturn pos;\n+\n+\t\tif (DLB_PCI_CAP_ID(hdr) == 0xFF)\n+\t\t\treturn -1;\n+\n+\t\tpos = DLB_PCI_CAP_NEXT(hdr);\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static int dlb_mask_ur_err(struct rte_pci_device *pdev)\n+{\n+\tuint32_t mask;\n+\tsize_t sz = sizeof(mask);\n+\tint pos = dlb_pci_find_ext_capability(pdev, DLB_PCI_EXT_CAP_ID_ERR);\n+\n+\tif (pos < 0) {\n+\t\tprintf(\"[%s()] failed to find the aer capability\\n\",\n+\t\t       __func__);\n+\t\treturn pos;\n+\t}\n+\n+\tpos += DLB_PCI_ERR_UNCOR_MASK;\n+\n+\tif (rte_pci_read_config(pdev, &mask, sz, pos) != (int)sz) {\n+\t\tprintf(\"[%s()] Failed to read uncorrectable error mask reg\\n\",\n+\t\t       __func__);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Mask Unsupported Request errors */\n+\tmask |= DLB_PCI_ERR_UNC_UNSUP;\n+\n+\tif (rte_pci_write_config(pdev, &mask, sz, pos) != (int)sz) {\n+\t\tprintf(\"[%s()] Failed to write uncorrectable error mask reg at offset %d\\n\",\n+\t\t       __func__, pos);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+struct dlb_dev *\n+dlb_probe(struct rte_pci_device *pdev)\n+{\n+\tstruct dlb_dev *dlb_dev;\n+\tint ret = 0;\n+\n+\tDLB_INFO(dlb_dev, \"probe\\n\");\n+\n+\tdlb_dev = rte_malloc(\"DLB_PF\", sizeof(struct dlb_dev),\n+\t\t\t     RTE_CACHE_LINE_SIZE);\n+\n+\tif (!dlb_dev) {\n+\t\tret = -ENOMEM;\n+\t\tgoto dlb_dev_malloc_fail;\n+\t}\n+\n+\t/* PCI Bus driver has already mapped bar space into process.\n+\t * Save off our IO register and FUNC addresses.\n+\t */\n+\n+\t/* BAR 0 */\n+\tif (pdev->mem_resource[0].addr == NULL) {\n+\t\tDLB_ERR(dlb_dev, \"probe: BAR 0 addr (csr_kva) is NULL\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto pci_mmap_bad_addr;\n+\t}\n+\tdlb_dev->hw.func_kva = (void *)(uintptr_t)pdev->mem_resource[0].addr;\n+\tdlb_dev->hw.func_phys_addr = pdev->mem_resource[0].phys_addr;\n+\n+\tDLB_INFO(dlb_dev, \"DLB FUNC VA=%p, PA=%p, len=%\"PRIu64\"\\n\",\n+\t\t (void *)dlb_dev->hw.func_kva,\n+\t\t (void *)dlb_dev->hw.func_phys_addr,\n+\t\t pdev->mem_resource[0].len);\n+\n+\t/* BAR 2 */\n+\tif (pdev->mem_resource[2].addr == NULL) {\n+\t\tDLB_ERR(dlb_dev, \"probe: BAR 2 addr (func_kva) is NULL\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto pci_mmap_bad_addr;\n+\t}\n+\tdlb_dev->hw.csr_kva = (void *)(uintptr_t)pdev->mem_resource[2].addr;\n+\tdlb_dev->hw.csr_phys_addr = pdev->mem_resource[2].phys_addr;\n+\n+\tDLB_INFO(dlb_dev, \"DLB CSR VA=%p, PA=%p, len=%\"PRIu64\"\\n\",\n+\t\t (void *)dlb_dev->hw.csr_kva,\n+\t\t (void *)dlb_dev->hw.csr_phys_addr,\n+\t\t pdev->mem_resource[2].len);\n+\n+\tdlb_dev->pdev = pdev;\n+\n+\tret = dlb_pf_reset(dlb_dev);\n+\tif (ret)\n+\t\tgoto dlb_reset_fail;\n+\n+\t/* DLB incorrectly sends URs in response to certain messages. Mask UR\n+\t * errors to prevent these from being propagated to the MCA.\n+\t */\n+\tret = dlb_mask_ur_err(pdev);\n+\tif (ret)\n+\t\tgoto mask_ur_err_fail;\n+\n+\tret = dlb_pf_init_driver_state(dlb_dev);\n+\tif (ret)\n+\t\tgoto init_driver_state_fail;\n+\n+\tret = dlb_resource_init(&dlb_dev->hw);\n+\tif (ret)\n+\t\tgoto resource_init_fail;\n+\n+\tdlb_dev->revision = os_get_dev_revision(&dlb_dev->hw);\n+\n+\tdlb_pf_init_hardware(dlb_dev);\n+\n+\treturn dlb_dev;\n+\n+resource_init_fail:\n+\tdlb_resource_free(&dlb_dev->hw);\n+init_driver_state_fail:\n+mask_ur_err_fail:\n+dlb_reset_fail:\n+pci_mmap_bad_addr:\n+\trte_free(dlb_dev);\n+dlb_dev_malloc_fail:\n+\trte_errno = ret;\n+\treturn NULL;\n+}\n+\n+int\n+dlb_pf_reset(struct dlb_dev *dlb_dev)\n+{\n+\tint msix_cap_offset, err_cap_offset, acs_cap_offset, wait_count;\n+\tuint16_t dev_ctl_word, dev_ctl2_word, lnk_word, lnk_word2;\n+\tuint16_t rt_ctl_word, pri_reqs_dword,  pri_ctrl_word;\n+\tstruct rte_pci_device *pdev = dlb_dev->pdev;\n+\tuint16_t devsta_busy_word, devctl_word;\n+\tint pcie_cap_offset, pri_cap_offset;\n+\tuint16_t slt_word, slt_word2, cmd;\n+\tint ret = 0, i = 0;\n+\tuint32_t dword[16];\n+\toff_t off;\n+\n+\t/* Save PCI config state */\n+\n+\tfor (i = 0; i < 16; i++) {\n+\t\tif (rte_pci_read_config(pdev, &dword[i], 4, i * 4) != 4)\n+\t\t\treturn ret;\n+\t}\n+\n+\tpcie_cap_offset = dlb_pci_find_capability(pdev, DLB_PCI_CAP_ID_EXP);\n+\n+\tif (pcie_cap_offset < 0) {\n+\t\tprintf(\"[%s()] failed to find the pcie capability\\n\",\n+\t\t       __func__);\n+\t\treturn pcie_cap_offset;\n+\t}\n+\n+\toff = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;\n+\tif (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)\n+\t\tdev_ctl_word = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_LNKCTL;\n+\tif (rte_pci_read_config(pdev, &lnk_word, 2, off) != 2)\n+\t\tlnk_word = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_SLTCTL;\n+\tif (rte_pci_read_config(pdev, &slt_word, 2, off) != 2)\n+\t\tslt_word = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_RTCTL;\n+\tif (rte_pci_read_config(pdev, &rt_ctl_word, 2, off) != 2)\n+\t\trt_ctl_word = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_EXP_DEVCTL2;\n+\tif (rte_pci_read_config(pdev, &dev_ctl2_word, 2, off) != 2)\n+\t\tdev_ctl2_word = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_LNKCTL2;\n+\tif (rte_pci_read_config(pdev, &lnk_word2, 2, off) != 2)\n+\t\tlnk_word2 = 0;\n+\n+\toff = pcie_cap_offset + DLB_PCI_SLTCTL2;\n+\tif (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)\n+\t\tslt_word2 = 0;\n+\n+\tpri_cap_offset = dlb_pci_find_ext_capability(pdev,\n+\t\t\t\t\t\t     DLB_PCI_EXT_CAP_ID_PRI);\n+\tif (pri_cap_offset >= 0) {\n+\t\toff = pri_cap_offset + DLB_PCI_PRI_ALLOC_REQ;\n+\t\tif (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) != 4)\n+\t\t\tpri_reqs_dword = 0;\n+\t}\n+\n+\t/* clear the PCI command register before issuing the FLR */\n+\n+\toff = DLB_PCI_CMD;\n+\tcmd = 0;\n+\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t       __func__, (int)off);\n+\t\treturn -1;\n+\t}\n+\n+\t/* issue the FLR */\n+\tfor (wait_count = 0; wait_count < 4; wait_count++) {\n+\t\tint sleep_time;\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_EXP_DEVSTA;\n+\t\tret = rte_pci_read_config(pdev, &devsta_busy_word, 2, off);\n+\t\tif (ret != 2) {\n+\t\t\tprintf(\"[%s()] failed to read the pci device status\\n\",\n+\t\t\t       __func__);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (!(devsta_busy_word & DLB_PCI_EXP_DEVSTA_TRPND))\n+\t\t\tbreak;\n+\n+\t\tsleep_time = (1 << (wait_count)) * 100;\n+\t\trte_delay_ms(sleep_time);\n+\t}\n+\n+\tif (wait_count == 4) {\n+\t\tprintf(\"[%s()] wait for pci pending transactions timed out\\n\",\n+\t\t       __func__);\n+\t\treturn -1;\n+\t}\n+\n+\toff = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;\n+\tret = rte_pci_read_config(pdev, &devctl_word, 2, off);\n+\tif (ret != 2) {\n+\t\tprintf(\"[%s()] failed to read the pcie device control\\n\",\n+\t\t       __func__);\n+\t\treturn ret;\n+\t}\n+\n+\tdevctl_word |= DLB_PCI_EXP_DEVCTL_BCR_FLR;\n+\n+\tif (rte_pci_write_config(pdev, &devctl_word, 2, off) != 2) {\n+\t\tprintf(\"[%s()] failed to write the pcie device control at offset %d\\n\",\n+\t\t       __func__, (int)off);\n+\t\treturn -1;\n+\t}\n+\n+\trte_delay_ms(100);\n+\n+\t/* Restore PCI config state */\n+\n+\tif (pcie_cap_offset >= 0) {\n+\t\toff = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;\n+\t\tif (rte_pci_write_config(pdev, &dev_ctl_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write the pcie device control at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_LNKCTL;\n+\t\tif (rte_pci_write_config(pdev, &lnk_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_SLTCTL;\n+\t\tif (rte_pci_write_config(pdev, &slt_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_RTCTL;\n+\t\tif (rte_pci_write_config(pdev, &rt_ctl_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_EXP_DEVCTL2;\n+\t\tif (rte_pci_write_config(pdev, &dev_ctl2_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_LNKCTL2;\n+\t\tif (rte_pci_write_config(pdev, &lnk_word2, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pcie_cap_offset + DLB_PCI_SLTCTL2;\n+\t\tif (rte_pci_write_config(pdev, &slt_word2, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tif (pri_cap_offset >= 0) {\n+\t\tpri_ctrl_word = DLB_PCI_PRI_CTRL_ENABLE;\n+\n+\t\toff = pri_cap_offset + DLB_PCI_PRI_ALLOC_REQ;\n+\t\tif (rte_pci_write_config(pdev, &pri_reqs_dword, 4, off) != 4) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = pri_cap_offset + DLB_PCI_PRI_CTRL;\n+\t\tif (rte_pci_write_config(pdev, &pri_ctrl_word, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\terr_cap_offset = dlb_pci_find_ext_capability(pdev,\n+\t\t\t\t\t\t     DLB_PCI_EXT_CAP_ID_ERR);\n+\tif (err_cap_offset >= 0) {\n+\t\tuint32_t tmp;\n+\n+\t\toff = err_cap_offset + DLB_PCI_ERR_ROOT_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tif (rte_pci_write_config(pdev, &tmp, 4, off) != 4) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = err_cap_offset + DLB_PCI_ERR_COR_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tif (rte_pci_write_config(pdev, &tmp, 4, off) != 4) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = err_cap_offset + DLB_PCI_ERR_UNCOR_STATUS;\n+\t\tif (rte_pci_read_config(pdev, &tmp, 4, off) != 4)\n+\t\t\ttmp = 0;\n+\n+\t\tif (rte_pci_write_config(pdev, &tmp, 4, off) != 4) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tfor (i = 16; i > 0; i--) {\n+\t\toff = (i - 1) * 4;\n+\t\tif (rte_pci_write_config(pdev, &dword[i - 1], 4, off) != 4) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\toff = DLB_PCI_CMD;\n+\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\tcmd &= ~DLB_PCI_COMMAND_INTX_DISABLE;\n+\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space\\n\",\n+\t\t\t       __func__);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tmsix_cap_offset = dlb_pci_find_capability(pdev, DLB_PCI_CAP_ID_MSIX);\n+\tif (msix_cap_offset >= 0) {\n+\t\toff = msix_cap_offset + DLB_PCI_MSIX_FLAGS;\n+\t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\t\tcmd |= DLB_PCI_MSIX_FLAGS_ENABLE;\n+\t\t\tcmd |= DLB_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\t\tprintf(\"[%s()] failed to write msix flags\\n\",\n+\t\t\t\t       __func__);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\toff = msix_cap_offset + DLB_PCI_MSIX_FLAGS;\n+\t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n+\t\t\tcmd &= ~DLB_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n+\t\t\t\tprintf(\"[%s()] failed to write msix flags\\n\",\n+\t\t\t\t       __func__);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tacs_cap_offset = dlb_pci_find_ext_capability(pdev,\n+\t\t\t\t\t\t     DLB_PCI_EXT_CAP_ID_ACS);\n+\tif (acs_cap_offset >= 0) {\n+\t\tuint16_t acs_cap, acs_ctrl, acs_mask;\n+\t\toff = acs_cap_offset + DLB_PCI_ACS_CAP;\n+\t\tif (rte_pci_read_config(pdev, &acs_cap, 2, off) != 2)\n+\t\t\tacs_cap = 0;\n+\n+\t\toff = acs_cap_offset + DLB_PCI_ACS_CTRL;\n+\t\tif (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)\n+\t\t\tacs_ctrl = 0;\n+\n+\t\tacs_mask = DLB_PCI_ACS_SV | DLB_PCI_ACS_RR;\n+\t\tacs_mask |= (DLB_PCI_ACS_CR | DLB_PCI_ACS_UF);\n+\t\tacs_ctrl |= (acs_cap & acs_mask);\n+\n+\t\tif (rte_pci_write_config(pdev, &acs_ctrl, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\toff = acs_cap_offset + DLB_PCI_ACS_CTRL;\n+\t\tif (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)\n+\t\t\tacs_ctrl = 0;\n+\n+\t\tacs_mask = DLB_PCI_ACS_RR | DLB_PCI_ACS_CR | DLB_PCI_ACS_EC;\n+\t\tacs_ctrl &= ~acs_mask;\n+\n+\t\toff = acs_cap_offset + DLB_PCI_ACS_CTRL;\n+\t\tif (rte_pci_write_config(pdev, &acs_ctrl, 2, off) != 2) {\n+\t\t\tprintf(\"[%s()] failed to write pci config space at offset %d\\n\",\n+\t\t\t       __func__, (int)off);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*******************************/\n+/****** Driver management ******/\n+/*******************************/\n+\n+int\n+dlb_pf_init_driver_state(struct dlb_dev *dlb_dev)\n+{\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIR64B))\n+\t\tdlb_dev->enqueue_four = dlb_movdir64b;\n+\telse\n+\t\tdlb_dev->enqueue_four = dlb_movntdq;\n+\n+\t/* Initialize software state */\n+\trte_spinlock_init(&dlb_dev->resource_mutex);\n+\trte_spinlock_init(&dlb_dev->measurement_lock);\n+\n+\treturn 0;\n+}\n+\n+void\n+dlb_pf_init_hardware(struct dlb_dev *dlb_dev)\n+{\n+\tdlb_disable_dp_vasr_feature(&dlb_dev->hw);\n+\n+\tdlb_enable_excess_tokens_alarm(&dlb_dev->hw);\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0) {\n+\t\tdlb_hw_enable_sparse_ldb_cq_mode(&dlb_dev->hw);\n+\t\tdlb_hw_enable_sparse_dir_cq_mode(&dlb_dev->hw);\n+\t}\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0) {\n+\t\tdlb_hw_disable_pf_to_vf_isr_pend_err(&dlb_dev->hw);\n+\t\tdlb_hw_disable_vf_to_pf_isr_pend_err(&dlb_dev->hw);\n+\t}\n+}\ndiff --git a/drivers/event/dlb/pf/dlb_main.h b/drivers/event/dlb/pf/dlb_main.h\nnew file mode 100644\nindex 0000000..abe9c02\n--- /dev/null\n+++ b/drivers/event/dlb/pf/dlb_main.h\n@@ -0,0 +1,52 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_MAIN_H\n+#define __DLB_MAIN_H\n+\n+#include <rte_debug.h>\n+#include <rte_log.h>\n+#include <rte_spinlock.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#ifndef PAGE_SIZE\n+#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n+#endif\n+\n+#include \"base/dlb_hw_types.h\"\n+#include \"../dlb_user.h\"\n+\n+#define DLB_DEFAULT_UNREGISTER_TIMEOUT_S 5\n+\n+struct dlb_dev {\n+\tstruct rte_pci_device *pdev;\n+\tstruct dlb_hw hw;\n+\t/* struct list_head list; */\n+\tstruct device *dlb_device;\n+\t/* The enqueue_four function enqueues four HCWs (one cache-line worth)\n+\t * to the DLB, using whichever mechanism is supported by the platform\n+\t * on which this driver is running.\n+\t */\n+\tvoid (*enqueue_four)(void *qe4, void *pp_addr);\n+\tbool domain_reset_failed;\n+\t/* The resource mutex serializes access to driver data structures and\n+\t * hardware registers.\n+\t */\n+\trte_spinlock_t resource_mutex;\n+\trte_spinlock_t measurement_lock;\n+\tbool worker_launched;\n+\tu8 revision;\n+};\n+\n+struct dlb_dev *dlb_probe(struct rte_pci_device *pdev);\n+void dlb_reset_done(struct dlb_dev *dlb_dev);\n+\n+/* pf_ops */\n+int dlb_pf_init_driver_state(struct dlb_dev *dev);\n+void dlb_pf_free_driver_state(struct dlb_dev *dev);\n+void dlb_pf_init_hardware(struct dlb_dev *dev);\n+int dlb_pf_reset(struct dlb_dev *dlb_dev);\n+\n+#endif /* __DLB_MAIN_H */\ndiff --git a/drivers/event/dlb/pf/dlb_pf.c b/drivers/event/dlb/pf/dlb_pf.c\nnew file mode 100644\nindex 0000000..7fc85e9\n--- /dev/null\n+++ b/drivers/event/dlb/pf/dlb_pf.c\n@@ -0,0 +1,232 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <sys/mman.h>\n+#include <sys/fcntl.h>\n+#include <sys/time.h>\n+#include <errno.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+#include <rte_debug.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_devargs.h>\n+#include <rte_mbuf.h>\n+#include <rte_ring.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+#include <rte_malloc.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_memory.h>\n+#include <rte_string_fns.h>\n+\n+#include \"../dlb_priv.h\"\n+#include \"../dlb_iface.h\"\n+#include \"../dlb_inline_fns.h\"\n+#include \"dlb_main.h\"\n+#include \"base/dlb_hw_types.h\"\n+#include \"base/dlb_osdep.h\"\n+#include \"base/dlb_resource.h\"\n+\n+static void\n+dlb_pf_low_level_io_init(struct dlb_eventdev *dlb __rte_unused)\n+{\n+\tint i;\n+\n+\t/* Addresses will be initialized at port create */\n+\tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++) {\n+\t\t/* First directed ports */\n+\n+\t\t/* producer port */\n+\t\tdlb_port[i][DLB_DIR].pp_addr = NULL;\n+\n+\t\t/* popcount */\n+\t\tdlb_port[i][DLB_DIR].ldb_popcount = NULL;\n+\t\tdlb_port[i][DLB_DIR].dir_popcount = NULL;\n+\n+\t\t/* consumer queue */\n+\t\tdlb_port[i][DLB_DIR].cq_base = NULL;\n+\t\tdlb_port[i][DLB_DIR].mmaped = true;\n+\n+\t\t/* Now load balanced ports */\n+\n+\t\t/* producer port */\n+\t\tdlb_port[i][DLB_LDB].pp_addr = NULL;\n+\n+\t\t/* popcount */\n+\t\tdlb_port[i][DLB_LDB].ldb_popcount = NULL;\n+\t\tdlb_port[i][DLB_LDB].dir_popcount = NULL;\n+\n+\t\t/* consumer queue */\n+\t\tdlb_port[i][DLB_LDB].cq_base = NULL;\n+\t\tdlb_port[i][DLB_LDB].mmaped = true;\n+\t}\n+}\n+\n+static int\n+dlb_pf_open(struct dlb_hw_dev *handle, const char *name)\n+{\n+\tRTE_SET_USED(handle);\n+\tRTE_SET_USED(name);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_device_version(struct dlb_hw_dev *handle,\n+\t\t\t  uint8_t *revision)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\t*revision = dlb_dev->revision;\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_num_resources(struct dlb_hw_dev *handle,\n+\t\t\t struct dlb_get_num_resources_args *rsrcs)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\tdlb_hw_get_num_resources(&dlb_dev->hw, rsrcs);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_cq_poll_mode(struct dlb_hw_dev *handle,\n+\t\t\tenum dlb_cq_poll_modes *mode)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0)\n+\t\t*mode = DLB_CQ_POLL_MODE_SPARSE;\n+\telse\n+\t\t*mode = DLB_CQ_POLL_MODE_STD;\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb_pf_iface_fn_ptrs_init(void)\n+{\n+\tdlb_iface_low_level_io_init = dlb_pf_low_level_io_init;\n+\tdlb_iface_open = dlb_pf_open;\n+\tdlb_iface_get_device_version = dlb_pf_get_device_version;\n+\tdlb_iface_get_num_resources = dlb_pf_get_num_resources;\n+\tdlb_iface_get_cq_poll_mode = dlb_pf_get_cq_poll_mode;\n+}\n+\n+/* PCI DEV HOOKS */\n+static int\n+dlb_eventdev_pci_init(struct rte_eventdev *eventdev)\n+{\n+\tint ret = 0;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct dlb_devargs dlb_args = {\n+\t\t.socket_id = rte_socket_id(),\n+\t\t.max_num_events = DLB_MAX_NUM_LDB_CREDITS,\n+\t\t.num_dir_credits_override = -1,\n+\t\t.defer_sched = 0,\n+\t\t.num_atm_inflights = DLB_NUM_ATOMIC_INFLIGHTS_PER_QUEUE,\n+\t};\n+\tstruct dlb_eventdev *dlb;\n+\n+\tDLB_LOG_DBG(\"Enter with dev_id=%d socket_id=%d\",\n+\t\t    eventdev->data->dev_id, eventdev->data->socket_id);\n+\n+\tdlb_entry_points_init(eventdev);\n+\n+\tdlb_pf_iface_fn_ptrs_init();\n+\n+\tpci_dev = RTE_DEV_TO_PCI(eventdev->dev);\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tdlb = dlb_pmd_priv(eventdev); /* rte_zmalloc_socket mem */\n+\n+\t\t/* Probe the DLB PF layer */\n+\t\tdlb->qm_instance.pf_dev = dlb_probe(pci_dev);\n+\n+\t\tif (dlb->qm_instance.pf_dev == NULL) {\n+\t\t\tDLB_LOG_ERR(\"DLB PF Probe failed with error %d\\n\",\n+\t\t\t\t    rte_errno);\n+\t\t\tret = -rte_errno;\n+\t\t\tgoto dlb_probe_failed;\n+\t\t}\n+\n+\t\t/* Were we invoked with runtime parameters? */\n+\t\tif (pci_dev->device.devargs) {\n+\t\t\tret = dlb_parse_params(pci_dev->device.devargs->args,\n+\t\t\t\t\t       pci_dev->device.devargs->name,\n+\t\t\t\t\t       &dlb_args);\n+\t\t\tif (ret) {\n+\t\t\t\tDLB_LOG_ERR(\"PFPMD failed to parse args ret=%d, errno=%d\\n\",\n+\t\t\t\t\t    ret, rte_errno);\n+\t\t\t\tgoto dlb_probe_failed;\n+\t\t\t}\n+\t\t}\n+\n+\t\tret = dlb_primary_eventdev_probe(eventdev,\n+\t\t\t\t\t\t EVDEV_DLB_NAME_PMD_STR,\n+\t\t\t\t\t\t &dlb_args);\n+\t} else {\n+\t\tret = dlb_secondary_eventdev_probe(eventdev,\n+\t\t\t\t\t\t   EVDEV_DLB_NAME_PMD_STR);\n+\t}\n+\tif (ret)\n+\t\tgoto dlb_probe_failed;\n+\n+\tDLB_LOG_INFO(\"DLB PF Probe success\\n\");\n+\n+\treturn 0;\n+\n+dlb_probe_failed:\n+\n+\tDLB_LOG_INFO(\"DLB PF Probe failed, ret=%d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+#define EVENTDEV_INTEL_VENDOR_ID 0x8086\n+\n+static const struct rte_pci_id pci_id_dlb_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(EVENTDEV_INTEL_VENDOR_ID,\n+\t\t\t       DLB_PF_DEV_ID)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static int\n+event_dlb_pci_probe(struct rte_pci_driver *pci_drv,\n+\t\t    struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_probe_named(pci_drv, pci_dev,\n+\t\tsizeof(struct dlb_eventdev), dlb_eventdev_pci_init,\n+\t\tEVDEV_DLB_NAME_PMD_STR);\n+}\n+\n+static int\n+event_dlb_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_remove(pci_dev, NULL);\n+}\n+\n+static struct rte_pci_driver pci_eventdev_dlb_pmd = {\n+\t.id_table = pci_id_dlb_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = event_dlb_pci_probe,\n+\t.remove = event_dlb_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(event_dlb_pf, pci_eventdev_dlb_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(event_dlb_pf, pci_id_dlb_map);\n",
    "prefixes": [
        "v4",
        "06/22"
    ]
}