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{
    "id": 77489,
    "url": "http://patches.dpdk.org/api/patches/77489/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599851920-16802-8-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599851920-16802-8-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599851920-16802-8-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2020-09-11T19:18:25",
    "name": "[v4,07/22] event/dlb: add xstats",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "75f00043bfc9e8a287e65905df88b286a77ab17d",
    "submitter": {
        "id": 826,
        "url": "http://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599851920-16802-8-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 12163,
            "url": "http://patches.dpdk.org/api/series/12163/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12163",
            "date": "2020-09-11T19:18:18",
            "name": "Add DLB PMD",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/12163/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77489/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/77489/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B1797A04C1;\n\tFri, 11 Sep 2020 21:22:59 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E04841C1BA;\n\tFri, 11 Sep 2020 21:22:15 +0200 (CEST)",
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        ],
        "IronPort-SDR": [
            "\n cVqT/jAzf9HMWVSBFiU7oNcT13awZCbwmETRj/fZiUCC31kbiLg7SuSeJdDO/DwAvvzXr8Mt8x\n 6UXrcwkRe+1A==",
            "\n igW49sGdTM+U+UQoyyE0CxUYa66POL2NkITzo16tCXpRFIdcu5JdYa7/HFbPfZuu5kg4LcKoKf\n ytEqrVhp2HNQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9741\"; a=\"138352260\"",
            "E=Sophos;i=\"5.76,416,1592895600\"; d=\"scan'208\";a=\"138352260\"",
            "E=Sophos;i=\"5.76,416,1592895600\"; d=\"scan'208\";a=\"506375659\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com",
        "Date": "Fri, 11 Sep 2020 14:18:25 -0500",
        "Message-Id": "<1599851920-16802-8-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1599851920-16802-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<1599851920-16802-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4 07/22] event/dlb: add xstats",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add support for DLB xstats.  Perform initialization and add\nstandard xstats entry points\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb/dlb.c        |   23 +\n drivers/event/dlb/dlb_xstats.c | 1252 ++++++++++++++++++++++++++++++++++++++++\n drivers/event/dlb/meson.build  |    1 +\n 3 files changed, 1276 insertions(+)\n create mode 100644 drivers/event/dlb/dlb_xstats.c",
    "diff": "diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nindex e2acb61..f89edf2 100644\n--- a/drivers/event/dlb/dlb.c\n+++ b/drivers/event/dlb/dlb.c\n@@ -71,6 +71,17 @@ static struct rte_event_dev_info evdev_dlb_default_info = {\n struct process_local_port_data\n dlb_port[DLB_MAX_NUM_PORTS][NUM_DLB_PORT_TYPES];\n \n+uint32_t\n+dlb_get_queue_depth(struct dlb_eventdev *dlb,\n+\t\t    struct dlb_eventdev_queue *queue)\n+{\n+\t/* DUMMY FOR NOW So \"xstats\" patch compiles */\n+\tRTE_SET_USED(dlb);\n+\tRTE_SET_USED(queue);\n+\n+\treturn 0;\n+}\n+\n static int\n dlb_hw_query_resources(struct dlb_eventdev *dlb)\n {\n@@ -298,6 +309,11 @@ void\n dlb_entry_points_init(struct rte_eventdev *dev)\n {\n \tstatic struct rte_eventdev_ops dlb_eventdev_entry_ops = {\n+\t\t.dump             = dlb_eventdev_dump,\n+\t\t.xstats_get       = dlb_eventdev_xstats_get,\n+\t\t.xstats_get_names = dlb_eventdev_xstats_get_names,\n+\t\t.xstats_get_by_name = dlb_eventdev_xstats_get_by_name,\n+\t\t.xstats_reset\t    = dlb_eventdev_xstats_reset,\n \t};\n \n \t/* Expose PMD's eventdev interface */\n@@ -356,6 +372,13 @@ dlb_primary_eventdev_probe(struct rte_eventdev *dev,\n \t\treturn err;\n \t}\n \n+\t/* Complete xtstats runtime initialization */\n+\terr = dlb_xstats_init(dlb);\n+\tif (err) {\n+\t\tDLB_LOG_ERR(\"dlb: failed to init xstats, err=%d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n \t/* Initialize each port's token pop mode */\n \tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++)\n \t\tdlb->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;\ndiff --git a/drivers/event/dlb/dlb_xstats.c b/drivers/event/dlb/dlb_xstats.c\nnew file mode 100644\nindex 0000000..4d01cc0\n--- /dev/null\n+++ b/drivers/event/dlb/dlb_xstats.c\n@@ -0,0 +1,1252 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <sys/mman.h>\n+#include <sys/fcntl.h>\n+#include <errno.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+#include <rte_debug.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_mbuf.h>\n+#include <rte_ring.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+#include <rte_malloc.h>\n+#include <rte_cycles.h>\n+#include <rte_io.h>\n+#include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+\n+#include \"dlb_priv.h\"\n+#include \"dlb_inline_fns.h\"\n+\n+enum dlb_xstats_type {\n+\t/* common to device and port */\n+\trx_ok,\t\t\t\t/**< Receive an event */\n+\trx_drop,                        /**< Error bit set in received QE */\n+\trx_interrupt_wait,\t\t/**< Wait on an interrupt */\n+\trx_umonitor_umwait,\t\t/**< Block using umwait */\n+\ttx_ok,\t\t\t\t/**< Transmit an event */\n+\ttotal_polls,\t\t\t/**< Call dequeue_burst */\n+\tzero_polls,\t\t\t/**< Call dequeue burst and return 0 */\n+\ttx_nospc_ldb_hw_credits,\t/**< Insufficient LDB h/w credits */\n+\ttx_nospc_dir_hw_credits,\t/**< Insufficient DIR h/w credits */\n+\ttx_nospc_inflight_max,\t\t/**< Reach the new_event_threshold */\n+\ttx_nospc_new_event_limit,\t/**< Insufficient s/w credits */\n+\ttx_nospc_inflight_credits,\t/**< Port has too few s/w credits */\n+\t/* device specific */\n+\tnb_events_limit,\t\t/**< Maximum num of events */\n+\tinflight_events,\t\t/**< Current num events outstanding */\n+\tldb_pool_size,\t\t\t/**< Num load balanced credits */\n+\tdir_pool_size,\t\t\t/**< Num directed credits */\n+\t/* port specific */\n+\ttx_new,\t\t\t\t/**< Send an OP_NEW event */\n+\ttx_fwd,\t\t\t\t/**< Send an OP_FORWARD event */\n+\ttx_rel,\t\t\t\t/**< Send an OP_RELEASE event */\n+\ttx_implicit_rel,\t\t/**< Issue an implicit event release */\n+\ttx_sched_ordered,\t\t/**< Send a SCHED_TYPE_ORDERED event */\n+\ttx_sched_unordered,\t\t/**< Send a SCHED_TYPE_PARALLEL event */\n+\ttx_sched_atomic,\t\t/**< Send a SCHED_TYPE_ATOMIC event */\n+\ttx_sched_directed,\t\t/**< Send a directed event */\n+\ttx_invalid,                     /**< Send an event with an invalid op */\n+\toutstanding_releases,\t\t/**< # of releases a port owes */\n+\tmax_outstanding_releases,\t/**< max # of releases a port can owe */\n+\trx_sched_ordered,\t\t/**< Dequeue an ordered event */\n+\trx_sched_unordered,\t\t/**< Dequeue an unordered event */\n+\trx_sched_atomic,\t\t/**< Dequeue an atomic event */\n+\trx_sched_directed,\t\t/**< Dequeue an directed event */\n+\trx_sched_invalid,               /**< Dequeue event sched type invalid */\n+\t/* common to port and queue */\n+\tis_configured,\t\t\t/**< Port is configured */\n+\tis_load_balanced,\t\t/**< Port is LDB */\n+\thw_id,\t\t\t\t/**< Hardware ID */\n+\t/* queue specific */\n+\tnum_links,\t\t\t/**< Number of ports linked */\n+\tsched_type,\t\t\t/**< Queue sched type */\n+\tenq_ok,\t\t\t\t/**< # events enqueued to the queue */\n+\tcurrent_depth\t\t\t/**< Current queue depth */\n+};\n+\n+typedef uint64_t (*dlb_xstats_fn)(struct dlb_eventdev *dlb,\n+\t\tuint16_t obj_idx, /* port or queue id */\n+\t\tenum dlb_xstats_type stat, int extra_arg);\n+\n+enum dlb_xstats_fn_type {\n+\tDLB_XSTATS_FN_DEV,\n+\tDLB_XSTATS_FN_PORT,\n+\tDLB_XSTATS_FN_QUEUE\n+};\n+\n+struct dlb_xstats_entry {\n+\tstruct rte_event_dev_xstats_name name;\n+\tuint64_t reset_value; /* an offset to be taken away to emulate resets */\n+\tenum dlb_xstats_fn_type fn_id;\n+\tenum dlb_xstats_type stat;\n+\tenum rte_event_dev_xstats_mode mode;\n+\tint extra_arg;\n+\tuint16_t obj_idx;\n+\tuint8_t reset_allowed; /* when set, this value can be reset */\n+};\n+\n+/* Some device stats are simply a summation of the corresponding port values */\n+static uint64_t\n+dlb_device_traffic_stat_get(struct dlb_eventdev *dlb, int which_stat)\n+{\n+\tint i;\n+\tuint64_t val = 0;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++) {\n+\t\tstruct dlb_eventdev_port *port = &dlb->ev_ports[i];\n+\n+\t\tif (!port->setup_done)\n+\t\t\tcontinue;\n+\n+\t\tswitch (which_stat) {\n+\t\tcase rx_ok:\n+\t\t\tval += port->stats.traffic.rx_ok;\n+\t\t\tbreak;\n+\t\tcase rx_drop:\n+\t\t\tval += port->stats.traffic.rx_drop;\n+\t\t\tbreak;\n+\t\tcase rx_interrupt_wait:\n+\t\t\tval += port->stats.traffic.rx_interrupt_wait;\n+\t\t\tbreak;\n+\t\tcase rx_umonitor_umwait:\n+\t\t\tval += port->stats.traffic.rx_umonitor_umwait;\n+\t\t\tbreak;\n+\t\tcase tx_ok:\n+\t\t\tval += port->stats.traffic.tx_ok;\n+\t\t\tbreak;\n+\t\tcase total_polls:\n+\t\t\tval += port->stats.traffic.total_polls;\n+\t\t\tbreak;\n+\t\tcase zero_polls:\n+\t\t\tval += port->stats.traffic.zero_polls;\n+\t\t\tbreak;\n+\t\tcase tx_nospc_ldb_hw_credits:\n+\t\t\tval += port->stats.traffic.tx_nospc_ldb_hw_credits;\n+\t\t\tbreak;\n+\t\tcase tx_nospc_dir_hw_credits:\n+\t\t\tval += port->stats.traffic.tx_nospc_dir_hw_credits;\n+\t\t\tbreak;\n+\t\tcase tx_nospc_inflight_max:\n+\t\t\tval += port->stats.traffic.tx_nospc_inflight_max;\n+\t\t\tbreak;\n+\t\tcase tx_nospc_new_event_limit:\n+\t\t\tval += port->stats.traffic.tx_nospc_new_event_limit;\n+\t\t\tbreak;\n+\t\tcase tx_nospc_inflight_credits:\n+\t\t\tval += port->stats.traffic.tx_nospc_inflight_credits;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\treturn val;\n+}\n+\n+static uint64_t\n+get_dev_stat(struct dlb_eventdev *dlb, uint16_t obj_idx __rte_unused,\n+\t     enum dlb_xstats_type type, int extra_arg __rte_unused)\n+{\n+\tswitch (type) {\n+\tcase rx_ok:\n+\tcase rx_drop:\n+\tcase rx_interrupt_wait:\n+\tcase rx_umonitor_umwait:\n+\tcase tx_ok:\n+\tcase total_polls:\n+\tcase zero_polls:\n+\tcase tx_nospc_ldb_hw_credits:\n+\tcase tx_nospc_dir_hw_credits:\n+\tcase tx_nospc_inflight_max:\n+\tcase tx_nospc_new_event_limit:\n+\tcase tx_nospc_inflight_credits:\n+\t\treturn dlb_device_traffic_stat_get(dlb, type);\n+\tcase nb_events_limit:\n+\t\treturn dlb->new_event_limit;\n+\tcase inflight_events:\n+\t\treturn __atomic_load_n(&dlb->inflights, __ATOMIC_SEQ_CST);\n+\tcase ldb_pool_size:\n+\t\treturn dlb->num_ldb_credits;\n+\tcase dir_pool_size:\n+\t\treturn dlb->num_dir_credits;\n+\tdefault: return -1;\n+\t}\n+}\n+\n+static uint64_t\n+get_port_stat(struct dlb_eventdev *dlb, uint16_t obj_idx,\n+\t      enum dlb_xstats_type type, int extra_arg __rte_unused)\n+{\n+\tstruct dlb_eventdev_port *ev_port = &dlb->ev_ports[obj_idx];\n+\n+\tswitch (type) {\n+\tcase rx_ok: return ev_port->stats.traffic.rx_ok;\n+\n+\tcase rx_drop: return ev_port->stats.traffic.rx_drop;\n+\n+\tcase rx_interrupt_wait: return ev_port->stats.traffic.rx_interrupt_wait;\n+\n+\tcase rx_umonitor_umwait:\n+\t\treturn ev_port->stats.traffic.rx_umonitor_umwait;\n+\n+\tcase tx_ok: return ev_port->stats.traffic.tx_ok;\n+\n+\tcase total_polls: return ev_port->stats.traffic.total_polls;\n+\n+\tcase zero_polls: return ev_port->stats.traffic.zero_polls;\n+\n+\tcase tx_nospc_ldb_hw_credits:\n+\t\treturn ev_port->stats.traffic.tx_nospc_ldb_hw_credits;\n+\n+\tcase tx_nospc_dir_hw_credits:\n+\t\treturn ev_port->stats.traffic.tx_nospc_dir_hw_credits;\n+\n+\tcase tx_nospc_inflight_max:\n+\t\treturn ev_port->stats.traffic.tx_nospc_inflight_max;\n+\n+\tcase tx_nospc_new_event_limit:\n+\t\treturn ev_port->stats.traffic.tx_nospc_new_event_limit;\n+\n+\tcase tx_nospc_inflight_credits:\n+\t\treturn ev_port->stats.traffic.tx_nospc_inflight_credits;\n+\n+\tcase is_configured: return ev_port->setup_done;\n+\n+\tcase is_load_balanced: return !ev_port->qm_port.is_directed;\n+\n+\tcase hw_id: return ev_port->qm_port.id;\n+\n+\tcase tx_new: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_NEW];\n+\n+\tcase tx_fwd: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_FORWARD];\n+\n+\tcase tx_rel: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_RELEASE];\n+\n+\tcase tx_implicit_rel: return ev_port->stats.tx_implicit_rel;\n+\n+\tcase tx_sched_ordered:\n+\t\treturn ev_port->stats.tx_sched_cnt[DLB_SCHED_ORDERED];\n+\n+\tcase tx_sched_unordered:\n+\t\treturn ev_port->stats.tx_sched_cnt[DLB_SCHED_UNORDERED];\n+\n+\tcase tx_sched_atomic:\n+\t\treturn ev_port->stats.tx_sched_cnt[DLB_SCHED_ATOMIC];\n+\n+\tcase tx_sched_directed:\n+\t\treturn ev_port->stats.tx_sched_cnt[DLB_SCHED_DIRECTED];\n+\n+\tcase tx_invalid: return ev_port->stats.tx_invalid;\n+\n+\tcase outstanding_releases: return ev_port->outstanding_releases;\n+\n+\tcase max_outstanding_releases:\n+\t\treturn DLB_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\n+\tcase rx_sched_ordered:\n+\t\treturn ev_port->stats.rx_sched_cnt[DLB_SCHED_ORDERED];\n+\n+\tcase rx_sched_unordered:\n+\t\treturn ev_port->stats.rx_sched_cnt[DLB_SCHED_UNORDERED];\n+\n+\tcase rx_sched_atomic:\n+\t\treturn ev_port->stats.rx_sched_cnt[DLB_SCHED_ATOMIC];\n+\n+\tcase rx_sched_directed:\n+\t\treturn ev_port->stats.rx_sched_cnt[DLB_SCHED_DIRECTED];\n+\n+\tcase rx_sched_invalid: return ev_port->stats.rx_sched_invalid;\n+\n+\tdefault: return -1;\n+\t}\n+}\n+\n+static uint64_t\n+get_queue_stat(struct dlb_eventdev *dlb, uint16_t obj_idx,\n+\t       enum dlb_xstats_type type, int extra_arg __rte_unused)\n+{\n+\tstruct dlb_eventdev_queue *ev_queue = &dlb->ev_queues[obj_idx];\n+\n+\tswitch (type) {\n+\tcase is_configured: return ev_queue->setup_done;\n+\n+\tcase is_load_balanced: return !ev_queue->qm_queue.is_directed;\n+\n+\tcase hw_id: return ev_queue->qm_queue.id;\n+\n+\tcase num_links: return ev_queue->num_links;\n+\n+\tcase sched_type: return ev_queue->qm_queue.sched_type;\n+\n+\tcase enq_ok:\n+\t{\n+\t\tint port_count = 0;\n+\t\tuint64_t enq_ok_tally = 0;\n+\n+\t\tev_queue->enq_ok = 0;\n+\t\tfor (port_count = 0; port_count < DLB_MAX_NUM_PORTS;\n+\t\t     port_count++) {\n+\t\t\tstruct dlb_eventdev_port *ev_port =\n+\t\t\t\t&dlb->ev_ports[port_count];\n+\t\t\tenq_ok_tally += ev_port->stats.enq_ok[ev_queue->id];\n+\t\t}\n+\t\tev_queue->enq_ok = enq_ok_tally;\n+\t\treturn ev_queue->enq_ok;\n+\t}\n+\n+\tcase current_depth: return dlb_get_queue_depth(dlb, ev_queue);\n+\n+\tdefault: return -1;\n+\t}\n+}\n+\n+int\n+dlb_xstats_init(struct dlb_eventdev *dlb)\n+{\n+\t/*\n+\t * define the stats names and types. Used to build up the device\n+\t * xstats array\n+\t * There are multiple set of stats:\n+\t *   - device-level,\n+\t *   - per-port,\n+\t *   - per-qid,\n+\t *\n+\t * For each of these sets, we have three parallel arrays, one for the\n+\t * names, the other for the stat type parameter to be passed in the fn\n+\t * call to get that stat. The third array allows resetting or not.\n+\t * All these arrays must be kept in sync\n+\t */\n+\tstatic const char * const dev_stats[] = {\n+\t\t\"rx_ok\",\n+\t\t\"rx_drop\",\n+\t\t\"rx_interrupt_wait\",\n+\t\t\"rx_umonitor_umwait\",\n+\t\t\"tx_ok\",\n+\t\t\"total_polls\",\n+\t\t\"zero_polls\",\n+\t\t\"tx_nospc_ldb_hw_credits\",\n+\t\t\"tx_nospc_dir_hw_credits\",\n+\t\t\"tx_nospc_inflight_max\",\n+\t\t\"tx_nospc_new_event_limit\",\n+\t\t\"tx_nospc_inflight_credits\",\n+\t\t\"nb_events_limit\",\n+\t\t\"inflight_events\",\n+\t\t\"ldb_pool_size\",\n+\t\t\"dir_pool_size\",\n+\t};\n+\tstatic const enum dlb_xstats_type dev_types[] = {\n+\t\trx_ok,\n+\t\trx_drop,\n+\t\trx_interrupt_wait,\n+\t\trx_umonitor_umwait,\n+\t\ttx_ok,\n+\t\ttotal_polls,\n+\t\tzero_polls,\n+\t\ttx_nospc_ldb_hw_credits,\n+\t\ttx_nospc_dir_hw_credits,\n+\t\ttx_nospc_inflight_max,\n+\t\ttx_nospc_new_event_limit,\n+\t\ttx_nospc_inflight_credits,\n+\t\tnb_events_limit,\n+\t\tinflight_events,\n+\t\tldb_pool_size,\n+\t\tdir_pool_size,\n+\t};\n+\t/* Note: generated device stats are not allowed to be reset. */\n+\tstatic const uint8_t dev_reset_allowed[] = {\n+\t\t0, /* rx_ok */\n+\t\t0, /* rx_drop */\n+\t\t0, /* rx_interrupt_wait */\n+\t\t0, /* rx_umonitor_umwait */\n+\t\t0, /* tx_ok */\n+\t\t0, /* total_polls */\n+\t\t0, /* zero_polls */\n+\t\t0, /* tx_nospc_ldb_hw_credits */\n+\t\t0, /* tx_nospc_dir_hw_credits */\n+\t\t0, /* tx_nospc_inflight_max */\n+\t\t0, /* tx_nospc_new_event_limit */\n+\t\t0, /* tx_nospc_inflight_credits */\n+\t\t0, /* nb_events_limit */\n+\t\t0, /* inflight_events */\n+\t\t0, /* ldb_pool_size */\n+\t\t0, /* dir_pool_size */\n+\t};\n+\tstatic const char * const port_stats[] = {\n+\t\t\"is_configured\",\n+\t\t\"is_load_balanced\",\n+\t\t\"hw_id\",\n+\t\t\"rx_ok\",\n+\t\t\"rx_drop\",\n+\t\t\"rx_interrupt_wait\",\n+\t\t\"rx_umonitor_umwait\",\n+\t\t\"tx_ok\",\n+\t\t\"total_polls\",\n+\t\t\"zero_polls\",\n+\t\t\"tx_nospc_ldb_hw_credits\",\n+\t\t\"tx_nospc_dir_hw_credits\",\n+\t\t\"tx_nospc_inflight_max\",\n+\t\t\"tx_nospc_new_event_limit\",\n+\t\t\"tx_nospc_inflight_credits\",\n+\t\t\"tx_new\",\n+\t\t\"tx_fwd\",\n+\t\t\"tx_rel\",\n+\t\t\"tx_implicit_rel\",\n+\t\t\"tx_sched_ordered\",\n+\t\t\"tx_sched_unordered\",\n+\t\t\"tx_sched_atomic\",\n+\t\t\"tx_sched_directed\",\n+\t\t\"tx_invalid\",\n+\t\t\"outstanding_releases\",\n+\t\t\"max_outstanding_releases\",\n+\t\t\"rx_sched_ordered\",\n+\t\t\"rx_sched_unordered\",\n+\t\t\"rx_sched_atomic\",\n+\t\t\"rx_sched_directed\",\n+\t\t\"rx_sched_invalid\"\n+\t};\n+\tstatic const enum dlb_xstats_type port_types[] = {\n+\t\tis_configured,\n+\t\tis_load_balanced,\n+\t\thw_id,\n+\t\trx_ok,\n+\t\trx_drop,\n+\t\trx_interrupt_wait,\n+\t\trx_umonitor_umwait,\n+\t\ttx_ok,\n+\t\ttotal_polls,\n+\t\tzero_polls,\n+\t\ttx_nospc_ldb_hw_credits,\n+\t\ttx_nospc_dir_hw_credits,\n+\t\ttx_nospc_inflight_max,\n+\t\ttx_nospc_new_event_limit,\n+\t\ttx_nospc_inflight_credits,\n+\t\ttx_new,\n+\t\ttx_fwd,\n+\t\ttx_rel,\n+\t\ttx_implicit_rel,\n+\t\ttx_sched_ordered,\n+\t\ttx_sched_unordered,\n+\t\ttx_sched_atomic,\n+\t\ttx_sched_directed,\n+\t\ttx_invalid,\n+\t\toutstanding_releases,\n+\t\tmax_outstanding_releases,\n+\t\trx_sched_ordered,\n+\t\trx_sched_unordered,\n+\t\trx_sched_atomic,\n+\t\trx_sched_directed,\n+\t\trx_sched_invalid\n+\t};\n+\tstatic const uint8_t port_reset_allowed[] = {\n+\t\t0, /* is_configured */\n+\t\t0, /* is_load_balanced */\n+\t\t0, /* hw_id */\n+\t\t1, /* rx_ok */\n+\t\t1, /* rx_drop */\n+\t\t1, /* rx_interrupt_wait */\n+\t\t1, /* rx_umonitor_umwait */\n+\t\t1, /* tx_ok */\n+\t\t1, /* total_polls */\n+\t\t1, /* zero_polls */\n+\t\t1, /* tx_nospc_ldb_hw_credits */\n+\t\t1, /* tx_nospc_dir_hw_credits */\n+\t\t1, /* tx_nospc_inflight_max */\n+\t\t1, /* tx_nospc_new_event_limit */\n+\t\t1, /* tx_nospc_inflight_credits */\n+\t\t1, /* tx_new */\n+\t\t1, /* tx_fwd */\n+\t\t1, /* tx_rel */\n+\t\t1, /* tx_implicit_rel */\n+\t\t1, /* tx_sched_ordered */\n+\t\t1, /* tx_sched_unordered */\n+\t\t1, /* tx_sched_atomic */\n+\t\t1, /* tx_sched_directed */\n+\t\t1, /* tx_invalid */\n+\t\t0, /* outstanding_releases */\n+\t\t0, /* max_outstanding_releases */\n+\t\t1, /* rx_sched_ordered */\n+\t\t1, /* rx_sched_unordered */\n+\t\t1, /* rx_sched_atomic */\n+\t\t1, /* rx_sched_directed */\n+\t\t1  /* rx_sched_invalid */\n+\t};\n+\n+\t/* QID specific stats */\n+\tstatic const char * const qid_stats[] = {\n+\t\t\"is_configured\",\n+\t\t\"is_load_balanced\",\n+\t\t\"hw_id\",\n+\t\t\"num_links\",\n+\t\t\"sched_type\",\n+\t\t\"enq_ok\",\n+\t\t\"current_depth\",\n+\t};\n+\tstatic const enum dlb_xstats_type qid_types[] = {\n+\t\tis_configured,\n+\t\tis_load_balanced,\n+\t\thw_id,\n+\t\tnum_links,\n+\t\tsched_type,\n+\t\tenq_ok,\n+\t\tcurrent_depth,\n+\t};\n+\tstatic const uint8_t qid_reset_allowed[] = {\n+\t\t0, /* is_configured */\n+\t\t0, /* is_load_balanced */\n+\t\t0, /* hw_id */\n+\t\t0, /* num_links */\n+\t\t0, /* sched_type */\n+\t\t1, /* enq_ok */\n+\t\t0, /* current_depth */\n+\t};\n+\n+\t/* ---- end of stat definitions ---- */\n+\n+\t/* check sizes, since a missed comma can lead to strings being\n+\t * joined by the compiler.\n+\t */\n+\tRTE_BUILD_BUG_ON(RTE_DIM(dev_stats) != RTE_DIM(dev_types));\n+\tRTE_BUILD_BUG_ON(RTE_DIM(port_stats) != RTE_DIM(port_types));\n+\tRTE_BUILD_BUG_ON(RTE_DIM(qid_stats) != RTE_DIM(qid_types));\n+\n+\tRTE_BUILD_BUG_ON(RTE_DIM(dev_stats) != RTE_DIM(dev_reset_allowed));\n+\tRTE_BUILD_BUG_ON(RTE_DIM(port_stats) != RTE_DIM(port_reset_allowed));\n+\tRTE_BUILD_BUG_ON(RTE_DIM(qid_stats) != RTE_DIM(qid_reset_allowed));\n+\n+\t/* other vars */\n+\tconst unsigned int count = RTE_DIM(dev_stats) +\n+\t\t\tDLB_MAX_NUM_PORTS * RTE_DIM(port_stats) +\n+\t\t\tDLB_MAX_NUM_QUEUES * RTE_DIM(qid_stats);\n+\tunsigned int i, port, qid, stat_id = 0;\n+\n+\tdlb->xstats = rte_zmalloc_socket(NULL,\n+\t\t\t\t\t sizeof(dlb->xstats[0]) * count, 0,\n+\t\t\t\t\t dlb->qm_instance.info.socket_id);\n+\tif (dlb->xstats == NULL)\n+\t\treturn -ENOMEM;\n+\n+#define sname dlb->xstats[stat_id].name.name\n+\tfor (i = 0; i < RTE_DIM(dev_stats); i++, stat_id++) {\n+\t\tdlb->xstats[stat_id] = (struct dlb_xstats_entry) {\n+\t\t\t.fn_id = DLB_XSTATS_FN_DEV,\n+\t\t\t.stat = dev_types[i],\n+\t\t\t.mode = RTE_EVENT_DEV_XSTATS_DEVICE,\n+\t\t\t.reset_allowed = dev_reset_allowed[i],\n+\t\t};\n+\t\tsnprintf(sname, sizeof(sname), \"dev_%s\", dev_stats[i]);\n+\t}\n+\tdlb->xstats_count_mode_dev = stat_id;\n+\n+\tfor (port = 0; port < DLB_MAX_NUM_PORTS; port++) {\n+\t\tuint32_t count_offset = stat_id;\n+\n+\t\tdlb->xstats_offset_for_port[port] = stat_id;\n+\n+\t\tfor (i = 0; i < RTE_DIM(port_stats); i++, stat_id++) {\n+\t\t\tdlb->xstats[stat_id] = (struct dlb_xstats_entry){\n+\t\t\t\t.fn_id = DLB_XSTATS_FN_PORT,\n+\t\t\t\t.obj_idx = port,\n+\t\t\t\t.stat = port_types[i],\n+\t\t\t\t.mode = RTE_EVENT_DEV_XSTATS_PORT,\n+\t\t\t\t.reset_allowed = port_reset_allowed[i],\n+\t\t\t};\n+\t\t\tsnprintf(sname, sizeof(sname), \"port_%u_%s\",\n+\t\t\t\t port, port_stats[i]);\n+\t\t}\n+\n+\t\tdlb->xstats_count_per_port[port] = stat_id - count_offset;\n+\t}\n+\n+\tdlb->xstats_count_mode_port = stat_id - dlb->xstats_count_mode_dev;\n+\n+\tfor (qid = 0; qid < DLB_MAX_NUM_QUEUES; qid++) {\n+\t\tuint32_t count_offset = stat_id;\n+\n+\t\tdlb->xstats_offset_for_qid[qid] = stat_id;\n+\n+\t\tfor (i = 0; i < RTE_DIM(qid_stats); i++, stat_id++) {\n+\t\t\tdlb->xstats[stat_id] = (struct dlb_xstats_entry){\n+\t\t\t\t.fn_id = DLB_XSTATS_FN_QUEUE,\n+\t\t\t\t.obj_idx = qid,\n+\t\t\t\t.stat = qid_types[i],\n+\t\t\t\t.mode = RTE_EVENT_DEV_XSTATS_QUEUE,\n+\t\t\t\t.reset_allowed = qid_reset_allowed[i],\n+\t\t\t};\n+\t\t\tsnprintf(sname, sizeof(sname), \"qid_%u_%s\",\n+\t\t\t\t qid, qid_stats[i]);\n+\t\t}\n+\n+\t\tdlb->xstats_count_per_qid[qid] = stat_id - count_offset;\n+\t}\n+\n+\tdlb->xstats_count_mode_queue = stat_id -\n+\t\t(dlb->xstats_count_mode_dev + dlb->xstats_count_mode_port);\n+#undef sname\n+\n+\tdlb->xstats_count = stat_id;\n+\n+\treturn 0;\n+}\n+\n+void\n+dlb_xstats_uninit(struct dlb_eventdev *dlb)\n+{\n+\trte_free(dlb->xstats);\n+\tdlb->xstats_count = 0;\n+}\n+\n+int\n+dlb_eventdev_xstats_get_names(const struct rte_eventdev *dev,\n+\t\tenum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\tstruct rte_event_dev_xstats_name *xstats_names,\n+\t\tunsigned int *ids, unsigned int size)\n+{\n+\tconst struct dlb_eventdev *dlb = dlb_pmd_priv(dev);\n+\tunsigned int i;\n+\tunsigned int xidx = 0;\n+\n+\tRTE_SET_USED(mode);\n+\tRTE_SET_USED(queue_port_id);\n+\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\txstats_mode_count = dlb->xstats_count_mode_dev;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= DLB_MAX_NUM_PORTS)\n+\t\t\tbreak;\n+\t\txstats_mode_count = dlb->xstats_count_per_port[queue_port_id];\n+\t\tstart_offset = dlb->xstats_offset_for_port[queue_port_id];\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+#if (DLB_MAX_NUM_QUEUES <= 255) /* max 8 bit value */\n+\t\tif (queue_port_id >= DLB_MAX_NUM_QUEUES)\n+\t\t\tbreak;\n+#endif\n+\t\txstats_mode_count = dlb->xstats_count_per_qid[queue_port_id];\n+\t\tstart_offset = dlb->xstats_offset_for_qid[queue_port_id];\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t};\n+\n+\tif (xstats_mode_count > size || !ids || !xstats_names)\n+\t\treturn xstats_mode_count;\n+\n+\tfor (i = 0; i < dlb->xstats_count && xidx < size; i++) {\n+\t\tif (dlb->xstats[i].mode != mode)\n+\t\t\tcontinue;\n+\n+\t\tif (mode != RTE_EVENT_DEV_XSTATS_DEVICE &&\n+\t\t    queue_port_id != dlb->xstats[i].obj_idx)\n+\t\t\tcontinue;\n+\n+\t\txstats_names[xidx] = dlb->xstats[i].name;\n+\t\tif (ids)\n+\t\t\tids[xidx] = start_offset + xidx;\n+\t\txidx++;\n+\t}\n+\treturn xidx;\n+}\n+\n+static int\n+dlb_xstats_update(struct dlb_eventdev *dlb,\n+\t\tenum rte_event_dev_xstats_mode mode,\n+\t\tuint8_t queue_port_id, const unsigned int ids[],\n+\t\tuint64_t values[], unsigned int n, const uint32_t reset)\n+{\n+\tunsigned int i;\n+\tunsigned int xidx = 0;\n+\n+\tRTE_SET_USED(mode);\n+\tRTE_SET_USED(queue_port_id);\n+\n+\tuint32_t xstats_mode_count = 0;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\txstats_mode_count = dlb->xstats_count_mode_dev;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= DLB_MAX_NUM_PORTS)\n+\t\t\tgoto invalid_value;\n+\t\txstats_mode_count = dlb->xstats_count_per_port[queue_port_id];\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+#if (DLB_MAX_NUM_QUEUES <= 255) /* max 8 bit value */\n+\t\tif (queue_port_id >= DLB_MAX_NUM_QUEUES)\n+\t\t\tgoto invalid_value;\n+#endif\n+\t\txstats_mode_count = dlb->xstats_count_per_qid[queue_port_id];\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto invalid_value;\n+\t};\n+\n+\tfor (i = 0; i < n && xidx < xstats_mode_count; i++) {\n+\t\tstruct dlb_xstats_entry *xs = &dlb->xstats[ids[i]];\n+\t\tdlb_xstats_fn fn;\n+\n+\t\tif (ids[i] > dlb->xstats_count || xs->mode != mode)\n+\t\t\tcontinue;\n+\n+\t\tif (mode != RTE_EVENT_DEV_XSTATS_DEVICE &&\n+\t\t    queue_port_id != xs->obj_idx)\n+\t\t\tcontinue;\n+\n+\t\tswitch (xs->fn_id) {\n+\t\tcase DLB_XSTATS_FN_DEV:\n+\t\t\tfn = get_dev_stat;\n+\t\t\tbreak;\n+\t\tcase DLB_XSTATS_FN_PORT:\n+\t\t\tfn = get_port_stat;\n+\t\t\tbreak;\n+\t\tcase DLB_XSTATS_FN_QUEUE:\n+\t\t\tfn = get_queue_stat;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDLB_LOG_ERR(\"Unexpected xstat fn_id %d\\n\",\n+\t\t\t\t     xs->fn_id);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tuint64_t val = fn(dlb, xs->obj_idx, xs->stat,\n+\t\t\t\t  xs->extra_arg) - xs->reset_value;\n+\n+\t\tif (values)\n+\t\t\tvalues[xidx] = val;\n+\n+\t\tif (xs->reset_allowed && reset)\n+\t\t\txs->reset_value += val;\n+\n+\t\txidx++;\n+\t}\n+\n+\treturn xidx;\n+\n+invalid_value:\n+\treturn -EINVAL;\n+}\n+\n+int\n+dlb_eventdev_xstats_get(const struct rte_eventdev *dev,\n+\t\tenum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\tconst unsigned int ids[], uint64_t values[], unsigned int n)\n+{\n+\tstruct dlb_eventdev *dlb = dlb_pmd_priv(dev);\n+\tconst uint32_t reset = 0;\n+\n+\treturn dlb_xstats_update(dlb, mode, queue_port_id, ids, values, n,\n+\t\t\t\t  reset);\n+}\n+\n+uint64_t\n+dlb_eventdev_xstats_get_by_name(const struct rte_eventdev *dev,\n+\t\t\t\tconst char *name, unsigned int *id)\n+{\n+\tstruct dlb_eventdev *dlb = dlb_pmd_priv(dev);\n+\tunsigned int i;\n+\tdlb_xstats_fn fn;\n+\n+\tfor (i = 0; i < dlb->xstats_count; i++) {\n+\t\tstruct dlb_xstats_entry *xs = &dlb->xstats[i];\n+\n+\t\tif (strncmp(xs->name.name, name,\n+\t\t\t    RTE_EVENT_DEV_XSTATS_NAME_SIZE) == 0){\n+\t\t\tif (id != NULL)\n+\t\t\t\t*id = i;\n+\n+\t\t\tswitch (xs->fn_id) {\n+\t\t\tcase DLB_XSTATS_FN_DEV:\n+\t\t\t\tfn = get_dev_stat;\n+\t\t\t\tbreak;\n+\t\t\tcase DLB_XSTATS_FN_PORT:\n+\t\t\t\tfn = get_port_stat;\n+\t\t\t\tbreak;\n+\t\t\tcase DLB_XSTATS_FN_QUEUE:\n+\t\t\t\tfn = get_queue_stat;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tDLB_LOG_ERR(\"Unexpected xstat fn_id %d\\n\",\n+\t\t\t\t\t    xs->fn_id);\n+\t\t\t\treturn (uint64_t)-1;\n+\t\t\t}\n+\n+\t\t\treturn fn(dlb, xs->obj_idx, xs->stat,\n+\t\t\t\t  xs->extra_arg) - xs->reset_value;\n+\t\t}\n+\t}\n+\tif (id != NULL)\n+\t\t*id = (uint32_t)-1;\n+\treturn (uint64_t)-1;\n+}\n+\n+static void\n+dlb_xstats_reset_range(struct dlb_eventdev *dlb, uint32_t start,\n+\t\t       uint32_t num)\n+{\n+\tuint32_t i;\n+\tdlb_xstats_fn fn;\n+\n+\tfor (i = start; i < start + num; i++) {\n+\t\tstruct dlb_xstats_entry *xs = &dlb->xstats[i];\n+\n+\t\tif (!xs->reset_allowed)\n+\t\t\tcontinue;\n+\n+\t\tswitch (xs->fn_id) {\n+\t\tcase DLB_XSTATS_FN_DEV:\n+\t\t\tfn = get_dev_stat;\n+\t\t\tbreak;\n+\t\tcase DLB_XSTATS_FN_PORT:\n+\t\t\tfn = get_port_stat;\n+\t\t\tbreak;\n+\t\tcase DLB_XSTATS_FN_QUEUE:\n+\t\t\tfn = get_queue_stat;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDLB_LOG_ERR(\"Unexpected xstat fn_id %d\\n\", xs->fn_id);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tuint64_t val = fn(dlb, xs->obj_idx, xs->stat, xs->extra_arg);\n+\t\txs->reset_value = val;\n+\t}\n+}\n+\n+static int\n+dlb_xstats_reset_queue(struct dlb_eventdev *dlb, uint8_t queue_id,\n+\t\t       const uint32_t ids[], uint32_t nb_ids)\n+{\n+\tconst uint32_t reset = 1;\n+\n+\tif (ids) {\n+\t\tuint32_t nb_reset = dlb_xstats_update(dlb,\n+\t\t\t\t\tRTE_EVENT_DEV_XSTATS_QUEUE,\n+\t\t\t\t\tqueue_id, ids, NULL, nb_ids,\n+\t\t\t\t\treset);\n+\t\treturn nb_reset == nb_ids ? 0 : -EINVAL;\n+\t}\n+\n+\tif (ids == NULL)\n+\t\tdlb_xstats_reset_range(dlb,\n+\t\t\t\t       dlb->xstats_offset_for_qid[queue_id],\n+\t\t\t\t       dlb->xstats_count_per_qid[queue_id]);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_xstats_reset_port(struct dlb_eventdev *dlb, uint8_t port_id,\n+\t\t      const uint32_t ids[], uint32_t nb_ids)\n+{\n+\tconst uint32_t reset = 1;\n+\tint offset = dlb->xstats_offset_for_port[port_id];\n+\tint nb_stat = dlb->xstats_count_per_port[port_id];\n+\n+\tif (ids) {\n+\t\tuint32_t nb_reset = dlb_xstats_update(dlb,\n+\t\t\t\t\tRTE_EVENT_DEV_XSTATS_PORT, port_id,\n+\t\t\t\t\tids, NULL, nb_ids,\n+\t\t\t\t\treset);\n+\t\treturn nb_reset == nb_ids ? 0 : -EINVAL;\n+\t}\n+\n+\tdlb_xstats_reset_range(dlb, offset, nb_stat);\n+\treturn 0;\n+}\n+\n+static int\n+dlb_xstats_reset_dev(struct dlb_eventdev *dlb, const uint32_t ids[],\n+\t\t     uint32_t nb_ids)\n+{\n+\tuint32_t i;\n+\n+\tif (ids) {\n+\t\tfor (i = 0; i < nb_ids; i++) {\n+\t\t\tuint32_t id = ids[i];\n+\n+\t\t\tif (id >= dlb->xstats_count_mode_dev)\n+\t\t\t\treturn -EINVAL;\n+\t\t\tdlb_xstats_reset_range(dlb, id, 1);\n+\t\t}\n+\t} else {\n+\t\tfor (i = 0; i < dlb->xstats_count_mode_dev; i++)\n+\t\t\tdlb_xstats_reset_range(dlb, i, 1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+dlb_eventdev_xstats_reset(struct rte_eventdev *dev,\n+\t\t\t  enum rte_event_dev_xstats_mode mode,\n+\t\t\t  int16_t queue_port_id,\n+\t\t\t  const uint32_t ids[],\n+\t\t\t  uint32_t nb_ids)\n+{\n+\tstruct dlb_eventdev *dlb = dlb_pmd_priv(dev);\n+\tuint32_t i;\n+\n+\t/* handle -1 for queue_port_id here, looping over all ports/queues */\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\tif (dlb_xstats_reset_dev(dlb, ids, nb_ids))\n+\t\t\treturn -EINVAL;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id == -1) {\n+\t\t\tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++) {\n+\t\t\t\tif (dlb_xstats_reset_port(dlb, i, ids,\n+\t\t\t\t\t\t\t  nb_ids))\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t} else if (queue_port_id < DLB_MAX_NUM_PORTS) {\n+\t\t\tif (dlb_xstats_reset_port(dlb, queue_port_id, ids,\n+\t\t\t\t\t\t  nb_ids))\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id == -1) {\n+\t\t\tfor (i = 0; i < DLB_MAX_NUM_QUEUES; i++) {\n+\t\t\t\tif (dlb_xstats_reset_queue(dlb, i, ids,\n+\t\t\t\t\t\t\t   nb_ids))\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t} else if (queue_port_id < DLB_MAX_NUM_QUEUES) {\n+\t\t\tif (dlb_xstats_reset_queue(dlb, queue_port_id, ids,\n+\t\t\t\t\t\t   nb_ids))\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\t};\n+\n+\treturn 0;\n+}\n+\n+void\n+dlb_eventdev_dump(struct rte_eventdev *dev, FILE *f)\n+{\n+\tstruct dlb_eventdev *dlb;\n+\tstruct dlb_hw_dev *handle;\n+\tint i;\n+\n+\tif (!f) {\n+\t\tprintf(\"Invalid file pointer\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (!dev) {\n+\t\tfprintf(f, \"Invalid event device\\n\");\n+\t\treturn;\n+\t}\n+\n+\tdlb = dlb_pmd_priv(dev);\n+\n+\tif (!dlb) {\n+\t\tfprintf(f, \"DLB Event device cannot be dumped!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (!dlb->configured)\n+\t\tfprintf(f, \"DLB Event device is not configured\\n\");\n+\n+\thandle = &dlb->qm_instance;\n+\n+\tfprintf(f, \"================\\n\");\n+\tfprintf(f, \"DLB Device Dump\\n\");\n+\tfprintf(f, \"================\\n\");\n+\n+\tfprintf(f, \"Processor supports umonitor/umwait instructions = %s\\n\",\n+\t\tdlb->umwait_allowed ? \"yes\" : \"no\");\n+\n+\t/* Generic top level device information */\n+\n+\tfprintf(f, \"device is configured and run state =\");\n+\tif (dlb->run_state == DLB_RUN_STATE_STOPPED)\n+\t\tfprintf(f, \"STOPPED\\n\");\n+\telse if (dlb->run_state == DLB_RUN_STATE_STOPPING)\n+\t\tfprintf(f, \"STOPPING\\n\");\n+\telse if (dlb->run_state == DLB_RUN_STATE_STARTING)\n+\t\tfprintf(f, \"STARTING\\n\");\n+\telse if (dlb->run_state == DLB_RUN_STATE_STARTED)\n+\t\tfprintf(f, \"STARTED\\n\");\n+\telse\n+\t\tfprintf(f, \"UNEXPECTED\\n\");\n+\n+\tfprintf(f,\n+\t\t\"dev ID=%d, dom ID=%u, name=%s, path=%s, sock=%u, evdev=%p\\n\",\n+\t\thandle->device_id, handle->domain_id, handle->device_name,\n+\t\thandle->device_path, handle->info.socket_id, dlb->event_dev);\n+\n+\tfprintf(f, \"domain device path=%s\\n\", handle->domain_device_path);\n+\n+\tfprintf(f, \"num dir ports=%u, num dir queues=%u\\n\",\n+\t\tdlb->num_dir_ports, dlb->num_dir_queues);\n+\n+\tfprintf(f, \"num ldb ports=%u, num ldb queues=%u\\n\",\n+\t\tdlb->num_ldb_ports, dlb->num_ldb_queues);\n+\n+\tfprintf(f, \"dir_credit_pool_id=%u, num_credits=%u\\n\",\n+\t\thandle->cfg.dir_credit_pool_id, handle->cfg.num_dir_credits);\n+\n+\tfprintf(f, \"ldb_credit_pool_id=%u, num_credits=%u\\n\",\n+\t\thandle->cfg.ldb_credit_pool_id, handle->cfg.num_ldb_credits);\n+\n+\tfprintf(f, \"num atomic inflights=%u, hist list entries=%u\\n\",\n+\t\thandle->cfg.resources.num_atomic_inflights,\n+\t\thandle->cfg.resources.num_hist_list_entries);\n+\n+\tfprintf(f, \"results from most recent hw resource query:\\n\");\n+\n+\tfprintf(f, \"\\tnum_sched_domains = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_sched_domains);\n+\n+\tfprintf(f, \"\\tnum_ldb_queues = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues);\n+\n+\tfprintf(f, \"\\tnum_ldb_ports = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_ldb_ports);\n+\n+\tfprintf(f, \"\\tnum_dir_ports = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_dir_ports);\n+\n+\tfprintf(f, \"\\tnum_atomic_inflights = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_atomic_inflights);\n+\n+\tfprintf(f, \"\\tmax_contiguous_atomic_inflights = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_atomic_inflights);\n+\n+\tfprintf(f, \"\\tnum_hist_list_entries = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_hist_list_entries);\n+\n+\tfprintf(f, \"\\tmax_contiguous_hist_list_entries = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_hist_list_entries);\n+\n+\tfprintf(f, \"\\tnum_ldb_credits = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_ldb_credits);\n+\n+\tfprintf(f, \"\\tmax_contiguous_ldb_credits = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_ldb_credits);\n+\n+\tfprintf(f, \"\\tnum_dir_credits = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_dir_credits);\n+\n+\tfprintf(f, \"\\tmax_contiguous_dir_credits = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_dir_credits);\n+\n+\tfprintf(f, \"\\tnum_ldb_credit_pools = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_ldb_credit_pools);\n+\n+\tfprintf(f, \"\\tnum_dir_credit_pools = %u\\n\",\n+\t\tdlb->hw_rsrc_query_results.num_dir_credit_pools);\n+\n+\t/* Port level information */\n+\n+\tfor (i = 0; i < dlb->num_ports; i++) {\n+\t\tstruct dlb_eventdev_port *p = &dlb->ev_ports[i];\n+\t\tint j;\n+\n+\t\tif (!p->enq_configured)\n+\t\t\tfprintf(f, \"Port_%d is not configured\\n\", i);\n+\n+\t\tfprintf(f, \"Port_%d\\n\", i);\n+\t\tfprintf(f, \"=======\\n\");\n+\n+\t\tfprintf(f, \"\\tevport_%u is configured, setup done=%d\\n\",\n+\t\t\tp->id, p->setup_done);\n+\n+\t\tfprintf(f, \"\\tconfig state=%d, port state=%d\\n\",\n+\t\t\tp->qm_port.config_state, p->qm_port.state);\n+\n+\t\tfprintf(f, \"\\tport is %s\\n\",\n+\t\t\tp->qm_port.is_directed ? \"directed\" : \"load balanced\");\n+\n+\t\tfprintf(f, \"\\toutstanding releases=%u\\n\",\n+\t\t\tp->outstanding_releases);\n+\n+\t\tfprintf(f, \"\\tinflight max=%u, inflight credits=%u\\n\",\n+\t\t\tp->inflight_max, p->inflight_credits);\n+\n+\t\tfprintf(f, \"\\tcredit update quanta=%u, implicit release =%u\\n\",\n+\t\t\tp->credit_update_quanta, p->implicit_release);\n+\n+\t\tfprintf(f, \"\\tnum_links=%d, queues -> \", p->num_links);\n+\n+\t\tfor (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++) {\n+\t\t\tif (p->link[j].valid)\n+\t\t\t\tfprintf(f, \"id=%u prio=%u \",\n+\t\t\t\t\tp->link[j].queue_id,\n+\t\t\t\t\tp->link[j].priority);\n+\t\t}\n+\t\tfprintf(f, \"\\n\");\n+\n+\t\tfprintf(f, \"\\thardware port id=%u\\n\", p->qm_port.id);\n+\n+\t\tfprintf(f, \"\\tcached_ldb_credits=%u\\n\",\n+\t\t\tp->qm_port.cached_ldb_credits);\n+\n+\t\tfprintf(f, \"\\tldb_pushcount_at_credit_expiry = %u\\n\",\n+\t\t\tp->qm_port.ldb_pushcount_at_credit_expiry);\n+\n+\t\tfprintf(f, \"\\tldb_credits = %u\\n\",\n+\t\t\tp->qm_port.ldb_credits);\n+\n+\t\tfprintf(f, \"\\tcached_dir_credits = %u\\n\",\n+\t\t\tp->qm_port.cached_dir_credits);\n+\n+\t\tfprintf(f, \"\\tdir_pushcount_at_credit_expiry=%u\\n\",\n+\t\t\tp->qm_port.dir_pushcount_at_credit_expiry);\n+\n+\t\tfprintf(f, \"\\tdir_credits = %u\\n\",\n+\t\t\tp->qm_port.dir_credits);\n+\n+\t\tfprintf(f, \"\\tgenbit=%d, cq_idx=%d, cq_depth=%d\\n\",\n+\t\t\tp->qm_port.gen_bit,\n+\t\t\tp->qm_port.cq_idx,\n+\t\t\tp->qm_port.cq_depth);\n+\n+\t\tfprintf(f, \"\\tuse reserved token scheme=%d, cq_rsvd_token_deficit=%u\\n\",\n+\t\t\tp->qm_port.use_rsvd_token_scheme,\n+\t\t\tp->qm_port.cq_rsvd_token_deficit);\n+\n+\t\tfprintf(f, \"\\tinterrupt armed=%d\\n\",\n+\t\t\tp->qm_port.int_armed);\n+\n+\t\tfprintf(f, \"\\tPort statistics\\n\");\n+\n+\t\tfprintf(f, \"\\t\\trx_ok %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.rx_ok);\n+\n+\t\tfprintf(f, \"\\t\\trx_drop %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.rx_drop);\n+\n+\t\tfprintf(f, \"\\t\\trx_interrupt_wait %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.rx_interrupt_wait);\n+\n+\t\tfprintf(f, \"\\t\\trx_umonitor_umwait %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.rx_umonitor_umwait);\n+\n+\t\tfprintf(f, \"\\t\\ttx_ok %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_ok);\n+\n+\t\tfprintf(f, \"\\t\\ttotal_polls %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.total_polls);\n+\n+\t\tfprintf(f, \"\\t\\tzero_polls %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.zero_polls);\n+\n+\t\tfprintf(f, \"\\t\\ttx_nospc_ldb_hw_credits %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_ldb_hw_credits);\n+\n+\t\tfprintf(f, \"\\t\\ttx_nospc_dir_hw_credits %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_dir_hw_credits);\n+\n+\t\tfprintf(f, \"\\t\\ttx_nospc_inflight_max %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_inflight_max);\n+\n+\t\tfprintf(f, \"\\t\\ttx_nospc_new_event_limit %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_new_event_limit);\n+\n+\t\tfprintf(f, \"\\t\\ttx_nospc_inflight_credits %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_inflight_credits);\n+\n+\t\tfprintf(f, \"\\t\\ttx_new %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_op_cnt[RTE_EVENT_OP_NEW]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_fwd %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_op_cnt[RTE_EVENT_OP_FORWARD]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_rel %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_op_cnt[RTE_EVENT_OP_RELEASE]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_implicit_rel %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_implicit_rel);\n+\n+\t\tfprintf(f, \"\\t\\ttx_sched_ordered %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_sched_cnt[DLB_SCHED_ORDERED]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_sched_unordered %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_sched_cnt[DLB_SCHED_UNORDERED]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_sched_atomic %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_sched_cnt[DLB_SCHED_ATOMIC]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_sched_directed %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_sched_cnt[DLB_SCHED_DIRECTED]);\n+\n+\t\tfprintf(f, \"\\t\\ttx_invalid %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.tx_invalid);\n+\n+\t\tfprintf(f, \"\\t\\trx_sched_ordered %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.rx_sched_cnt[DLB_SCHED_ORDERED]);\n+\n+\t\tfprintf(f, \"\\t\\trx_sched_unordered %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.rx_sched_cnt[DLB_SCHED_UNORDERED]);\n+\n+\t\tfprintf(f, \"\\t\\trx_sched_atomic %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.rx_sched_cnt[DLB_SCHED_ATOMIC]);\n+\n+\t\tfprintf(f, \"\\t\\trx_sched_directed %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.rx_sched_cnt[DLB_SCHED_DIRECTED]);\n+\n+\t\tfprintf(f, \"\\t\\trx_sched_invalid %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.rx_sched_invalid);\n+\t}\n+\n+\t/* Queue level information */\n+\n+\tfor (i = 0; i < dlb->num_queues; i++) {\n+\t\tstruct dlb_eventdev_queue *q = &dlb->ev_queues[i];\n+\t\tint j, k;\n+\n+\t\tif (!q->setup_done)\n+\t\t\tfprintf(f, \"Queue_%d is not configured\\n\", i);\n+\n+\t\tfprintf(f, \"Queue_%d\\n\", i);\n+\t\tfprintf(f, \"========\\n\");\n+\n+\t\tfprintf(f, \"\\tevqueue_%u is set up\\n\", q->id);\n+\n+\t\tfprintf(f, \"\\tqueue is %s\\n\",\n+\t\t\tq->qm_queue.is_directed ? \"directed\" : \"load balanced\");\n+\n+\t\tfprintf(f, \"\\tnum_links=%d, ports -> \", q->num_links);\n+\n+\t\tfor (j = 0; j < dlb->num_ports; j++) {\n+\t\t\tstruct dlb_eventdev_port *p = &dlb->ev_ports[j];\n+\n+\t\t\tfor (k = 0; k < DLB_MAX_NUM_QIDS_PER_LDB_CQ; k++) {\n+\t\t\t\tif (p->link[k].valid &&\n+\t\t\t\t    p->link[k].queue_id == q->id)\n+\t\t\t\t\tfprintf(f, \"id=%u prio=%u \",\n+\t\t\t\t\t\tp->id, p->link[k].priority);\n+\t\t\t}\n+\t\t}\n+\t\tfprintf(f, \"\\n\");\n+\n+\t\t fprintf(f, \"\\tcurrent depth: %u events\\n\",\n+\t\t\t dlb_get_queue_depth(dlb, q));\n+\n+\t\tfprintf(f, \"\\tnum qid inflights=%u, sched_type=%d\\n\",\n+\t\t\tq->qm_queue.num_qid_inflights, q->qm_queue.sched_type);\n+\t}\n+}\ndiff --git a/drivers/event/dlb/meson.build b/drivers/event/dlb/meson.build\nindex 414b3ed..6f87274 100644\n--- a/drivers/event/dlb/meson.build\n+++ b/drivers/event/dlb/meson.build\n@@ -3,6 +3,7 @@\n \n sources = files('dlb.c',\n \t\t'dlb_iface.c',\n+\t\t'dlb_xstats.c',\n \t\t'pf/dlb_main.c',\n \t\t'pf/dlb_pf.c',\n \t\t'pf/base/dlb_resource.c'\n",
    "prefixes": [
        "v4",
        "07/22"
    ]
}