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GET /api/patches/77423/?format=api
{ "id": 77423, "url": "http://patches.dpdk.org/api/patches/77423/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-37-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200911131954.15999-37-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200911131954.15999-37-qi.z.zhang@intel.com", "date": "2020-09-11T13:19:50", "name": "[v2,36/40] net/ice/base: cache NVM module bank information", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a3a1c5dd596ce6cfbc4790cdc2b6b54226167349", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-37-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 12148, "url": "http://patches.dpdk.org/api/series/12148/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12148", "date": "2020-09-11T13:19:15", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/12148/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77423/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77423/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2F252A04B6;\n\tFri, 11 Sep 2020 15:23:31 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9EF071C2A7;\n\tFri, 11 Sep 2020 15:17:08 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id D8E281C217\n for <dev@dpdk.org>; Fri, 11 Sep 2020 15:16:53 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 06:16:52 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by FMSMGA003.fm.intel.com with ESMTP; 11 Sep 2020 06:16:51 -0700" ], "IronPort-SDR": [ "\n IZdIDLHeaeF1peT1PgYYy19UoeYPYP5rommniHcwgnKTaM5AcsnA6VA/cOAelEPte6+Pt9W6nN\n GPyArv/dR4gg==", "\n AqN2sEYgty8L9zoBXlkzw9QStZGJodv2U8Sc455lmH8JZjweZVrbJ5upZa64qHT0Kn2yMtOSqA\n uWEuSvk4otQw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9740\"; a=\"146482419\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"146482419\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"342296769\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Fri, 11 Sep 2020 21:19:50 +0800", "Message-Id": "<20200911131954.15999-37-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200911131954.15999-1-qi.z.zhang@intel.com>", "References": "<20200907112826.48493-1-qi.z.zhang@intel.com>\n <20200911131954.15999-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 36/40] net/ice/base: cache NVM module bank\n\tinformation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The ice flash contains two copies of each of the NVM, Option ROM, and\nNetlist modules. Each bank has a pointer word and a size word. In order\nto correctly read from the active flash bank, the driver must calculate\nthe offset manually.\n\nDuring NVM initialization, read the Shadow RAM control word and\ndetermine which bank is active for each NVM module. Additionally, cache\nthe size and pointer values for use in calculating the correct offset.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_nvm.c | 151 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_type.h | 29 ++++++++\n 2 files changed, 180 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 56a2346a3..61af767ed 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -503,6 +503,151 @@ static enum ice_status ice_discover_flash_size(struct ice_hw *hw)\n }\n \n /**\n+ * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM word to read\n+ * @pointer: pointer value read from Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to a pointer value specified\n+ * in bytes. This function assumes the specified offset is a valid pointer\n+ * word.\n+ *\n+ * Each pointer word specifies whether it is stored in word size or 4KB\n+ * sector size by using the highest bit. The reported pointer value will be in\n+ * bytes, intended for flat NVM reads.\n+ */\n+static enum ice_status\n+ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)\n+{\n+\tenum ice_status status;\n+\tu16 value;\n+\n+\tstatus = ice_read_sr_word(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Determine if the pointer is in 4KB or word units */\n+\tif (value & ICE_SR_NVM_PTR_4KB_UNITS)\n+\t\t*pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;\n+\telse\n+\t\t*pointer = value * 2;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_sr_area_size - Read an area size from a Shadow RAM word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM to read\n+ * @size: size value read from the Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to an area size value\n+ * specified in bytes. This function assumes the specified offset is a valid\n+ * area size word.\n+ *\n+ * Each area size word is specified in 4KB sector units. This function reports\n+ * the size in bytes, intended for flat NVM reads.\n+ */\n+static enum ice_status\n+ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)\n+{\n+\tenum ice_status status;\n+\tu16 value;\n+\n+\tstatus = ice_read_sr_word(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Area sizes are always specified in 4KB units */\n+\t*size = value * 4 * 1024;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_determine_active_flash_banks - Discover active bank for each module\n+ * @hw: pointer to the HW struct\n+ *\n+ * Read the Shadow RAM control word and determine which banks are active for\n+ * the NVM, OROM, and Netlist modules. Also read and calculate the associated\n+ * pointer and size. These values are then cached into the ice_flash_info\n+ * structure for later use in order to calculate the correct offset to read\n+ * from the active module.\n+ */\n+static enum ice_status\n+ice_determine_active_flash_banks(struct ice_hw *hw)\n+{\n+\tstruct ice_bank_info *banks = &hw->flash.banks;\n+\tenum ice_status status;\n+\tu16 ctrl_word;\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read the Shadow RAM control word\\n\");\n+\t\treturn status;\n+\t}\n+\n+\t/* Check that the control word indicates validity */\n+\tif ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Shadow RAM control word is invalid\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\tif (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))\n+\t\tbanks->nvm_bank = ICE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->nvm_bank = ICE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))\n+\t\tbanks->orom_bank = ICE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->orom_bank = ICE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))\n+\t\tbanks->netlist_bank = ICE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->netlist_bank = ICE_2ND_FLASH_BANK;\n+\n+\tstatus = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read NVM bank pointer\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read NVM bank area size\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read OROM bank pointer\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read OROM bank area size\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read Netlist bank pointer\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to read Netlist bank area size\\n\");\n+\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n * ice_init_nvm - initializes NVM setting\n * @hw: pointer to the HW struct\n *\n@@ -544,6 +689,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)\n \t\treturn status;\n \t}\n \n+\tstatus = ice_determine_active_flash_banks(hw);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_NVM, \"Failed to determine active flash banks.\\n\");\n+\t\treturn status;\n+\t}\n+\n \tstatus = ice_get_nvm_ver_info(hw, &flash->nvm);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read NVM info.\\n\");\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 9e9a2198d..1e1c672cb 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -518,10 +518,33 @@ struct ice_nvm_info {\n \tu8 minor;\n };\n \n+/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules\n+ * of the flash image.\n+ */\n+enum ice_flash_bank {\n+\tICE_INVALID_FLASH_BANK,\n+\tICE_1ST_FLASH_BANK,\n+\tICE_2ND_FLASH_BANK,\n+};\n+\n+/* information for accessing NVM, OROM, and Netlist flash banks */\n+struct ice_bank_info {\n+\tu32 nvm_ptr;\t\t\t\t/* Pointer to 1st NVM bank */\n+\tu32 nvm_size;\t\t\t\t/* Size of NVM bank */\n+\tu32 orom_ptr;\t\t\t\t/* Pointer to 1st OROM bank */\n+\tu32 orom_size;\t\t\t\t/* Size of OROM bank */\n+\tu32 netlist_ptr;\t\t\t/* Pointer to 1st Netlist bank */\n+\tu32 netlist_size;\t\t\t/* Size of Netlist bank */\n+\tenum ice_flash_bank nvm_bank;\t\t/* Active NVM bank */\n+\tenum ice_flash_bank orom_bank;\t\t/* Active OROM bank */\n+\tenum ice_flash_bank netlist_bank;\t/* Active Netlist bank */\n+};\n+\n /* Flash Chip Information */\n struct ice_flash_info {\n \tstruct ice_orom_info orom;\t/* Option ROM version info */\n \tstruct ice_nvm_info nvm;\t/* NVM version information */\n+\tstruct ice_bank_info banks;\t/* Flash Bank information */\n \tu16 sr_words;\t\t\t/* Shadow RAM size in words */\n \tu32 flash_size;\t\t\t/* Size of available flash in bytes */\n \tu8 blank_nvm_mode;\t\t/* is NVM empty (no FW present) */\n@@ -1099,6 +1122,12 @@ enum ice_sw_fwd_act_type {\n #define ICE_SR_PCIE_ALT_SIZE_WORDS\t512\n #define ICE_SR_CTRL_WORD_1_S\t\t0x06\n #define ICE_SR_CTRL_WORD_1_M\t\t(0x03 << ICE_SR_CTRL_WORD_1_S)\n+#define ICE_SR_CTRL_WORD_VALID\t\t0x1\n+#define ICE_SR_CTRL_WORD_OROM_BANK\tBIT(3)\n+#define ICE_SR_CTRL_WORD_NETLIST_BANK\tBIT(4)\n+#define ICE_SR_CTRL_WORD_NVM_BANK\tBIT(5)\n+\n+#define ICE_SR_NVM_PTR_4KB_UNITS\tBIT(15)\n \n /* Shadow RAM related */\n #define ICE_SR_SECTOR_SIZE_IN_WORDS\t0x800\n", "prefixes": [ "v2", "36/40" ] }