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GET /api/patches/77419/?format=api
{ "id": 77419, "url": "http://patches.dpdk.org/api/patches/77419/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-33-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200911131954.15999-33-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200911131954.15999-33-qi.z.zhang@intel.com", "date": "2020-09-11T13:19:46", "name": "[v2,32/40] net/ice/base: enable QinQ filter for switch advanced rule", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a53c098296da8f54c3e4b6904a5a0ff43cffc45a", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-33-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 12148, "url": "http://patches.dpdk.org/api/series/12148/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12148", "date": "2020-09-11T13:19:15", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/12148/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77419/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77419/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D44C9A04B7;\n\tFri, 11 Sep 2020 15:22:35 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 233591C23C;\n\tFri, 11 Sep 2020 15:17:01 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id E91EA1C1FB\n for <dev@dpdk.org>; Fri, 11 Sep 2020 15:16:47 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 06:16:47 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by FMSMGA003.fm.intel.com with ESMTP; 11 Sep 2020 06:16:46 -0700" ], "IronPort-SDR": [ "\n xVkJqDjYJgTwixPVtx2xN811taWAK/5FiKIhUHvrexLQI6058/KGQPTtuAZLj1bytJlVmGsJRU\n ZkfH9+tq9TMA==", "\n pKhKnBQwdODjmCR8GBuwsJddMCczXt5TA9OLv2SYDL59a/wAiGA62a9UqnXeAoro6s3Fh0rGh0\n 8SXEHGwN/LjA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9740\"; a=\"146482395\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"146482395\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"342296744\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Wei Zhao <wei.zhao1@intel.com>", "Date": "Fri, 11 Sep 2020 21:19:46 +0800", "Message-Id": "<20200911131954.15999-33-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200911131954.15999-1-qi.z.zhang@intel.com>", "References": "<20200907112826.48493-1-qi.z.zhang@intel.com>\n <20200911131954.15999-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 32/40] net/ice/base: enable QinQ filter for\n\tswitch advanced rule", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable QinQ type filter for switch advanced rule, it support tunnel\nand non-tunnel packet use external and inner vlan id as input set\nfor rules, it also support session id as input set for PPPoE rule\nwith QinQ flag in packet.\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_protocol_type.h | 8 ++\n drivers/net/ice/base/ice_switch.c | 236 +++++++++++++++++++++++++++++--\n 2 files changed, 230 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h\nindex 4d3136fb2..e8caefd8f 100644\n--- a/drivers/net/ice/base/ice_protocol_type.h\n+++ b/drivers/net/ice/base/ice_protocol_type.h\n@@ -52,6 +52,7 @@ enum ice_protocol_type {\n \tICE_AH,\n \tICE_NAT_T,\n \tICE_GTP_NO_PAY,\n+\tICE_VLAN_EX,\n \tICE_PROTOCOL_LAST\n };\n \n@@ -102,6 +103,12 @@ enum ice_sw_tunnel_type {\n \tICE_SW_TUN_PROFID_IPV4_PFCP_SESSION,\n \tICE_SW_TUN_PROFID_IPV6_PFCP_NODE,\n \tICE_SW_TUN_PROFID_IPV6_PFCP_SESSION,\n+\tICE_SW_TUN_AND_NON_TUN_QINQ,\n+\tICE_NON_TUN_QINQ,\n+\tICE_SW_TUN_PPPOE_QINQ,\n+\tICE_SW_TUN_PPPOE_PAY_QINQ,\n+\tICE_SW_TUN_PPPOE_IPV4_QINQ,\n+\tICE_SW_TUN_PPPOE_IPV6_QINQ,\n \tICE_ALL_TUNNELS /* All tunnel types including NVGRE */\n };\n \n@@ -160,6 +167,7 @@ enum ice_prot_id {\n #define ICE_MAC_OFOS_HW\t\t1\n #define ICE_MAC_IL_HW\t\t4\n #define ICE_ETYPE_OL_HW\t\t9\n+#define ICE_VLAN_OF_HW\t\t16\n #define ICE_VLAN_OL_HW\t\t17\n #define ICE_IPV4_OFOS_HW\t32\n #define ICE_IPV4_IL_HW\t\t33\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 1c07c60a1..01d59edf4 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -1202,6 +1202,153 @@ static const u8 dummy_ipv6_l2tpv3_pkt[] = {\n \t0x00, 0x00,\t\t/* 2 bytes for 4 bytes alignment */\n };\n \n+static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {\n+\t{ ICE_MAC_OFOS,\t\t0 },\n+\t{ ICE_VLAN_EX,\t\t14 },\n+\t{ ICE_VLAN_OFOS,\t18 },\n+\t{ ICE_IPV4_OFOS,\t22 },\n+\t{ ICE_PROTOCOL_LAST,\t0 },\n+};\n+\n+static const u8 dummy_qinq_ipv4_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x91, 0x00,\n+\n+\t0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */\n+\t0x00, 0x00, 0x08, 0x00, /* ICE_VLAN_OFOS 18 */\n+\n+\t0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */\n+\t0x00, 0x01, 0x00, 0x00,\n+\t0x00, 0x11, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 42 */\n+\t0x00, 0x08, 0x00, 0x00,\n+\n+\t0x00, 0x00,\t/* 2 bytes for 4 byte alignment */\n+};\n+\n+static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = {\n+\t{ ICE_MAC_OFOS,\t\t0 },\n+\t{ ICE_VLAN_EX,\t\t14 },\n+\t{ ICE_VLAN_OFOS,\t18 },\n+\t{ ICE_IPV6_OFOS,\t22 },\n+\t{ ICE_PROTOCOL_LAST,\t0 },\n+};\n+\n+static const u8 dummy_qinq_ipv6_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x91, 0x00,\n+\n+\t0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */\n+\t0x00, 0x00, 0x86, 0xDD, /* ICE_VLAN_OFOS 18 */\n+\n+\t0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */\n+\t0x00, 0x10, 0x11, 0x00, /* Next header UDP */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 62 */\n+\t0x00, 0x10, 0x00, 0x00,\n+\n+\t0x00, 0x00, 0x00, 0x00, /* needed for ESP packets */\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x00, 0x00,\t/* 2 bytes for 4 byte alignment */\n+};\n+\n+static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = {\n+\t{ ICE_MAC_OFOS,\t\t0 },\n+\t{ ICE_VLAN_EX,\t\t14 },\n+\t{ ICE_VLAN_OFOS,\t18 },\n+\t{ ICE_PPPOE,\t\t22 },\n+\t{ ICE_PROTOCOL_LAST,\t0 },\n+};\n+\n+static const\n+struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = {\n+\t{ ICE_MAC_OFOS,\t\t0 },\n+\t{ ICE_VLAN_EX,\t\t14 },\n+\t{ ICE_VLAN_OFOS,\t18 },\n+\t{ ICE_PPPOE,\t\t22 },\n+\t{ ICE_IPV4_OFOS,\t30 },\n+\t{ ICE_PROTOCOL_LAST,\t0 },\n+};\n+\n+static const u8 dummy_qinq_pppoe_ipv4_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x91, 0x00,\n+\n+\t0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */\n+\t0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 18 */\n+\n+\t0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */\n+\t0x00, 0x16,\n+\n+\t0x00, 0x21,\t\t/* PPP Link Layer 28 */\n+\n+\t0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 30 */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x00, 0x00,\t/* 2 bytes for 4 byte alignment */\n+};\n+\n+static const\n+struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = {\n+\t{ ICE_MAC_OFOS,\t\t0 },\n+\t{ ICE_ETYPE_OL,\t\t12 },\n+\t{ ICE_VLAN_EX,\t\t14},\n+\t{ ICE_VLAN_OFOS,\t18 },\n+\t{ ICE_PPPOE,\t\t22 },\n+\t{ ICE_IPV6_OFOS,\t30 },\n+\t{ ICE_PROTOCOL_LAST,\t0 },\n+};\n+\n+static const u8 dummy_qinq_pppoe_ipv6_packet[] = {\n+\t0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x91, 0x00,\t\t/* ICE_ETYPE_OL 12 */\n+\n+\t0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */\n+\t0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 18 */\n+\n+\t0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */\n+\t0x00, 0x2a,\n+\n+\t0x00, 0x57,\t\t/* PPP Link Layer 28*/\n+\n+\t0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 30 */\n+\t0x00, 0x00, 0x3b, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+\n+\t0x00, 0x00,\t\t/* 2 bytes for 4 bytes alignment */\n+};\n+\n /* this is a recipe to profile association bitmap */\n static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],\n \t\t\t ICE_MAX_NUM_PROFILES);\n@@ -1229,13 +1376,13 @@ static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,\n * ice_get_tun_type_for_recipe - get tunnel type for the recipe\n * @rid: recipe ID that we are populating\n */\n-static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid)\n+static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan)\n {\n \tu8 vxlan_profile[12] = {10, 11, 12, 16, 17, 18, 22, 23, 24, 25, 26, 27};\n \tu8 gre_profile[12] = {13, 14, 15, 19, 20, 21, 28, 29, 30, 31, 32, 33};\n \tu8 pppoe_profile[7] = {34, 35, 36, 37, 38, 39, 40};\n \tu8 non_tun_profile[6] = {4, 5, 6, 7, 8, 9};\n-\tenum ice_sw_tunnel_type tun_type = ICE_NON_TUN;\n+\tenum ice_sw_tunnel_type tun_type;\n \tu16 i, j, profile_num = 0;\n \tbool non_tun_valid = false;\n \tbool pppoe_valid = false;\n@@ -1416,6 +1563,19 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid)\n \t\t}\n \t}\n \n+\tif (vlan && tun_type == ICE_SW_TUN_PPPOE)\n+\t\ttun_type = ICE_SW_TUN_PPPOE_QINQ;\n+\telse if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV6)\n+\t\ttun_type = ICE_SW_TUN_PPPOE_IPV6_QINQ;\n+\telse if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV4)\n+\t\ttun_type = ICE_SW_TUN_PPPOE_IPV4_QINQ;\n+\telse if (vlan && tun_type == ICE_SW_TUN_PPPOE_PAY)\n+\t\ttun_type = ICE_SW_TUN_PPPOE_PAY_QINQ;\n+\telse if (vlan && tun_type == ICE_SW_TUN_AND_NON_TUN)\n+\t\ttun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;\n+\telse if (vlan && tun_type == ICE_NON_TUN)\n+\t\ttun_type = ICE_NON_TUN_QINQ;\n+\n \treturn tun_type;\n }\n \n@@ -1440,6 +1600,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tstruct ice_prot_lkup_ext *lkup_exts;\n \tenum ice_status status;\n \tu8 fv_word_idx = 0;\n+\tbool vlan = false;\n \tu16 sub_recps;\n \n \tice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);\n@@ -1528,6 +1689,9 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\t\tlkup_exts->fv_words[fv_word_idx].off = off;\n \t\t\tlkup_exts->field_mask[fv_word_idx] =\n \t\t\t\trg_entry->fv_mask[i];\n+\t\t\tif (prot == ICE_META_DATA_ID_HW &&\n+\t\t\t off == ICE_TUN_FLAG_MDID_OFF)\n+\t\t\t\tvlan = true;\n \t\t\tfv_word_idx++;\n \t\t}\n \t\t/* populate rg_list with the data from the child entry of this\n@@ -1562,7 +1726,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tlkup_exts->n_val_words = fv_word_idx;\n \trecps[rid].big_recp = (num_recps > 1);\n \trecps[rid].n_grp_count = (u8)num_recps;\n-\trecps[rid].tun_type = ice_get_tun_type_for_recipe(rid);\n+\trecps[rid].tun_type = ice_get_tun_type_for_recipe(rid, vlan);\n \trecps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)\n \t\tice_memdup(hw, tmp, recps[rid].n_grp_count *\n \t\t\t sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);\n@@ -2726,7 +2890,7 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n \t} while (req_desc && !status);\n \n out:\n-\tice_free(hw, (void *)rbuf);\n+\tice_free(hw, rbuf);\n \treturn status;\n }\n \n@@ -2982,8 +3146,7 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t\tm_ent->fltr_info.fwd_id.hw_vsi_id;\n \n \tact = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;\n-\tact |= (id << ICE_LG_ACT_VSI_LIST_ID_S) &\n-\t\tICE_LG_ACT_VSI_LIST_ID_M;\n+\tact |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M;\n \tif (m_ent->vsi_count > 1)\n \t\tact |= ICE_LG_ACT_VSI_LIST;\n \tlg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);\n@@ -3064,13 +3227,11 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t */\n \tlg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_acts);\n \trules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n-\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw,\n-\t\t\t\t\t\t\t\t rules_size);\n+\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);\n \tif (!lg_act)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n-\trx_tx = (struct ice_aqc_sw_rules_elem *)\n-\t\t((u8 *)lg_act + lg_act_size);\n+\trx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);\n \n \t/* Fill in the first switch rule i.e. large action */\n \tlg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n@@ -4525,7 +4686,8 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,\n \thw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n \n \ts_rule_size = set ? ICE_SW_RULE_RX_TX_ETH_HDR_SIZE :\n-\t\t\t ICE_SW_RULE_RX_TX_NO_HDR_SIZE;\n+\t\tICE_SW_RULE_RX_TX_NO_HDR_SIZE;\n+\n \ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);\n \tif (!s_rule)\n \t\treturn ICE_ERR_NO_MEMORY;\n@@ -5825,6 +5987,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = {\n \t{ ICE_AH,\t\t{ 0, 2, 4, 6, 8, 10 } },\n \t{ ICE_NAT_T,\t\t{ 8, 10, 12, 14 } },\n \t{ ICE_GTP_NO_PAY,\t{ 8, 10, 12, 14 } },\n+\t{ ICE_VLAN_EX,\t\t{ 0, 2 } },\n };\n \n /* The following table describes preferred grouping of recipes.\n@@ -5858,6 +6021,7 @@ static const struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = {\n \t{ ICE_AH,\t\tICE_AH_HW },\n \t{ ICE_NAT_T,\t\tICE_UDP_ILOS_HW },\n \t{ ICE_GTP_NO_PAY,\tICE_UDP_ILOS_HW },\n+\t{ ICE_VLAN_EX,\t\tICE_VLAN_OF_HW },\n };\n \n /**\n@@ -6569,6 +6733,12 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *mask)\n \tcase ICE_SW_TUN_NVGRE:\n \tcase ICE_SW_TUN_UDP:\n \tcase ICE_ALL_TUNNELS:\n+\tcase ICE_SW_TUN_AND_NON_TUN_QINQ:\n+\tcase ICE_NON_TUN_QINQ:\n+\tcase ICE_SW_TUN_PPPOE_QINQ:\n+\tcase ICE_SW_TUN_PPPOE_PAY_QINQ:\n+\tcase ICE_SW_TUN_PPPOE_IPV4_QINQ:\n+\tcase ICE_SW_TUN_PPPOE_IPV6_QINQ:\n \t\t*mask = ICE_TUN_FLAG_MASK;\n \t\treturn true;\n \n@@ -6627,6 +6797,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \n \tswitch (rinfo->tun_type) {\n \tcase ICE_NON_TUN:\n+\tcase ICE_NON_TUN_QINQ:\n \t\tprof_type = ICE_PROF_NON_TUN;\n \t\tbreak;\n \tcase ICE_ALL_TUNNELS:\n@@ -6645,12 +6816,15 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \t\tprof_type = ICE_PROF_TUN_GRE;\n \t\tbreak;\n \tcase ICE_SW_TUN_PPPOE:\n+\tcase ICE_SW_TUN_PPPOE_QINQ:\n \t\tprof_type = ICE_PROF_TUN_PPPOE;\n \t\tbreak;\n \tcase ICE_SW_TUN_PPPOE_PAY:\n+\tcase ICE_SW_TUN_PPPOE_PAY_QINQ:\n \t\tice_set_bit(ICE_PROFID_PPPOE_PAY, bm);\n \t\treturn;\n \tcase ICE_SW_TUN_PPPOE_IPV4:\n+\tcase ICE_SW_TUN_PPPOE_IPV4_QINQ:\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV4_OTHER, bm);\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV4_TCP, bm);\n@@ -6662,6 +6836,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);\n \t\treturn;\n \tcase ICE_SW_TUN_PPPOE_IPV6:\n+\tcase ICE_SW_TUN_PPPOE_IPV6_QINQ:\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV6_OTHER, bm);\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV6_UDP, bm);\n \t\tice_set_bit(ICE_PROFID_PPPOE_IPV6_TCP, bm);\n@@ -6757,6 +6932,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \t\tice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_TCP, bm);\n \t\treturn;\n \tcase ICE_SW_TUN_AND_NON_TUN:\n+\tcase ICE_SW_TUN_AND_NON_TUN_QINQ:\n \tdefault:\n \t\tprof_type = ICE_PROF_ALL;\n \t\tbreak;\n@@ -7046,6 +7222,38 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t\t\ttcp = true;\n \t}\n \n+\tif ((tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n+\t tun_type == ICE_NON_TUN_QINQ) && ipv6) {\n+\t\t*pkt = dummy_qinq_ipv6_pkt;\n+\t\t*pkt_len = sizeof(dummy_qinq_ipv6_pkt);\n+\t\t*offsets = dummy_qinq_ipv6_packet_offsets;\n+\t\treturn;\n+\t} else if (tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n+\t\t\t tun_type == ICE_NON_TUN_QINQ) {\n+\t\t*pkt = dummy_qinq_ipv4_pkt;\n+\t\t*pkt_len = sizeof(dummy_qinq_ipv4_pkt);\n+\t\t*offsets = dummy_qinq_ipv4_packet_offsets;\n+\t\treturn;\n+\t}\n+\n+\tif (tun_type == ICE_SW_TUN_PPPOE_IPV6_QINQ) {\n+\t\t*pkt = dummy_qinq_pppoe_ipv6_packet;\n+\t\t*pkt_len = sizeof(dummy_qinq_pppoe_ipv6_packet);\n+\t\t*offsets = dummy_qinq_pppoe_packet_ipv6_offsets;\n+\t\treturn;\n+\t} else if (tun_type == ICE_SW_TUN_PPPOE_IPV4_QINQ) {\n+\t\t*pkt = dummy_qinq_pppoe_ipv4_pkt;\n+\t\t*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);\n+\t\t*offsets = dummy_qinq_pppoe_ipv4_packet_offsets;\n+\t\treturn;\n+\t} else if (tun_type == ICE_SW_TUN_PPPOE_QINQ ||\n+\t\t\ttun_type == ICE_SW_TUN_PPPOE_PAY_QINQ) {\n+\t\t*pkt = dummy_qinq_pppoe_ipv4_pkt;\n+\t\t*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);\n+\t\t*offsets = dummy_qinq_pppoe_packet_offsets;\n+\t\treturn;\n+\t}\n+\n \tif (tun_type == ICE_SW_TUN_IPV4_GTPU_NO_PAY) {\n \t\t*pkt = dummy_ipv4_gtpu_ipv4_packet;\n \t\t*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);\n@@ -7364,6 +7572,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t\t\tlen = sizeof(struct ice_ethtype_hdr);\n \t\t\tbreak;\n \t\tcase ICE_VLAN_OFOS:\n+\t\tcase ICE_VLAN_EX:\n \t\t\tlen = sizeof(struct ice_vlan_hdr);\n \t\t\tbreak;\n \t\tcase ICE_IPV4_OFOS:\n@@ -8038,9 +8247,8 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\tu16 rule_buf_sz;\n \n \t\trule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;\n-\t\ts_rule =\n-\t\t\t(struct ice_aqc_sw_rules_elem *)ice_malloc(hw,\n-\t\t\t\t\t\t\t\t rule_buf_sz);\n+\t\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\t\tice_malloc(hw, rule_buf_sz);\n \t\tif (!s_rule)\n \t\t\treturn ICE_ERR_NO_MEMORY;\n \t\ts_rule->pdata.lkup_tx_rx.act = 0;\n", "prefixes": [ "v2", "32/40" ] }