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GET /api/patches/77416/?format=api
{ "id": 77416, "url": "http://patches.dpdk.org/api/patches/77416/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-30-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200911131954.15999-30-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200911131954.15999-30-qi.z.zhang@intel.com", "date": "2020-09-11T13:19:43", "name": "[v2,29/40] net/ice/base: preserve NVM capabilities in safe mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6a28841138166cb43112944b3a058c387d410e9e", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-30-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 12148, "url": "http://patches.dpdk.org/api/series/12148/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12148", "date": "2020-09-11T13:19:15", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/12148/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77416/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/77416/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 37642A04B7;\n\tFri, 11 Sep 2020 15:21:58 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4888C1C225;\n\tFri, 11 Sep 2020 15:16:57 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 49FF21C191\n for <dev@dpdk.org>; Fri, 11 Sep 2020 15:16:43 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 06:16:42 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by FMSMGA003.fm.intel.com with ESMTP; 11 Sep 2020 06:16:41 -0700" ], "IronPort-SDR": [ "\n GtPJV3RBKodcaI6JHiZ7ULQSR4OGhoAR96GY71eG7P1ar33oKN4oksQcBy8EWiEMTvXPV3KvmZ\n GPNWGNyB3v3A==", "\n Zaz3SX103Wj591D8CZc/sM2u2DWi6gudwLPpU2payqs3RGW2cJHsttsRZ4sGKBOHAJVy1WNVZG\n 2sFHwnACMafg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9740\"; a=\"146482364\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"146482364\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"342296709\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Fri, 11 Sep 2020 21:19:43 +0800", "Message-Id": "<20200911131954.15999-30-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200911131954.15999-1-qi.z.zhang@intel.com>", "References": "<20200907112826.48493-1-qi.z.zhang@intel.com>\n <20200911131954.15999-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 29/40] net/ice/base: preserve NVM capabilities\n\tin safe mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "If the driver initializes in safe mode, it will call\nice_set_safe_mode_caps. This results in clearing the capabilities\nstructures, in order to set them up for operating in safe mode, ensuring\nmany features are disabled.\n\nThis has a side effect of also clearing the capability bits that relate\nto NVM update. The result is that the device driver will not indicate\nsupport for unified update, even if the firmware is capable.\n\nFix this by adding the relevant capability fields to the list of values\nwe preserve. To simplify the code, use a common_cap structure instead of\na handful of local variables. To reduce some duplication of the\ncapability name, introduce a couple of macros used to restore the\ncapabilities values from the cached copy.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 43 +++++++++++++++++++--------------------\n 1 file changed, 21 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex f5b1a0ce8..d917f8be7 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2248,26 +2248,25 @@ void ice_set_safe_mode_caps(struct ice_hw *hw)\n {\n \tstruct ice_hw_func_caps *func_caps = &hw->func_caps;\n \tstruct ice_hw_dev_caps *dev_caps = &hw->dev_caps;\n-\tu32 valid_func, rxq_first_id, txq_first_id;\n-\tu32 msix_vector_first_id, max_mtu;\n+\tstruct ice_hw_common_caps cached_caps;\n \tu32 num_funcs;\n \n \t/* cache some func_caps values that should be restored after memset */\n-\tvalid_func = func_caps->common_cap.valid_functions;\n-\ttxq_first_id = func_caps->common_cap.txq_first_id;\n-\trxq_first_id = func_caps->common_cap.rxq_first_id;\n-\tmsix_vector_first_id = func_caps->common_cap.msix_vector_first_id;\n-\tmax_mtu = func_caps->common_cap.max_mtu;\n+\tcached_caps = func_caps->common_cap;\n \n \t/* unset func capabilities */\n \tmemset(func_caps, 0, sizeof(*func_caps));\n \n+#define ICE_RESTORE_FUNC_CAP(name) \\\n+\tfunc_caps->common_cap.name = cached_caps.name\n+\n \t/* restore cached values */\n-\tfunc_caps->common_cap.valid_functions = valid_func;\n-\tfunc_caps->common_cap.txq_first_id = txq_first_id;\n-\tfunc_caps->common_cap.rxq_first_id = rxq_first_id;\n-\tfunc_caps->common_cap.msix_vector_first_id = msix_vector_first_id;\n-\tfunc_caps->common_cap.max_mtu = max_mtu;\n+\tICE_RESTORE_FUNC_CAP(valid_functions);\n+\tICE_RESTORE_FUNC_CAP(txq_first_id);\n+\tICE_RESTORE_FUNC_CAP(rxq_first_id);\n+\tICE_RESTORE_FUNC_CAP(msix_vector_first_id);\n+\tICE_RESTORE_FUNC_CAP(max_mtu);\n+\tICE_RESTORE_FUNC_CAP(nvm_unified_update);\n \n \t/* one Tx and one Rx queue in safe mode */\n \tfunc_caps->common_cap.num_rxq = 1;\n@@ -2278,22 +2277,22 @@ void ice_set_safe_mode_caps(struct ice_hw *hw)\n \tfunc_caps->guar_num_vsi = 1;\n \n \t/* cache some dev_caps values that should be restored after memset */\n-\tvalid_func = dev_caps->common_cap.valid_functions;\n-\ttxq_first_id = dev_caps->common_cap.txq_first_id;\n-\trxq_first_id = dev_caps->common_cap.rxq_first_id;\n-\tmsix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;\n-\tmax_mtu = dev_caps->common_cap.max_mtu;\n+\tcached_caps = dev_caps->common_cap;\n \tnum_funcs = dev_caps->num_funcs;\n \n \t/* unset dev capabilities */\n \tmemset(dev_caps, 0, sizeof(*dev_caps));\n \n+#define ICE_RESTORE_DEV_CAP(name) \\\n+\tdev_caps->common_cap.name = cached_caps.name\n+\n \t/* restore cached values */\n-\tdev_caps->common_cap.valid_functions = valid_func;\n-\tdev_caps->common_cap.txq_first_id = txq_first_id;\n-\tdev_caps->common_cap.rxq_first_id = rxq_first_id;\n-\tdev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;\n-\tdev_caps->common_cap.max_mtu = max_mtu;\n+\tICE_RESTORE_DEV_CAP(valid_functions);\n+\tICE_RESTORE_DEV_CAP(txq_first_id);\n+\tICE_RESTORE_DEV_CAP(rxq_first_id);\n+\tICE_RESTORE_DEV_CAP(msix_vector_first_id);\n+\tICE_RESTORE_DEV_CAP(max_mtu);\n+\tICE_RESTORE_DEV_CAP(nvm_unified_update);\n \tdev_caps->num_funcs = num_funcs;\n \n \t/* one Tx and one Rx queue per function in safe mode */\n", "prefixes": [ "v2", "29/40" ] }