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GET /api/patches/77400/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 77400,
    "url": "http://patches.dpdk.org/api/patches/77400/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-14-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200911131954.15999-14-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200911131954.15999-14-qi.z.zhang@intel.com",
    "date": "2020-09-11T13:19:27",
    "name": "[v2,13/40] net/ice/base: introduce and use for each bit iterator",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b15eb32df651c4119fe4bd84e03a40796e40abc9",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-14-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 12148,
            "url": "http://patches.dpdk.org/api/series/12148/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12148",
            "date": "2020-09-11T13:19:15",
            "name": "ice base code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/12148/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77400/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/77400/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9020A04B7;\n\tFri, 11 Sep 2020 15:18:34 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 89F401C1AA;\n\tFri, 11 Sep 2020 15:16:29 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 6264A1C195\n for <dev@dpdk.org>; Fri, 11 Sep 2020 15:16:20 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 06:16:19 -0700",
            "from dpdk51.sh.intel.com ([10.67.111.82])\n by FMSMGA003.fm.intel.com with ESMTP; 11 Sep 2020 06:16:18 -0700"
        ],
        "IronPort-SDR": [
            "\n DXncQ/Z2w4SqKxndNnCf5P2Bpm6ZINWPNXk7eI1zzDDP89eRBQpquGNVa1Ma0KhOQe9BJrK+TR\n kOUNKU3CaUHw==",
            "\n 44hIdkjDVr8J/CbNf3Epi+hO/hDCXYP111UPyz3VaiqGgmiojjhp32l2STYY+0DxR9JzNyLInK\n NKHPs7TaN7yQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9740\"; a=\"146482204\"",
            "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"146482204\"",
            "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"342296563\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "ferruh.yigit@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Bruce Allan <bruce.w.allan@intel.com>",
        "Date": "Fri, 11 Sep 2020 21:19:27 +0800",
        "Message-Id": "<20200911131954.15999-14-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20200911131954.15999-1-qi.z.zhang@intel.com>",
        "References": "<20200907112826.48493-1-qi.z.zhang@intel.com>\n <20200911131954.15999-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 13/40] net/ice/base: introduce and use for\n\teach bit iterator",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "A number of code flows iterate over a block of memory to do something for\nevery bit set in that memory. Use existing bit operations in a new iterator\nmacro to make those code flows cleaner.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_acl_ctrl.c  | 17 +++-----\n drivers/net/ice/base/ice_bitops.h    |  5 +++\n drivers/net/ice/base/ice_flex_pipe.c | 66 ++++++++++++++-----------------\n drivers/net/ice/base/ice_flow.c      | 75 +++++++++++-------------------------\n drivers/net/ice/base/ice_switch.c    | 59 ++++++++++++----------------\n 5 files changed, 85 insertions(+), 137 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c\nindex a732397ce..49c4f3675 100644\n--- a/drivers/net/ice/base/ice_acl_ctrl.c\n+++ b/drivers/net/ice/base/ice_acl_ctrl.c\n@@ -1028,9 +1028,8 @@ ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen,\n \tentry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);\n \tidx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + entry_idx);\n \n-\ti = ice_find_first_bit(scen->act_mem_bitmap,\n-\t\t\t       ICE_AQC_MAX_ACTION_MEMORIES);\n-\twhile (i < ICE_AQC_MAX_ACTION_MEMORIES) {\n+\tice_for_each_set_bit(i, scen->act_mem_bitmap,\n+\t\t\t     ICE_AQC_MAX_ACTION_MEMORIES) {\n \t\tstruct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];\n \n \t\tif (actx_idx >= acts_cnt)\n@@ -1057,9 +1056,6 @@ ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen,\n \t\t\t}\n \t\t\tactx_idx++;\n \t\t}\n-\n-\t\ti = ice_find_next_bit(scen->act_mem_bitmap,\n-\t\t\t\t      ICE_AQC_MAX_ACTION_MEMORIES, i + 1);\n \t}\n \n \tif (!status && actx_idx < acts_cnt)\n@@ -1111,9 +1107,9 @@ ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)\n \t}\n \n \tice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);\n-\ti = ice_find_first_bit(scen->act_mem_bitmap,\n-\t\t\t       ICE_AQC_MAX_ACTION_MEMORIES);\n-\twhile (i < ICE_AQC_MAX_ACTION_MEMORIES) {\n+\n+\tice_for_each_set_bit(i, scen->act_mem_bitmap,\n+\t\t\t     ICE_AQC_MAX_ACTION_MEMORIES) {\n \t\tstruct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];\n \n \t\tif (mem->member_of_tcam >= entry_tcam &&\n@@ -1126,9 +1122,6 @@ ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)\n \t\t\t\t\t  \"program actpair failed.status: %d\\n\",\n \t\t\t\t\t  status);\n \t\t}\n-\n-\t\ti = ice_find_next_bit(scen->act_mem_bitmap,\n-\t\t\t\t      ICE_AQC_MAX_ACTION_MEMORIES, i + 1);\n \t}\n \n \tice_acl_scen_free_entry_idx(scen, entry_idx);\ndiff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h\nindex a56d55455..f954a7436 100644\n--- a/drivers/net/ice/base/ice_bitops.h\n+++ b/drivers/net/ice/base/ice_bitops.h\n@@ -346,6 +346,11 @@ static inline u16 ice_find_first_bit(const ice_bitmap_t *bitmap, u16 size)\n \treturn ice_find_next_bit(bitmap, size, 0);\n }\n \n+#define ice_for_each_set_bit(_bitpos, _addr, _maxlen)\t\\\n+\tfor ((_bitpos) = ice_find_first_bit((_addr), (_maxlen)); \\\n+\t     (_bitpos) < (_maxlen); \\\n+\t     (_bitpos) = ice_find_next_bit((_addr), (_maxlen), (_bitpos) + 1))\n+\n /**\n  * ice_is_any_bit_set - Return true of any bit in the bitmap is set\n  * @bitmap: the bitmap to check\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex a08390992..3df7b8596 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -4665,50 +4665,42 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\t\tbyte++;\n \t\t\tcontinue;\n \t\t}\n+\n \t\t/* Examine 8 bits per byte */\n-\t\tfor (bit = 0; bit < 8; bit++) {\n-\t\t\tif (ptypes[byte] & BIT(bit)) {\n-\t\t\t\tu16 ptype;\n-\t\t\t\tu8 ptg;\n-\t\t\t\tu8 m;\n+\t\tice_for_each_set_bit(bit, (ice_bitmap_t *)&ptypes[byte],\n+\t\t\t\t     BITS_PER_BYTE) {\n+\t\t\tu16 ptype;\n+\t\t\tu8 ptg;\n \n-\t\t\t\tptype = byte * BITS_PER_BYTE + bit;\n+\t\t\tptype = byte * BITS_PER_BYTE + bit;\n \n-\t\t\t\t/* The package should place all ptypes in a\n-\t\t\t\t * non-zero PTG, so the following call should\n-\t\t\t\t * never fail.\n-\t\t\t\t */\n-\t\t\t\tif (ice_ptg_find_ptype(hw, blk, ptype, &ptg))\n-\t\t\t\t\tcontinue;\n+\t\t\t/* The package should place all ptypes in a non-zero\n+\t\t\t * PTG, so the following call should never fail.\n+\t\t\t */\n+\t\t\tif (ice_ptg_find_ptype(hw, blk, ptype, &ptg))\n+\t\t\t\tcontinue;\n \n-\t\t\t\t/* If PTG is already added, skip and continue */\n-\t\t\t\tif (ice_is_bit_set(ptgs_used, ptg))\n-\t\t\t\t\tcontinue;\n+\t\t\t/* If PTG is already added, skip and continue */\n+\t\t\tif (ice_is_bit_set(ptgs_used, ptg))\n+\t\t\t\tcontinue;\n \n-\t\t\t\tice_set_bit(ptg, ptgs_used);\n-\t\t\t\t/* Check to see there are any attributes for\n-\t\t\t\t * this ptype, and add them if found.\n+\t\t\tice_set_bit(ptg, ptgs_used);\n+\t\t\t/* Check to see there are any attributes for this\n+\t\t\t * ptype, and add them if found.\n+\t\t\t */\n+\t\t\tstatus = ice_add_prof_attrib(prof, ptg, ptype, attr,\n+\t\t\t\t\t\t     attr_cnt);\n+\t\t\tif (status == ICE_ERR_MAX_LIMIT)\n+\t\t\t\tbreak;\n+\t\t\tif (status) {\n+\t\t\t\t/* This is simple a ptype/PTG with no\n+\t\t\t\t * attribute\n \t\t\t\t */\n-\t\t\t\tstatus = ice_add_prof_attrib(prof, ptg, ptype,\n-\t\t\t\t\t\t\t     attr, attr_cnt);\n-\t\t\t\tif (status == ICE_ERR_MAX_LIMIT)\n-\t\t\t\t\tbreak;\n-\t\t\t\tif (status) {\n-\t\t\t\t\t/* This is simple a ptype/PTG with no\n-\t\t\t\t\t * attribute\n-\t\t\t\t\t */\n-\t\t\t\t\tprof->ptg[prof->ptg_cnt] = ptg;\n-\t\t\t\t\tprof->attr[prof->ptg_cnt].flags = 0;\n-\t\t\t\t\tprof->attr[prof->ptg_cnt].mask = 0;\n-\n-\t\t\t\t\tif (++prof->ptg_cnt >=\n-\t\t\t\t\t    ICE_MAX_PTG_PER_PROFILE)\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t}\n+\t\t\t\tprof->ptg[prof->ptg_cnt] = ptg;\n+\t\t\t\tprof->attr[prof->ptg_cnt].flags = 0;\n+\t\t\t\tprof->attr[prof->ptg_cnt].mask = 0;\n \n-\t\t\t\t/* nothing left in byte, then exit */\n-\t\t\t\tm = ~(u8)((1 << (bit + 1)) - 1);\n-\t\t\t\tif (!(ptypes[byte] & m))\n+\t\t\t\tif (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)\n \t\t\t\t\tbreak;\n \t\t\t}\n \t\t}\ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 0169da995..98c07778b 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1340,16 +1340,12 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,\n \t\tu64 match = params->prof->segs[i].match;\n \t\tenum ice_flow_field j;\n \n-\t\tfor (j = 0; j < ICE_FLOW_FIELD_IDX_MAX && match; j++) {\n-\t\t\tconst u64 bit = BIT_ULL(j);\n-\n-\t\t\tif (match & bit) {\n-\t\t\t\tstatus = ice_flow_xtract_fld(hw, params, i, j,\n-\t\t\t\t\t\t\t     match);\n-\t\t\t\tif (status)\n-\t\t\t\t\treturn status;\n-\t\t\t\tmatch &= ~bit;\n-\t\t\t}\n+\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&match,\n+\t\t\t\t     ICE_FLOW_FIELD_IDX_MAX) {\n+\t\t\tstatus = ice_flow_xtract_fld(hw, params, i, j, match);\n+\t\t\tif (status)\n+\t\t\t\treturn status;\n+\t\t\tice_clear_bit(j, (ice_bitmap_t *)&match);\n \t\t}\n \n \t\t/* Process raw matching bytes */\n@@ -1406,17 +1402,12 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)\n \n \tfor (i = 0; i < params->prof->segs_cnt; i++) {\n \t\tstruct ice_flow_seg_info *seg = &params->prof->segs[i];\n-\t\tu64 match = seg->match;\n \t\tu8 j;\n \n-\t\tfor (j = 0; j < ICE_FLOW_FIELD_IDX_MAX && match; j++) {\n-\t\t\tstruct ice_flow_fld_info *fld;\n-\t\t\tconst u64 bit = BIT_ULL(j);\n+\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\t\t\t     ICE_FLOW_FIELD_IDX_MAX) {\n+\t\t\tstruct ice_flow_fld_info *fld = &seg->fields[j];\n \n-\t\t\tif (!(match & bit))\n-\t\t\t\tcontinue;\n-\n-\t\t\tfld = &seg->fields[j];\n \t\t\tfld->entry.mask = ICE_FLOW_FLD_OFF_INVAL;\n \n \t\t\tif (fld->type == ICE_FLOW_FLD_TYPE_RANGE) {\n@@ -1448,8 +1439,6 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)\n \t\t\t\tfld->entry.val = index;\n \t\t\t\tindex += fld->entry.last;\n \t\t\t}\n-\n-\t\t\tmatch &= ~bit;\n \t\t}\n \n \t\tfor (j = 0; j < seg->raws_cnt; j++) {\n@@ -2028,25 +2017,18 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof)\n \n \t\tfor (i = 0; i < prof->segs_cnt; i++) {\n \t\t\tstruct ice_flow_seg_info *seg = &prof->segs[i];\n-\t\t\tu64 match = seg->match;\n \t\t\tu16 j;\n \n-\t\t\tfor (j = 0; j < ICE_FLOW_FIELD_IDX_MAX && match; j++) {\n-\t\t\t\tconst u64 bit = BIT_ULL(j);\n-\n-\t\t\t\tif (!(match & bit))\n-\t\t\t\t\tcontinue;\n-\n+\t\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\t\t\t\t     ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\t\tinfo = &seg->fields[j];\n \n \t\t\t\tif (info->type == ICE_FLOW_FLD_TYPE_RANGE)\n \t\t\t\t\tbuf.word_selection[info->entry.val] =\n-\t\t\t\t\t\t\t\tinfo->xtrct.idx;\n+\t\t\t\t\t\tinfo->xtrct.idx;\n \t\t\t\telse\n \t\t\t\t\tice_flow_acl_set_xtrct_seq_fld(&buf,\n \t\t\t\t\t\t\t\t       info);\n-\n-\t\t\t\tmatch &= ~bit;\n \t\t\t}\n \n \t\t\tfor (j = 0; j < seg->raws_cnt; j++) {\n@@ -2549,17 +2531,11 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,\n \n \tfor (i = 0; i < prof->segs_cnt; i++) {\n \t\tstruct ice_flow_seg_info *seg = &prof->segs[i];\n-\t\tu64 match = seg->match;\n-\t\tu16 j;\n-\n-\t\tfor (j = 0; j < ICE_FLOW_FIELD_IDX_MAX && match; j++) {\n-\t\t\tstruct ice_flow_fld_info *info;\n-\t\t\tconst u64 bit = BIT_ULL(j);\n-\n-\t\t\tif (!(match & bit))\n-\t\t\t\tcontinue;\n+\t\tu8 j;\n \n-\t\t\tinfo = &seg->fields[j];\n+\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\t\t\t     ICE_FLOW_FIELD_IDX_MAX) {\n+\t\t\tstruct ice_flow_fld_info *info = &seg->fields[j];\n \n \t\t\tif (info->type == ICE_FLOW_FLD_TYPE_RANGE)\n \t\t\t\tice_flow_acl_frmt_entry_range(j, info,\n@@ -2568,8 +2544,6 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,\n \t\t\telse\n \t\t\t\tice_flow_acl_frmt_entry_fld(j, info, buf,\n \t\t\t\t\t\t\t    dontcare, data);\n-\n-\t\t\tmatch &= ~bit;\n \t\t}\n \n \t\tfor (j = 0; j < seg->raws_cnt; j++) {\n@@ -3271,20 +3245,15 @@ static enum ice_status\n ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u64 hash_fields,\n \t\t\t  u32 flow_hdr)\n {\n-\tu64 val = hash_fields;\n+\tu64 val;\n \tu8 i;\n \n-\tfor (i = 0; val && i < ICE_FLOW_FIELD_IDX_MAX; i++) {\n-\t\tu64 bit = BIT_ULL(i);\n+\tice_for_each_set_bit(i, (ice_bitmap_t *)&hash_fields,\n+\t\t\t     ICE_FLOW_FIELD_IDX_MAX)\n+\t\tice_flow_set_fld(segs, (enum ice_flow_field)i,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL, ICE_FLOW_FLD_OFF_INVAL,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL, false);\n \n-\t\tif (val & bit) {\n-\t\t\tice_flow_set_fld(segs, (enum ice_flow_field)i,\n-\t\t\t\t\t ICE_FLOW_FLD_OFF_INVAL,\n-\t\t\t\t\t ICE_FLOW_FLD_OFF_INVAL,\n-\t\t\t\t\t ICE_FLOW_FLD_OFF_INVAL, false);\n-\t\t\tval &= ~bit;\n-\t\t}\n-\t}\n \tICE_FLOW_SET_HDRS(segs, flow_hdr);\n \n \tif (segs->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS &\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex ecb411714..f2d8514be 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -1374,9 +1374,8 @@ static void ice_get_recp_to_prof_map(struct ice_hw *hw)\n \t\t\tcontinue;\n \t\tice_cp_bitmap(profile_to_recipe[i], r_bitmap,\n \t\t\t      ICE_MAX_NUM_RECIPES);\n-\t\tfor (j = 0; j < ICE_MAX_NUM_RECIPES; j++)\n-\t\t\tif (ice_is_bit_set(r_bitmap, j))\n-\t\t\t\tice_set_bit(i, recipe_to_profile[j]);\n+\t\tice_for_each_set_bit(j, r_bitmap, ICE_MAX_NUM_RECIPES)\n+\t\t\tice_set_bit(i, recipe_to_profile[j]);\n \t}\n }\n \n@@ -5946,26 +5945,21 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,\n \t * the set of recipes that our recipe may collide with. Also, determine\n \t * what possible result indexes are usable given this set of profiles.\n \t */\n-\tbit = 0;\n-\twhile (ICE_MAX_NUM_PROFILES >\n-\t       (bit = ice_find_next_bit(profiles, ICE_MAX_NUM_PROFILES, bit))) {\n+\tice_for_each_set_bit(bit, profiles, ICE_MAX_NUM_PROFILES) {\n \t\tice_or_bitmap(recipes, recipes, profile_to_recipe[bit],\n \t\t\t      ICE_MAX_NUM_RECIPES);\n \t\tice_and_bitmap(possible_idx, possible_idx,\n \t\t\t       hw->switch_info->prof_res_bm[bit],\n \t\t\t       ICE_MAX_FV_WORDS);\n-\t\tbit++;\n \t}\n \n \t/* For each recipe that our new recipe may collide with, determine\n \t * which indexes have been used.\n \t */\n-\tfor (bit = 0; bit < ICE_MAX_NUM_RECIPES; bit++)\n-\t\tif (ice_is_bit_set(recipes, bit)) {\n-\t\t\tice_or_bitmap(used_idx, used_idx,\n-\t\t\t\t      hw->switch_info->recp_list[bit].res_idxs,\n-\t\t\t\t      ICE_MAX_FV_WORDS);\n-\t\t}\n+\tice_for_each_set_bit(bit, recipes, ICE_MAX_NUM_RECIPES)\n+\t\tice_or_bitmap(used_idx, used_idx,\n+\t\t\t      hw->switch_info->recp_list[bit].res_idxs,\n+\t\t\t      ICE_MAX_FV_WORDS);\n \n \tice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS);\n \n@@ -6650,18 +6644,17 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \tif (LIST_EMPTY(&rm->fv_list)) {\n \t\tu16 j;\n \n-\t\tfor (j = 0; j < ICE_MAX_NUM_PROFILES; j++)\n-\t\t\tif (ice_is_bit_set(fv_bitmap, j)) {\n-\t\t\t\tstruct ice_sw_fv_list_entry *fvl;\n-\n-\t\t\t\tfvl = (struct ice_sw_fv_list_entry *)\n-\t\t\t\t\tice_malloc(hw, sizeof(*fvl));\n-\t\t\t\tif (!fvl)\n-\t\t\t\t\tgoto err_unroll;\n-\t\t\t\tfvl->fv_ptr = NULL;\n-\t\t\t\tfvl->profile_id = j;\n-\t\t\t\tLIST_ADD(&fvl->list_entry, &rm->fv_list);\n-\t\t\t}\n+\t\tice_for_each_set_bit(j, fv_bitmap, ICE_MAX_NUM_PROFILES) {\n+\t\t\tstruct ice_sw_fv_list_entry *fvl;\n+\n+\t\t\tfvl = (struct ice_sw_fv_list_entry *)\n+\t\t\t\tice_malloc(hw, sizeof(*fvl));\n+\t\t\tif (!fvl)\n+\t\t\t\tgoto err_unroll;\n+\t\t\tfvl->fv_ptr = NULL;\n+\t\t\tfvl->profile_id = j;\n+\t\t\tLIST_ADD(&fvl->list_entry, &rm->fv_list);\n+\t\t}\n \t}\n \n \t/* get bitmap of all profiles the recipe will be associated with */\n@@ -6716,10 +6709,9 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\t\t      ICE_MAX_NUM_RECIPES);\n \n \t\t/* Update recipe to profile bitmap array */\n-\t\tfor (j = 0; j < ICE_MAX_NUM_RECIPES; j++)\n-\t\t\tif (ice_is_bit_set(r_bitmap, j))\n-\t\t\t\tice_set_bit((u16)fvit->profile_id,\n-\t\t\t\t\t    recipe_to_profile[j]);\n+\t\tice_for_each_set_bit(j, rm->r_bitmap, ICE_MAX_NUM_RECIPES)\n+\t\t\tice_set_bit((u16)fvit->profile_id,\n+\t\t\t\t    recipe_to_profile[j]);\n \t}\n \n \t*rid = rm->root_rid;\n@@ -7909,6 +7901,7 @@ ice_replay_fltr(struct ice_hw *hw, u8 recp_id, struct LIST_HEAD_TYPE *list_head)\n \tLIST_FOR_EACH_ENTRY(itr, &l_head, ice_fltr_mgmt_list_entry,\n \t\t\t    list_entry) {\n \t\tstruct ice_fltr_list_entry f_entry;\n+\t\tu16 vsi_handle;\n \n \t\tf_entry.fltr_info = itr->fltr_info;\n \t\tif (itr->vsi_count < 2 && recp_id != ICE_SW_LKUP_VLAN) {\n@@ -7920,12 +7913,8 @@ ice_replay_fltr(struct ice_hw *hw, u8 recp_id, struct LIST_HEAD_TYPE *list_head)\n \t\t}\n \n \t\t/* Add a filter per VSI separately */\n-\t\twhile (1) {\n-\t\t\tu16 vsi_handle;\n-\n-\t\t\tvsi_handle =\n-\t\t\t\tice_find_first_bit(itr->vsi_list_info->vsi_map,\n-\t\t\t\t\t\t   ICE_MAX_VSI);\n+\t\tice_for_each_set_bit(vsi_handle, itr->vsi_list_info->vsi_map,\n+\t\t\t\t     ICE_MAX_VSI) {\n \t\t\tif (!ice_is_vsi_valid(hw, vsi_handle))\n \t\t\t\tbreak;\n \n",
    "prefixes": [
        "v2",
        "13/40"
    ]
}