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GET /api/patches/77321/?format=api
{ "id": 77321, "url": "http://patches.dpdk.org/api/patches/77321/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599801997-19880-3-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599801997-19880-3-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599801997-19880-3-git-send-email-phil.yang@arm.com", "date": "2020-09-11T05:26:37", "name": "[v2,2/2] eal: remove RTE CIO barriers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f1872954bb5d1facb23beace06fa8f248a390d39", "submitter": { "id": 833, "url": "http://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599801997-19880-3-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 12128, "url": "http://patches.dpdk.org/api/series/12128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12128", "date": "2020-09-11T05:26:35", "name": "remove RTE CIO barriers", "version": 2, "mbox": "http://patches.dpdk.org/series/12128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77321/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/77321/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A7692A04B5;\n\tFri, 11 Sep 2020 07:27:00 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CC9961C0D4;\n\tFri, 11 Sep 2020 07:26:54 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 7B4B01C0D4\n for <dev@dpdk.org>; Fri, 11 Sep 2020 07:26:53 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06D48106F;\n Thu, 10 Sep 2020 22:26:53 -0700 (PDT)", "from phil-VirtualBox.shanghai.arm.com\n (phil-VirtualBox.shanghai.arm.com [10.169.182.49])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2135E3F66E;\n Thu, 10 Sep 2020 22:26:48 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "dev@dpdk.org", "Cc": "Honnappa.Nagarahalli@arm.com, Ruifeng.Wang@arm.com, joyce.kong@arm.com,\n nd@arm.com, John McNamara <john.mcnamara@intel.com>,\n Marko Kovacevic <marko.kovacevic@intel.com>,\n Jan Viktorin <viktorin@rehivetech.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Jerin Jacob <jerinj@marvell.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>", "Date": "Fri, 11 Sep 2020 13:26:37 +0800", "Message-Id": "<1599801997-19880-3-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1599801997-19880-1-git-send-email-phil.yang@arm.com>", "References": "<1598258441-15696-1-git-send-email-phil.yang@arm.com>\n <1599801997-19880-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH v2 2/2] eal: remove RTE CIO barriers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove the deprecated rte_cio_[rw]mb APIs.\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n doc/guides/rel_notes/release_20_11.rst | 3 +++\n lib/librte_eal/arm/include/rte_atomic_32.h | 4 ---\n lib/librte_eal/arm/include/rte_atomic_64.h | 4 ---\n lib/librte_eal/include/generic/rte_atomic.h | 39 -----------------------------\n lib/librte_eal/ppc/include/rte_atomic.h | 4 ---\n lib/librte_eal/x86/include/rte_atomic.h | 4 ---\n 6 files changed, 3 insertions(+), 55 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex df227a1..7090caf 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -84,6 +84,9 @@ API Changes\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* eal: The ``rte_cio_rmb()`` and ``rte_cio_wmb()`` were deprecated since\n+ 20.08 and are removed in this release.\n+\n \n ABI Changes\n -----------\ndiff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/arm/include/rte_atomic_32.h\nindex 368f10c..9d0568d 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_32.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_32.h\n@@ -33,10 +33,6 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n-#define rte_cio_wmb() rte_wmb()\n-\n-#define rte_cio_rmb() rte_rmb()\n-\n static __rte_always_inline void\n rte_atomic_thread_fence(int memory_order)\n {\ndiff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h\nindex 5cae52d..c518559 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_64.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_64.h\n@@ -37,10 +37,6 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n-#define rte_cio_wmb() rte_wmb()\n-\n-#define rte_cio_rmb() rte_rmb()\n-\n static __rte_always_inline void\n rte_atomic_thread_fence(int memory_order)\n {\ndiff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal/include/generic/rte_atomic.h\nindex 95270f1..d1255b2 100644\n--- a/lib/librte_eal/include/generic/rte_atomic.h\n+++ b/lib/librte_eal/include/generic/rte_atomic.h\n@@ -107,45 +107,6 @@ static inline void rte_io_wmb(void);\n static inline void rte_io_rmb(void);\n ///@}\n \n-/** @name Coherent I/O Memory Barrier\n- *\n- * Coherent I/O memory barrier is a lightweight version of I/O memory\n- * barriers which are system-wide data synchronization barriers. This\n- * is for only coherent memory domain between lcore and I/O device but\n- * it is same as the I/O memory barriers in most of architectures.\n- * However, some architecture provides even lighter barriers which are\n- * somewhere in between I/O memory barriers and SMP memory barriers.\n- * For example, in case of ARMv8, DMB(data memory barrier) instruction\n- * can have different shareability domains - inner-shareable and\n- * outer-shareable. And inner-shareable DMB fits for SMP memory\n- * barriers and outer-shareable DMB for coherent I/O memory barriers,\n- * which acts on coherent memory.\n- *\n- * In most cases, I/O memory barriers are safer but if operations are\n- * on coherent memory instead of incoherent MMIO region of a device,\n- * then coherent I/O memory barriers can be used and this could bring\n- * performance gain depending on architectures.\n- */\n-///@{\n-/**\n- * Write memory barrier for coherent memory between lcore and I/O device\n- *\n- * Guarantees that the STORE operations on coherent memory that\n- * precede the rte_cio_wmb() call are visible to I/O device before the\n- * STORE operations that follow it.\n- */\n-static inline void rte_cio_wmb(void);\n-\n-/**\n- * Read memory barrier for coherent memory between lcore and I/O device\n- *\n- * Guarantees that the LOAD operations on coherent memory updated by\n- * I/O device that precede the rte_cio_rmb() call are visible to CPU\n- * before the LOAD operations that follow it.\n- */\n-static inline void rte_cio_rmb(void);\n-///@}\n-\n #endif /* __DOXYGEN__ */\n \n /**\ndiff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc/include/rte_atomic.h\nindex 527fcaf..a919899 100644\n--- a/lib/librte_eal/ppc/include/rte_atomic.h\n+++ b/lib/librte_eal/ppc/include/rte_atomic.h\n@@ -36,10 +36,6 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n-#define rte_cio_wmb() rte_wmb()\n-\n-#define rte_cio_rmb() rte_rmb()\n-\n static __rte_always_inline void\n rte_atomic_thread_fence(int memory_order)\n {\ndiff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86/include/rte_atomic.h\nindex 62ea393..b7d6b06 100644\n--- a/lib/librte_eal/x86/include/rte_atomic.h\n+++ b/lib/librte_eal/x86/include/rte_atomic.h\n@@ -79,10 +79,6 @@ rte_smp_mb(void)\n \n #define rte_io_rmb() rte_compiler_barrier()\n \n-#define rte_cio_wmb() rte_compiler_barrier()\n-\n-#define rte_cio_rmb() rte_compiler_barrier()\n-\n /**\n * Synchronization fence between threads based on the specified memory order.\n *\n", "prefixes": [ "v2", "2/2" ] }