Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/77315/?format=api
{ "id": 77315, "url": "http://patches.dpdk.org/api/patches/77315/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599794967-17500-4-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599794967-17500-4-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599794967-17500-4-git-send-email-phil.yang@arm.com", "date": "2020-09-11T03:29:26", "name": "[3/4] power: use C11 atomic builtins for power in use state update", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4ce4358598c4074a09f011efb06b365c5d780c1b", "submitter": { "id": 833, "url": "http://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599794967-17500-4-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 12125, "url": "http://patches.dpdk.org/api/series/12125/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12125", "date": "2020-09-11T03:29:23", "name": "use C11 atomic builtins for libs", "version": 1, "mbox": "http://patches.dpdk.org/series/12125/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77315/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5DAABA04B5;\n\tFri, 11 Sep 2020 05:29:52 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B5B231C0DA;\n\tFri, 11 Sep 2020 05:29:38 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id F30831C0DA\n for <dev@dpdk.org>; Fri, 11 Sep 2020 05:29:36 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72D6B11B3;\n Thu, 10 Sep 2020 20:29:36 -0700 (PDT)", "from phil-VirtualBox.shanghai.arm.com\n (phil-VirtualBox.shanghai.arm.com [10.169.182.49])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9F36D3F73C;\n Thu, 10 Sep 2020 20:29:34 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "dev@dpdk.org", "Cc": "Honnappa.Nagarahalli@arm.com, Ruifeng.Wang@arm.com, nd@arm.com,\n David Hunt <david.hunt@intel.com>", "Date": "Fri, 11 Sep 2020 11:29:26 +0800", "Message-Id": "<1599794967-17500-4-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1599794967-17500-1-git-send-email-phil.yang@arm.com>", "References": "<1599794967-17500-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH 3/4] power: use C11 atomic builtins for power in\n\tuse state update", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Since rte_atomicXX APIs are not allowed to be used, use C11 atomic\nbuiltins for power in use state update.\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n lib/librte_power/power_acpi_cpufreq.c | 45 +++++++++++++++++++++++++--------\n lib/librte_power/power_pstate_cpufreq.c | 45 +++++++++++++++++++++++++--------\n 2 files changed, 70 insertions(+), 20 deletions(-)", "diff": "diff --git a/lib/librte_power/power_acpi_cpufreq.c b/lib/librte_power/power_acpi_cpufreq.c\nindex 583815a..84a9d75 100644\n--- a/lib/librte_power/power_acpi_cpufreq.c\n+++ b/lib/librte_power/power_acpi_cpufreq.c\n@@ -12,7 +12,6 @@\n #include <signal.h>\n #include <limits.h>\n \n-#include <rte_atomic.h>\n #include <rte_memcpy.h>\n #include <rte_memory.h>\n #include <rte_string_fns.h>\n@@ -86,7 +85,7 @@ struct rte_power_info {\n \tFILE *f; /**< FD of scaling_setspeed */\n \tchar governor_ori[32]; /**< Original governor name */\n \tuint32_t curr_idx; /**< Freq index in freqs array */\n-\tvolatile uint32_t state; /**< Power in use state */\n+\tuint32_t state; /**< Power in use state */\n \tuint16_t turbo_available; /**< Turbo Boost available */\n \tuint16_t turbo_enable; /**< Turbo Boost enable/disable */\n } __rte_cache_aligned;\n@@ -300,6 +299,7 @@ int\n power_acpi_cpufreq_init(unsigned int lcore_id)\n {\n \tstruct rte_power_info *pi;\n+\tuint32_t exp_state;\n \n \tif (lcore_id >= RTE_MAX_LCORE) {\n \t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n@@ -308,8 +308,16 @@ power_acpi_cpufreq_init(unsigned int lcore_id)\n \t}\n \n \tpi = &lcore_power_info[lcore_id];\n-\tif (rte_atomic32_cmpset(&(pi->state), POWER_IDLE, POWER_ONGOING)\n-\t\t\t== 0) {\n+\texp_state = POWER_IDLE;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n \t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n \t\t\t\t\"in use\\n\", lcore_id);\n \t\treturn -1;\n@@ -346,12 +354,16 @@ power_acpi_cpufreq_init(unsigned int lcore_id)\n \n \tRTE_LOG(INFO, POWER, \"Initialized successfully for lcore %u \"\n \t\t\t\"power management\\n\", lcore_id);\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_USED);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_USED,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn 0;\n \n fail:\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_UNKNOWN,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn -1;\n }\n@@ -408,6 +420,7 @@ int\n power_acpi_cpufreq_exit(unsigned int lcore_id)\n {\n \tstruct rte_power_info *pi;\n+\tuint32_t exp_state;\n \n \tif (lcore_id >= RTE_MAX_LCORE) {\n \t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n@@ -415,8 +428,16 @@ power_acpi_cpufreq_exit(unsigned int lcore_id)\n \t\treturn -1;\n \t}\n \tpi = &lcore_power_info[lcore_id];\n-\tif (rte_atomic32_cmpset(&(pi->state), POWER_USED, POWER_ONGOING)\n-\t\t\t== 0) {\n+\texp_state = POWER_USED;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n \t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n \t\t\t\t\"not used\\n\", lcore_id);\n \t\treturn -1;\n@@ -436,12 +457,16 @@ power_acpi_cpufreq_exit(unsigned int lcore_id)\n \tRTE_LOG(INFO, POWER, \"Power management of lcore %u has exited from \"\n \t\t\t\"'userspace' mode and been set back to the \"\n \t\t\t\"original\\n\", lcore_id);\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_IDLE);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_IDLE,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn 0;\n \n fail:\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_UNKNOWN,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn -1;\n }\ndiff --git a/lib/librte_power/power_pstate_cpufreq.c b/lib/librte_power/power_pstate_cpufreq.c\nindex 2526441..e3126d3 100644\n--- a/lib/librte_power/power_pstate_cpufreq.c\n+++ b/lib/librte_power/power_pstate_cpufreq.c\n@@ -14,7 +14,6 @@\n #include <errno.h>\n #include <inttypes.h>\n \n-#include <rte_atomic.h>\n #include <rte_memcpy.h>\n #include <rte_memory.h>\n #include <rte_string_fns.h>\n@@ -100,7 +99,7 @@ struct pstate_power_info {\n \tuint32_t non_turbo_max_ratio; /**< Non Turbo Max ratio */\n \tuint32_t sys_max_freq; /**< system wide max freq */\n \tuint32_t core_base_freq; /**< core base freq */\n-\tvolatile uint32_t state; /**< Power in use state */\n+\tuint32_t state; /**< Power in use state */\n \tuint16_t turbo_available; /**< Turbo Boost available */\n \tuint16_t turbo_enable; /**< Turbo Boost enable/disable */\n \tuint16_t priority_core; /**< High Performance core */\n@@ -542,6 +541,7 @@ int\n power_pstate_cpufreq_init(unsigned int lcore_id)\n {\n \tstruct pstate_power_info *pi;\n+\tuint32_t exp_state;\n \n \tif (lcore_id >= RTE_MAX_LCORE) {\n \t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceed %u\\n\",\n@@ -550,8 +550,16 @@ power_pstate_cpufreq_init(unsigned int lcore_id)\n \t}\n \n \tpi = &lcore_power_info[lcore_id];\n-\tif (rte_atomic32_cmpset(&(pi->state), POWER_IDLE, POWER_ONGOING)\n-\t\t\t== 0) {\n+\texp_state = POWER_IDLE;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n \t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n \t\t\t\t\"in use\\n\", lcore_id);\n \t\treturn -1;\n@@ -588,12 +596,16 @@ power_pstate_cpufreq_init(unsigned int lcore_id)\n \n \tRTE_LOG(INFO, POWER, \"Initialized successfully for lcore %u \"\n \t\t\t\"power management\\n\", lcore_id);\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_USED);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_USED,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn 0;\n \n fail:\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_UNKNOWN,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn -1;\n }\n@@ -602,6 +614,7 @@ int\n power_pstate_cpufreq_exit(unsigned int lcore_id)\n {\n \tstruct pstate_power_info *pi;\n+\tuint32_t exp_state;\n \n \tif (lcore_id >= RTE_MAX_LCORE) {\n \t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n@@ -610,8 +623,16 @@ power_pstate_cpufreq_exit(unsigned int lcore_id)\n \t}\n \tpi = &lcore_power_info[lcore_id];\n \n-\tif (rte_atomic32_cmpset(&(pi->state), POWER_USED, POWER_ONGOING)\n-\t\t\t== 0) {\n+\texp_state = POWER_USED;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are under done the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n \t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n \t\t\t\t\"not used\\n\", lcore_id);\n \t\treturn -1;\n@@ -633,12 +654,16 @@ power_pstate_cpufreq_exit(unsigned int lcore_id)\n \tRTE_LOG(INFO, POWER, \"Power management of lcore %u has exited from \"\n \t\t\t\"'performance' mode and been set back to the \"\n \t\t\t\"original\\n\", lcore_id);\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_IDLE);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_IDLE,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn 0;\n \n fail:\n-\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n+\texp_state = POWER_ONGOING;\n+\t__atomic_compare_exchange_n(&(pi->state), &exp_state, POWER_UNKNOWN,\n+\t\t\t\t 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n \n \treturn -1;\n }\n", "prefixes": [ "3/4" ] }