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GET /api/patches/77276/?format=api
{ "id": 77276, "url": "http://patches.dpdk.org/api/patches/77276/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911015603.88359-15-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200911015603.88359-15-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200911015603.88359-15-ajit.khaparde@broadcom.com", "date": "2020-09-11T01:55:52", "name": "[14/25] net/bnxt: move IF tbl from tunneled to direct HWRM msg", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "730ad1bbedff1fe0914925441d6b2f926c232c35", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911015603.88359-15-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 12116, "url": "http://patches.dpdk.org/api/series/12116/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12116", "date": "2020-09-11T01:55:38", "name": "patchset for bnxt", "version": 1, "mbox": "http://patches.dpdk.org/series/12116/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77276/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/77276/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C25A1A04B5;\n\tFri, 11 Sep 2020 03:58:47 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DD1431C0D9;\n\tFri, 11 Sep 2020 03:57:18 +0200 (CEST)", "from mail-pg1-f228.google.com (mail-pg1-f228.google.com\n [209.85.215.228]) by dpdk.org (Postfix) with ESMTP id 1E2D91C0CC\n for <dev@dpdk.org>; Fri, 11 Sep 2020 03:57:17 +0200 (CEST)", "by mail-pg1-f228.google.com with SMTP id s65so4392516pgb.0\n for <dev@dpdk.org>; Thu, 10 Sep 2020 18:57:17 -0700 (PDT)", "from localhost.localdomain ([192.19.223.252])\n by smtp-relay.gmail.com with ESMTPS id cl6sm80986pjb.15.2020.09.10.18.57.10\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Thu, 10 Sep 2020 18:57:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; 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6vNhz+ANYUgVI7jgFyeYpky4U73TU5GfMgCXyeQdbY1AcrmCzifL2SxEq5HmZ/dz/8Sv\n TDug==", "X-Gm-Message-State": "AOAM531zwZY4GfthfUh7WGxQIlh1KLxKI/fERgTYZ+9V17klpCVQ9Pl9\n 2yTB51v5mUvtaQAgA0m3G4dNdGbcAUFWBcwrblTi1gQTvCjb/nOpXXirmpQKEAYkp9wk2ghK33z\n St12ecxfREAswDzfZWiwffVHnYAsedCVt3Z2IA9HuRD3KI+k/9+WxPO/jfBzEY8qE7CwmNNA315\n 1lMg==", "X-Google-Smtp-Source": "\n ABdhPJy3h97YvwPqGSzCLMC8+RuBKlYLODw0WHJ4bwtVL+8oyUB1bRmOrUJUrcZe7k673Q+kgnQRdoTcTCnp", "X-Received": "by 2002:a63:cd0b:: with SMTP id i11mr6739309pgg.306.1599789435801;\n Thu, 10 Sep 2020 18:57:15 -0700 (PDT)", "X-Relaying-Domain": "broadcom.com", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Randy Schacher <stuart.schacher@broadcom.com>,\n Shahaji Bhosle <sbhosle@broadcom.com>", "Date": "Thu, 10 Sep 2020 18:55:52 -0700", "Message-Id": "<20200911015603.88359-15-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20200911015603.88359-1-ajit.khaparde@broadcom.com>", "References": "<20200911015603.88359-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 14/25] net/bnxt: move IF tbl from tunneled to\n\tdirect HWRM msg", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Randy Schacher <stuart.schacher@broadcom.com>\n\nChange IF tbl from tunneled to non-tunneled HWRM msg.\n\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 935 ++++++++++++++++++-------\n drivers/net/bnxt/tf_core/tf_msg.c | 58 +-\n 2 files changed, 706 insertions(+), 287 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex fb4f712ce..915b4274e 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -341,9 +341,9 @@ struct cmd_nums {\n \t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)\n \t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)\n \t#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)\n-\t#define HWRM_RING_SQ_ALLOC UINT32_C(0x55)\n-\t#define HWRM_RING_SQ_CFG UINT32_C(0x56)\n-\t#define HWRM_RING_SQ_FREE UINT32_C(0x57)\n+\t#define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)\n+\t#define HWRM_RING_SCHQ_CFG UINT32_C(0x56)\n+\t#define HWRM_RING_SCHQ_FREE UINT32_C(0x57)\n \t#define HWRM_RING_RESET UINT32_C(0x5e)\n \t#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)\n \t#define HWRM_RING_GRP_FREE UINT32_C(0x61)\n@@ -413,6 +413,7 @@ struct cmd_nums {\n \t#define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)\n \t#define HWRM_FW_ECN_CFG UINT32_C(0xcd)\n \t#define HWRM_FW_ECN_QCFG UINT32_C(0xce)\n+\t#define HWRM_FW_SECURE_CFG UINT32_C(0xcf)\n \t#define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)\n \t#define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)\n \t#define HWRM_FWD_RESP UINT32_C(0xd2)\n@@ -704,6 +705,10 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)\n \t/* Experimental */\n+\t#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)\n+\t/* Experimental */\n+\t#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)\n+\t/* Experimental */\n \t#define HWRM_SV UINT32_C(0x400)\n \t/* Experimental */\n \t#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)\n@@ -942,8 +947,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 48\n-#define HWRM_VERSION_STR \"1.10.1.48\"\n+#define HWRM_VERSION_RSVD 56\n+#define HWRM_VERSION_STR \"1.10.1.56\"\n \n /****************\n * hwrm_ver_get *\n@@ -2204,16 +2209,18 @@ struct rx_prod_pkt_bd {\n \t */\n \t#define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)\n \t/*\n+\t * This field has been deprecated. There can be no additional\n+\t * BDs for this packet from this ring.\n+\t *\n+\t * Old definition:\n \t * This value is the number of additional buffers in the ring that\n \t * describe the buffer space to be consumed for this packet.\n \t * If the value is zero, then the packet must fit within the\n \t * space described by this BD. If this value is 1 or more, it\n \t * indicates how many additional \"buffer\" BDs are in the ring\n \t * immediately following this BD to be used for the same\n-\t * network packet.\n-\t *\n-\t * Even if the packet to be placed does not need all the\n-\t * additional buffers, they will be consumed anyway.\n+\t * network packet. Even if the packet to be placed does not need\n+\t * all the additional buffers, they will be consumed anyway.\n \t */\n \t#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)\n \t#define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8\n@@ -3585,16 +3592,36 @@ struct rx_pkt_v2_cmpl {\n \t * truncation placement is used, this value represents the placed\n \t * (truncated) length of the packet.\n \t */\n-\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)\n-\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0\n+\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)\n+\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0\n \t/* This is data from the CFA as indicated by the meta_format field. */\n-\t#define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)\n-\t#define RX_PKT_V2_CMPL_METADATA1_SFT 12\n-\t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n-\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)\n-\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t#define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)\n+\t#define RX_PKT_V2_CMPL_METADATA1_SFT 12\n \t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n-\t#define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t/* 0x88a8 */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/* 0x8100 */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/* 0x9100 */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/* 0x9200 */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/* 0x9300 */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/* Value programmed in CFA VLANTPID register. */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \\\n+\t\tRX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG\n+\t/* When meta_format != 0, this value is the VLAN valid. */\n+\t#define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)\n \t/*\n \t * This value is the RSS hash value calculated for the packet\n \t * based on the mode bits and key value in the VNIC. When vee_cmpl_mode\n@@ -4484,15 +4511,38 @@ struct rx_tpa_start_v2_cmpl {\n \t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n-\t#define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)\n-\t#define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0\n-\t#define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)\n-\t#define RX_TPA_START_V2_CMPL_METADATA1_SFT 12\n+\t#define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)\n+\t#define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_MASK \\\n+\t\tUINT32_C(0xf000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_SFT 12\n \t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n-\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)\n-\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \\\n+\t\tUINT32_C(0x7000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t/* 0x88a8 */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/* 0x8100 */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/* 0x9100 */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/* 0x9200 */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/* 0x9300 */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/* Value programmed in CFA VLANTPID register. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG\n \t/* When meta_format != 0, this value is the VLAN valid. */\n-\t#define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_VALID \\\n+\t\tUINT32_C(0x8000)\n \t/*\n \t * This value is the RSS hash value calculated for the packet\n \t * based on the mode bits and key value in the VNIC.\n@@ -8908,6 +8958,13 @@ struct hwrm_func_vf_cfg_input {\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \\\n \t\tUINT32_C(0x100)\n+\t/*\n+\t * If this bit is set to 1, the VF driver is requesting FW to disable\n+\t * PPP TX PUSH feature on all the TX rings of the VF. This flag is\n+\t * ignored if the VF doesn't support PPP tx push feature.\n+\t */\n+\t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \\\n+\t\tUINT32_C(0x200)\n \t/* The number of RSS/COS contexts requested for the VF. */\n \tuint16_t\tnum_rsscos_ctxs;\n \t/* The number of completion rings requested for the VF. */\n@@ -9396,10 +9453,10 @@ struct hwrm_func_qcaps_output {\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * If 1, the device supports scheduler queues. SQs can be managed\n-\t * using RING_SQ_ALLOC/CFG/FREE commands.\n+\t * If 1, the device supports scheduler queues. SCHQs can be managed\n+\t * using RING_SCHQ_ALLOC/CFG/FREE commands.\n \t */\n-\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \\\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \\\n \t\tUINT32_C(0x40)\n \t/*\n \t * If set to 1, then this function supports the TX push mode that\n@@ -9407,8 +9464,8 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \\\n \t\tUINT32_C(0x80)\n-\t/* The maximum number of SQs supported by this device. */\n-\tuint8_t\tmax_sqs;\n+\t/* The maximum number of SCHQs supported by this device. */\n+\tuint8_t\tmax_schqs;\n \tuint8_t\tunused_1[2];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -10159,6 +10216,15 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \\\n \t\tUINT32_C(0x8000000)\n+\t/*\n+\t * If this bit is set to 1, the PF driver is requesting FW\n+\t * to disable PPP TX PUSH feature on all the TX rings specified in\n+\t * the num_tx_rings field. This flag is ignored if num_tx_rings\n+\t * field is not specified or the function doesn't support PPP tx\n+\t * push feature.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \\\n+\t\tUINT32_C(0x10000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -10305,10 +10371,10 @@ struct hwrm_func_cfg_input {\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \\\n \t\tUINT32_C(0x800000)\n \t/*\n-\t * This bit must be '1' for the sq_id field to be\n+\t * This bit must be '1' for the schq_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \\\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \\\n \t\tUINT32_C(0x1000000)\n \t/*\n \t * The maximum transmission unit of the function.\n@@ -10574,8 +10640,8 @@ struct hwrm_func_cfg_input {\n \t * be reserved for this function on the RX side.\n \t */\n \tuint16_t\tnum_mcast_filters;\n-\t/* Used by a PF driver to associate a SQ with a VF. */\n-\tuint16_t\tsq_id;\n+\t/* Used by a PF driver to associate a SCHQ with a VF. */\n+\tuint16_t\tschq_id;\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n@@ -10808,12 +10874,12 @@ struct hwrm_func_qstats_ext_input {\n \tuint8_t\tunused_0[1];\n \tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the sq_id and traffic_class fields to be\n-\t * configured.\n+\t * This bit must be '1' for the schq_id and traffic_class fields to\n+\t * be configured.\n \t */\n-\t#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID UINT32_C(0x1)\n-\t/* Specifies the SQ for which to gather statistics */\n-\tuint16_t\tsq_id;\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)\n+\t/* Specifies the SCHQ for which to gather statistics */\n+\tuint16_t\tschq_id;\n \t/*\n \t * Specifies the traffic class for which to gather statistics. Valid\n \t * values are 0 through (max_configurable_queues - 1), where\n@@ -15275,7 +15341,14 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x80)\n \t/*\n \t * When set to 1, then the HWRM shall enable FEC autonegotitation\n-\t * on this port if supported.\n+\t * on this port if supported. When enabled, at least one of the\n+\t * FEC modes must be advertised by enabling the fec_clause_74_enable,\n+\t * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable\n+\t * flag. If none of the FEC mode is currently enabled, the HWRM\n+\t * shall choose a default advertisement setting.\n+\t * The default advertisment setting can be queried by calling\n+\t * hwrm_port_phy_qcfg. Note that the link speed must be\n+\t * in autonegotiation mode for FEC autonegotiation to take effect.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15293,7 +15366,8 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x200)\n \t/*\n \t * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)\n-\t * on this port if supported.\n+\t * on this port if supported, by advertising FEC CLAUSE 74 if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15302,7 +15376,8 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x400)\n \t/*\n \t * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)\n-\t * on this port if supported.\n+\t * on this port if supported, by not advertising FEC CLAUSE 74 if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15311,7 +15386,8 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x800)\n \t/*\n \t * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported.\n+\t * on this port if supported, by advertising FEC CLAUSE 91 if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15320,7 +15396,8 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x1000)\n \t/*\n \t * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported.\n+\t * on this port if supported, by not advertising FEC CLAUSE 91 if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n \t * When set to 0, then this flag shall be ignored.\n \t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n \t * flag.\n@@ -15347,6 +15424,46 @@ struct hwrm_port_phy_cfg_input {\n \t */\n \t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * When set to 1, then the HWRM shall enable FEC RS544_1XN\n+\t * on this port if supported, by advertising FEC RS544_1XN if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS544_1XN is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * When set to 1, then the HWRM shall disable FEC RS544_1XN\n+\t * on this port if supported, by not advertising FEC RS544_1XN if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS544_1XN is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * When set to 1, then the HWRM shall enable FEC RS544_2XN\n+\t * on this port if supported, by advertising FEC RS544_2XN if\n+\t * FEC autonegotiation is enabled or force enabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS544_2XN is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \\\n+\t\tUINT32_C(0x20000)\n+\t/*\n+\t * When set to 1, then the HWRM shall disable FEC RS544_2XN\n+\t * on this port if supported, by not advertising FEC RS544_2XN if\n+\t * FEC autonegotiation is enabled or force disabled otherwise.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC RS544_2XN is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \\\n+\t\tUINT32_C(0x40000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the auto_mode field to be\n@@ -16573,9 +16690,6 @@ struct hwrm_port_phy_qcfg_output {\n \t * is set to 1, then all other FEC configuration flags shall be ignored.\n \t * When set to 0, then FEC is supported as indicated by other\n \t * configuration flags.\n-\t * If no cable is attached and the HWRM does not yet know the FEC\n-\t * capability, then the HWRM shall set this flag to 1 when reporting\n-\t * FEC capability.\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \\\n \t\tUINT32_C(0x1)\n@@ -16599,7 +16713,9 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.\n+\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this\n+\t * port. This means that FEC CLAUSE 74 is either advertised if\n+\t * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.\n \t * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.\n \t * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.\n \t */\n@@ -16612,12 +16728,84 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this\n+\t * port. This means that FEC CLAUSE 91 is either advertised if\n+\t * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled.\n \t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.\n \t * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \\\n \t\tUINT32_C(0x40)\n+\t/*\n+\t * When set to 1, then FEC RS544_1XN is supported on this port.\n+\t * When set to 0, then FEC RS544_1XN is not supported on this port.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When set to 1, then RS544_1XN is enabled on this\n+\t * port. This means that FEC RS544_1XN is either advertised if\n+\t * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.\n+\t * When set to 0, then FEC RS544_1XN is disabled if supported.\n+\t * This flag should be ignored if FEC RS544_1XN is not supported on this port.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When set to 1, then FEC RS544_2XN is supported on this port.\n+\t * When set to 0, then FEC RS544_2XN is not supported on this port.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When set to 1, then RS544_2XN is enabled on this\n+\t * port. This means that FEC RS544_2XN is either advertised if\n+\t * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled.\n+\t * When set to 0, then FEC RS544_2XN is disabled if supported.\n+\t * This flag should be ignored if FEC RS544_2XN is not supported on this port.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this\n+\t * port, either successfully autonegoatiated or forced.\n+\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active.\n+\t * This flag is only valid when link is up on this port.\n+\t * At most only one active FEC flags (fec_clause74_active,\n+\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this\n+\t * port, either successfully autonegoatiated or forced.\n+\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active.\n+\t * This flag is only valid when link is up on this port.\n+\t * At most only one active FEC flags (fec_clause74_active,\n+\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * When set to 1, then FEC RS544_1XN is active on this\n+\t * port, either successfully autonegoatiated or forced.\n+\t * When set to 0, then FEC RS544_1XN is not active.\n+\t * This flag is only valid when link is up on this port.\n+\t * At most only one active FEC flags (fec_clause74_active,\n+\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When set to 1, then FEC RS544_2XN is active on this\n+\t * port, either successfully autonegoatiated or forced.\n+\t * When set to 0, then FEC RS544_2XN is not active.\n+\t * This flag is only valid when link is up on this port.\n+\t * At most only one active FEC flags (fec_clause74_active,\n+\t * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \\\n+\t\tUINT32_C(0x4000)\n \t/*\n \t * This value is indicates the duplex of the current\n \t * connection state.\n@@ -19079,13 +19267,24 @@ struct hwrm_port_phy_qcaps_output {\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, it indicates that the port counters and extended\n+\t * port counters will not reset when the firmware shuts down or\n+\t * resets the PHY. These counters will only be reset during power\n+\t * cycle or by calling HWRM_PORT_CLR_STATS.\n+\t * If set to 0, the state of the counters is unspecified when\n+\t * firmware shuts down or resets the PHY.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \\\n+\t\tUINT32_C(0x10)\n \t/*\n \t * Reserved field. The HWRM shall set this field to 0.\n \t * An HWRM client shall ignore this field.\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n-\t\tUINT32_C(0xf0)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4\n+\t\tUINT32_C(0xe0)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \\\n+\t\t5\n \t/* Number of front panel ports for this device. */\n \tuint8_t\tport_cnt;\n \t/* Not supported or unknown */\n@@ -21251,7 +21450,7 @@ struct hwrm_queue_qportcfg_input {\n \tuint8_t\tunused_0;\n } __rte_packed;\n \n-/* hwrm_queue_qportcfg_output (size:256b/32B) */\n+/* hwrm_queue_qportcfg_output (size:1344b/168B) */\n struct hwrm_queue_qportcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -21627,6 +21826,28 @@ struct hwrm_queue_qportcfg_output {\n \t\tUINT32_C(0xff)\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \\\n \t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * Up to 16 bytes of null padded ASCII string describing this queue.\n+\t * The queue name includes a CoS queue index and, in some cases, text\n+\t * that distinguishes the queue from other queues in the group.\n+\t */\n+\tchar\tqid0_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid1_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid2_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid3_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid4_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid5_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid6_name[16];\n+\t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n+\tchar\tqid7_name[16];\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -26929,10 +27150,10 @@ struct hwrm_ring_alloc_input {\n \t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * This bit must be '1' for the sq_id field to be\n+\t * This bit must be '1' for the schq_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \\\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \\\n \t\tUINT32_C(0x200)\n \t/* Ring Type. */\n \tuint8_t\tring_type;\n@@ -26999,8 +27220,8 @@ struct hwrm_ring_alloc_input {\n \t * element of the ring.\n \t */\n \tuint8_t\tpage_tbl_depth;\n-\t/* Used by a PF driver to associate a SQ with one of its TX rings. */\n-\tuint16_t\tsq_id;\n+\t/* Used by a PF driver to associate a SCHQ with one of its TX rings. */\n+\tuint16_t\tschq_id;\n \t/*\n \t * Number of 16B units in the ring. Minimum size for\n \t * a ring is 16 16B entries.\n@@ -27453,8 +27674,8 @@ struct hwrm_ring_cfg_input {\n \t */\n \t#define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \\\n \t\tUINT32_C(0x4)\n-\t/* The sq_id field is valid */\n-\t#define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \\\n+\t/* The schq_id field is valid */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \\\n \t\tUINT32_C(0x8)\n \t/* Update completion ring ID associated with Tx or Rx ring. */\n \t#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \\\n@@ -27471,12 +27692,12 @@ struct hwrm_ring_cfg_input {\n \t */\n \tuint16_t\tproxy_fid;\n \t/*\n-\t * Identifies the new scheduler queue (SQ) to associate with the ring.\n-\t * Only valid for Tx rings.\n+\t * Identifies the new scheduler queue (SCHQ) to associate with the\n+\t * ring. Only valid for Tx rings.\n \t * A value of zero indicates that the Tx ring should be associated\n-\t * with the default scheduler queue (SQ).\n+\t * with the default scheduler queue (SCHQ).\n \t */\n-\tuint16_t\tsq_id;\n+\tuint16_t\tschq_id;\n \t/*\n \t * This field is valid for TX or Rx rings. This value identifies the\n \t * new completion ring ID to associate with the TX or Rx ring.\n@@ -27622,12 +27843,12 @@ struct hwrm_ring_qcfg_output {\n \t */\n \tuint16_t\tproxy_fid;\n \t/*\n-\t * Identifies the new scheduler queue (SQ) to associate with the ring.\n-\t * Only valid for Tx rings.\n+\t * Identifies the new scheduler queue (SCHQ) to associate with the\n+\t * ring. Only valid for Tx rings.\n \t * A value of zero indicates that the Tx ring should be associated with\n-\t * the default scheduler queue (SQ).\n+\t * the default scheduler queue (SCHQ).\n \t */\n-\tuint16_t\tsq_id;\n+\tuint16_t\tschq_id;\n \t/*\n \t * This field is used when ring_type is a TX or Rx ring.\n \t * This value indicates what completion ring the TX or Rx ring\n@@ -28222,13 +28443,13 @@ struct hwrm_ring_grp_free_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_ring_sq_alloc *\n- **********************/\n+/************************\n+ * hwrm_ring_schq_alloc *\n+ ************************/\n \n \n-/* hwrm_ring_sq_alloc_input (size:1088b/136B) */\n-struct hwrm_ring_sq_alloc_input {\n+/* hwrm_ring_schq_alloc_input (size:1088b/136B) */\n+struct hwrm_ring_schq_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -28262,380 +28483,396 @@ struct hwrm_ring_sq_alloc_input {\n \t * This bit must be '1' for the tqm_ring0 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)\n \t/*\n \t * This bit must be '1' for the tqm_ring1 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)\n \t/*\n \t * This bit must be '1' for the tqm_ring2 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)\n \t/*\n \t * This bit must be '1' for the tqm_ring3 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)\n \t/*\n \t * This bit must be '1' for the tqm_ring4 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)\n \t/*\n \t * This bit must be '1' for the tqm_ring5 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)\n \t/*\n \t * This bit must be '1' for the tqm_ring6 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)\n \t/*\n \t * This bit must be '1' for the tqm_ring7 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)\n \t/* Reserved for future use. */\n \tuint32_t\treserved;\n \t/* TQM ring 0 page size and level. */\n \tuint8_t\ttqm_ring0_pg_size_tqm_ring0_lvl;\n \t/* TQM ring 0 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2\n \t/* TQM ring 0 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G\n \t/* TQM ring 1 page size and level. */\n \tuint8_t\ttqm_ring1_pg_size_tqm_ring1_lvl;\n \t/* TQM ring 1 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2\n \t/* TQM ring 1 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G\n \t/* TQM ring 2 page size and level. */\n \tuint8_t\ttqm_ring2_pg_size_tqm_ring2_lvl;\n \t/* TQM ring 2 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2\n \t/* TQM ring 2 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G\n \t/* TQM ring 3 page size and level. */\n \tuint8_t\ttqm_ring3_pg_size_tqm_ring3_lvl;\n \t/* TQM ring 3 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2\n \t/* TQM ring 3 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G\n \t/* TQM ring 4 page size and level. */\n \tuint8_t\ttqm_ring4_pg_size_tqm_ring4_lvl;\n \t/* TQM ring 4 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2\n \t/* TQM ring 4 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G\n \t/* TQM ring 5 page size and level. */\n \tuint8_t\ttqm_ring5_pg_size_tqm_ring5_lvl;\n \t/* TQM ring 5 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2\n \t/* TQM ring 5 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G\n \t/* TQM ring 6 page size and level. */\n \tuint8_t\ttqm_ring6_pg_size_tqm_ring6_lvl;\n \t/* TQM ring 6 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2\n \t/* TQM ring 6 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G\n \t/* TQM ring 7 page size and level. */\n \tuint8_t\ttqm_ring7_pg_size_tqm_ring7_lvl;\n \t/* TQM ring 7 PBL indirect levels. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0\n \t/* PBL pointer is physical start address. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \\\n \t\tUINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * PBL pointer points to PDE table with each entry pointing to PTE\n \t * tables.\n \t */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2\n \t/* TQM ring 7 page size. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4\n \t/* 4KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \\\n \t\t(UINT32_C(0x0) << 4)\n \t/* 8KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \\\n \t\t(UINT32_C(0x1) << 4)\n \t/* 64KB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \\\n \t\t(UINT32_C(0x2) << 4)\n \t/* 2MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \\\n \t\t(UINT32_C(0x3) << 4)\n \t/* 8MB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \\\n \t\t(UINT32_C(0x4) << 4)\n \t/* 1GB. */\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \\\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \\\n \t\t(UINT32_C(0x5) << 4)\n-\t#define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \\\n-\t\tHWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G\n+\t#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \\\n+\t\tHWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G\n \t/* TQM ring 0 page directory. */\n \tuint64_t\ttqm_ring0_page_dir;\n \t/* TQM ring 1 page directory. */\n@@ -28661,7 +28898,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring0_num_entries;\n \t/*\n@@ -28673,7 +28910,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring1_num_entries;\n \t/*\n@@ -28685,7 +28922,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring2_num_entries;\n \t/*\n@@ -28697,7 +28934,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring3_num_entries;\n \t/*\n@@ -28709,7 +28946,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring4_num_entries;\n \t/*\n@@ -28721,7 +28958,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring5_num_entries;\n \t/*\n@@ -28733,7 +28970,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring6_num_entries;\n \t/*\n@@ -28745,7 +28982,7 @@ struct hwrm_ring_sq_alloc_input {\n \t *\n \t * Note that TQM ring sizes cannot be extended while the system is\n \t * operational. If a PF driver needs to extend a TQM ring, it needs\n-\t * to delete the SQ and then reallocate it.\n+\t * to delete the SCHQ and then reallocate it.\n \t */\n \tuint32_t\ttqm_ring7_num_entries;\n \t/* Number of bytes that have been allocated for each context entry. */\n@@ -28753,8 +28990,8 @@ struct hwrm_ring_sq_alloc_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_ring_sq_alloc_output (size:128b/16B) */\n-struct hwrm_ring_sq_alloc_output {\n+/* hwrm_ring_schq_alloc_output (size:128b/16B) */\n+struct hwrm_ring_schq_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -28764,11 +29001,11 @@ struct hwrm_ring_sq_alloc_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * This is an identifier for the SQ to be used in other HWRM commands\n-\t * that need to reference this SQ. This value is greater than zero\n-\t * (i.e. a sq_id of zero references the default SQ).\n+\t * This is an identifier for the SCHQ to be used in other HWRM commands\n+\t * that need to reference this SCHQ. This value is greater than zero\n+\t * (i.e. a schq_id of zero references the default SCHQ).\n \t */\n-\tuint16_t\tsq_id;\n+\tuint16_t\tschq_id;\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -28780,13 +29017,13 @@ struct hwrm_ring_sq_alloc_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/********************\n- * hwrm_ring_sq_cfg *\n- ********************/\n+/**********************\n+ * hwrm_ring_schq_cfg *\n+ **********************/\n \n \n-/* hwrm_ring_sq_cfg_input (size:768b/96B) */\n-struct hwrm_ring_sq_cfg_input {\n+/* hwrm_ring_schq_cfg_input (size:768b/96B) */\n+struct hwrm_ring_schq_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -28816,23 +29053,23 @@ struct hwrm_ring_sq_cfg_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Identifies the SQ being configured. A sq_id of zero refers to the\n-\t * default SQ.\n+\t * Identifies the SCHQ being configured. A schq_id of zero refers to\n+\t * the default SCHQ.\n \t */\n-\tuint16_t\tsq_id;\n+\tuint16_t\tschq_id;\n \t/*\n \t * This field is an 8 bit bitmap that indicates which TCs are enabled\n-\t * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents\n+\t * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents\n \t * traffic class 7.\n \t */\n \tuint8_t\ttc_enabled;\n \tuint8_t\tunused_0;\n \tuint32_t\tflags;\n \t/* The tc_max_bw array and the max_bw parameters are valid */\n-\t#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \\\n+\t#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \\\n \t\tUINT32_C(0x1)\n \t/* The tc_min_bw array is valid */\n-\t#define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \\\n+\t#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \\\n \t\tUINT32_C(0x2)\n \t/* Maximum bandwidth of the traffic class, specified in Mbps. */\n \tuint32_t\tmax_bw_tc0;\n@@ -28854,68 +29091,68 @@ struct hwrm_ring_sq_cfg_input {\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc0;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc1;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc2;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc3;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc4;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc5;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc6;\n \t/*\n \t * Bandwidth reservation for the traffic class, specified in Mbps.\n \t * A value of zero signifies that traffic belonging to this class\n \t * shares the bandwidth reservation for the same traffic class of\n-\t * the default SQ.\n+\t * the default SCHQ.\n \t */\n \tuint32_t\tmin_bw_tc7;\n \t/*\n \t * Indicates the max bandwidth for all enabled traffic classes in\n-\t * this SQ, specified in Mbps.\n+\t * this SCHQ, specified in Mbps.\n \t */\n \tuint32_t\tmax_bw;\n \tuint8_t\tunused_1[4];\n } __rte_packed;\n \n-/* hwrm_ring_sq_cfg_output (size:128b/16B) */\n-struct hwrm_ring_sq_cfg_output {\n+/* hwrm_ring_schq_cfg_output (size:128b/16B) */\n+struct hwrm_ring_schq_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -28935,13 +29172,13 @@ struct hwrm_ring_sq_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*********************\n- * hwrm_ring_sq_free *\n- *********************/\n+/***********************\n+ * hwrm_ring_schq_free *\n+ ***********************/\n \n \n-/* hwrm_ring_sq_free_input (size:192b/24B) */\n-struct hwrm_ring_sq_free_input {\n+/* hwrm_ring_schq_free_input (size:192b/24B) */\n+struct hwrm_ring_schq_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -28970,13 +29207,13 @@ struct hwrm_ring_sq_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Identifies the SQ being freed. */\n-\tuint16_t\tsq_id;\n+\t/* Identifies the SCHQ being freed. */\n+\tuint16_t\tschq_id;\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_ring_sq_free_output (size:128b/16B) */\n-struct hwrm_ring_sq_free_output {\n+/* hwrm_ring_schq_free_output (size:128b/16B) */\n+struct hwrm_ring_schq_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -38802,7 +39039,9 @@ struct hwrm_tf_global_cfg_set_input {\n \t/* unused. */\n \tuint8_t\tunused0[6];\n \t/* Data to set */\n-\tuint8_t\tdata[16];\n+\tuint8_t\tdata[8];\n+\t/* Mask of data to set, 0 indicates no mask */\n+\tuint8_t\tmask[8];\n } __rte_packed;\n \n /* hwrm_tf_global_cfg_set_output (size:128b/16B) */\n@@ -38903,6 +39142,182 @@ struct hwrm_tf_global_cfg_get_output {\n \tuint8_t\tdata[16];\n } __rte_packed;\n \n+/**********************\n+ * hwrm_tf_if_tbl_get *\n+ **********************/\n+\n+\n+/* hwrm_tf_if_tbl_get_input (size:256b/32B) */\n+struct hwrm_tf_if_tbl_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n+} __rte_packed;\n+\n+/* hwrm_tf_if_tbl_get_output (size:256b/32B) */\n+struct hwrm_tf_if_tbl_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint16_t\tunused0;\n+\t/* Response data. */\n+\tuint8_t\tdata[8];\n+\t/* unused */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***************************\n+ * hwrm_tf_if_tbl_type_set *\n+ ***************************/\n+\n+\n+/* hwrm_tf_if_tbl_set_input (size:384b/48B) */\n+struct hwrm_tf_if_tbl_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to set. */\n+\tuint32_t\tindex;\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused1[6];\n+\t/* Data to be set. */\n+\tuint8_t\tdata[8];\n+} __rte_packed;\n+\n+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */\n+struct hwrm_tf_if_tbl_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /******************************\n * hwrm_tunnel_dst_port_query *\n ******************************/\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c\nindex db471f625..7c2ad172f 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.c\n+++ b/drivers/net/bnxt/tf_core/tf_msg.c\n@@ -1250,8 +1250,8 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,\n {\n \tint rc = 0;\n \tstruct tfp_send_msg_parms parms = { 0 };\n-\ttf_if_tbl_get_input_t req = { 0 };\n-\ttf_if_tbl_get_output_t resp;\n+\tstruct hwrm_tf_if_tbl_get_input req = { 0 };\n+\tstruct hwrm_tf_if_tbl_get_output resp = { 0 };\n \tuint32_t flags = 0;\n \tstruct tf_session *tfs;\n \n@@ -1265,25 +1265,26 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,\n \t\treturn rc;\n \t}\n \n-\tflags = (params->dir == TF_DIR_TX ? TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX :\n-\t\t TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX);\n+\tflags = (params->dir == TF_DIR_TX ?\n+\t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX :\n+\t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX);\n \n \t/* Populate the request */\n \treq.fw_session_id =\n \t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n \treq.flags = flags;\n-\treq.tf_if_tbl_type = params->hcapi_type;\n-\treq.idx = tfp_cpu_to_le_16(params->idx);\n-\treq.data_sz_in_bytes = tfp_cpu_to_le_16(params->data_sz_in_bytes);\n+\treq.type = params->hcapi_type;\n+\treq.index = tfp_cpu_to_le_16(params->idx);\n+\treq.size = tfp_cpu_to_le_16(params->data_sz_in_bytes);\n \n-\tMSG_PREP(parms,\n-\t\t TF_KONG_MB,\n-\t\t HWRM_TF,\n-\t\t HWRM_TFT_IF_TBL_GET,\n-\t\t req,\n-\t\t resp);\n+\tparms.tf_type = HWRM_TF_IF_TBL_GET;\n+\tparms.req_data = (uint32_t *)&req;\n+\tparms.req_size = sizeof(req);\n+\tparms.resp_data = (uint32_t *)&resp;\n+\tparms.resp_size = sizeof(resp);\n+\tparms.mailbox = TF_KONG_MB;\n \n-\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\trc = tfp_send_msg_direct(tfp, &parms);\n \n \tif (rc != 0)\n \t\treturn rc;\n@@ -1291,7 +1292,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp,\n \tif (parms.tf_resp_code != 0)\n \t\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n \n-\ttfp_memcpy(¶ms->data[0], resp.data, req.data_sz_in_bytes);\n+\ttfp_memcpy(¶ms->data[0], resp.data, req.size);\n \n \treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n }\n@@ -1302,7 +1303,8 @@ tf_msg_set_if_tbl_entry(struct tf *tfp,\n {\n \tint rc = 0;\n \tstruct tfp_send_msg_parms parms = { 0 };\n-\ttf_if_tbl_set_input_t req = { 0 };\n+\tstruct hwrm_tf_if_tbl_set_input req = { 0 };\n+\tstruct hwrm_tf_if_tbl_get_output resp = { 0 };\n \tuint32_t flags = 0;\n \tstruct tf_session *tfs;\n \n@@ -1317,25 +1319,27 @@ tf_msg_set_if_tbl_entry(struct tf *tfp,\n \t}\n \n \n-\tflags = (params->dir == TF_DIR_TX ? TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX :\n-\t\t TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX);\n+\tflags = (params->dir == TF_DIR_TX ?\n+\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX :\n+\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX);\n \n \t/* Populate the request */\n \treq.fw_session_id =\n \t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n \treq.flags = flags;\n-\treq.tf_if_tbl_type = params->hcapi_type;\n-\treq.idx = tfp_cpu_to_le_32(params->idx);\n-\treq.data_sz_in_bytes = tfp_cpu_to_le_32(params->data_sz_in_bytes);\n+\treq.type = params->hcapi_type;\n+\treq.index = tfp_cpu_to_le_32(params->idx);\n+\treq.size = tfp_cpu_to_le_32(params->data_sz_in_bytes);\n \ttfp_memcpy(&req.data[0], params->data, params->data_sz_in_bytes);\n \n-\tMSG_PREP_NO_RESP(parms,\n-\t\t\t TF_KONG_MB,\n-\t\t\t HWRM_TF,\n-\t\t\t HWRM_TFT_IF_TBL_SET,\n-\t\t\t req);\n+\tparms.tf_type = HWRM_TF_IF_TBL_SET;\n+\tparms.req_data = (uint32_t *)&req;\n+\tparms.req_size = sizeof(req);\n+\tparms.resp_data = (uint32_t *)&resp;\n+\tparms.resp_size = sizeof(resp);\n+\tparms.mailbox = TF_KONG_MB;\n \n-\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\trc = tfp_send_msg_direct(tfp, &parms);\n \n \tif (rc != 0)\n \t\treturn rc;\n", "prefixes": [ "14/25" ] }