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GET /api/patches/77117/?format=api
{ "id": 77117, "url": "http://patches.dpdk.org/api/patches/77117/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200910065504.104217-2-leyi.rong@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200910065504.104217-2-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200910065504.104217-2-leyi.rong@intel.com", "date": "2020-09-10T06:55:03", "name": "[v1,1/2] net/ice: add AVX512 vector path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "940fdc52257c99de2f6daedd9bc3c141daa9c252", "submitter": { "id": 1204, "url": "http://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200910065504.104217-2-leyi.rong@intel.com/mbox/", "series": [ { "id": 12088, "url": "http://patches.dpdk.org/api/series/12088/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12088", "date": "2020-09-10T06:55:02", "name": "AVX512 vPMD on ice", "version": 1, "mbox": "http://patches.dpdk.org/series/12088/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77117/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/77117/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E53E1A04B5;\n\tThu, 10 Sep 2020 09:12:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F243D1C0CD;\n\tThu, 10 Sep 2020 09:12:21 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 0E96C1BEB3\n for <dev@dpdk.org>; Thu, 10 Sep 2020 09:12:17 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Sep 2020 00:12:17 -0700", "from dpdk-lrong-srv-04.sh.intel.com ([10.67.119.221])\n by fmsmga006.fm.intel.com with ESMTP; 10 Sep 2020 00:12:15 -0700" ], "IronPort-SDR": [ "\n 8taSs9/ARtFTUYjpOSdM1HAnuW2l5dQPri2CfztDl8nqNONFOad9JMLqxQK/82jMbSsn16a9Ok\n RpfJqkAXdfpQ==", "\n LTQYCz7r95A/qsuDuwICaX7Lj/GVpfNNEn9oXrMe3+smQjwLZ664cbyzPRo7CBt04SIuyY87CG\n hQnPL/pWmHrw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9739\"; a=\"155942596\"", "E=Sophos;i=\"5.76,412,1592895600\"; d=\"scan'208\";a=\"155942596\"", "E=Sophos;i=\"5.76,412,1592895600\"; d=\"scan'208\";a=\"505023559\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "bruce.richardson@intel.com,\n\twenzhuo.lu@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\tLeyi Rong <leyi.rong@intel.com>", "Date": "Thu, 10 Sep 2020 14:55:03 +0800", "Message-Id": "<20200910065504.104217-2-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200910065504.104217-1-leyi.rong@intel.com>", "References": "<20200910065504.104217-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH v1 1/2] net/ice: add AVX512 vector path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add AVX512 support for ice PMD. This patch adds ice_rxtx_vec_avx512.c\nto support ice AVX512 vPMD.\n\nThis patch aims to enable AVX512 on ice vPMD. Main changes are focus\non Rx path compared with AVX2 vPMD.\n\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n drivers/net/ice/ice_rxtx.c | 88 ++-\n drivers/net/ice/ice_rxtx.h | 7 +\n drivers/net/ice/ice_rxtx_vec_avx512.c | 824 ++++++++++++++++++++++++++\n drivers/net/ice/meson.build | 13 +\n 4 files changed, 914 insertions(+), 18 deletions(-)\n create mode 100644 drivers/net/ice/ice_rxtx_vec_avx512.c", "diff": "diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex ccddae687..096bf098f 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -1852,6 +1852,10 @@ ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)\n #ifdef RTE_ARCH_X86\n \tif (dev->rx_pkt_burst == ice_recv_pkts_vec ||\n \t dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||\n+#ifdef CC_AVX512_SUPPORT\n+\t dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||\n+\t dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||\n+#endif\n \t dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||\n \t dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)\n \t\treturn ptypes;\n@@ -2909,6 +2913,7 @@ ice_set_rx_function(struct rte_eth_dev *dev)\n #ifdef RTE_ARCH_X86\n \tstruct ice_rx_queue *rxq;\n \tint i;\n+\tbool use_avx512 = false;\n \tbool use_avx2 = false;\n \n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n@@ -2924,10 +2929,18 @@ ice_set_rx_function(struct rte_eth_dev *dev)\n \t\t\t\t}\n \t\t\t}\n \n-\t\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t\tif (rte_get_max_simd_bitwidth() >= RTE_MAX_512_SIMD &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\t\tuse_avx512 = true;\n+#else\n+\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\"AVX512 is not supported in build env\");\n+#endif\n+\t\t\tif (!use_avx512 &&\n+\t\t\t(rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n \t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n-\t\t\t\t\trte_get_max_simd_bitwidth()\n-\t\t\t\t\t>= RTE_MAX_256_SIMD)\n+\t\t\trte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD)\n \t\t\t\tuse_avx2 = true;\n \n \t\t} else {\n@@ -2937,20 +2950,37 @@ ice_set_rx_function(struct rte_eth_dev *dev)\n \n \tif (ad->rx_vec_allowed) {\n \t\tif (dev->data->scattered_rx) {\n-\t\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\tif (use_avx512) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t\"Using AVX512 Vector Scattered Rx (port %d).\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t\t\tdev->rx_pkt_burst =\n+\t\t\t\t\tice_recv_scattered_pkts_vec_avx512;\n+\t\t\t} else {\n+\t\t\t\tPMD_DRV_LOG(DEBUG,\n \t\t\t\t\t\"Using %sVector Scattered Rx (port %d).\",\n \t\t\t\t\tuse_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t\tdev->data->port_id);\n-\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n \t\t\t\t\tice_recv_scattered_pkts_vec_avx2 :\n \t\t\t\t\tice_recv_scattered_pkts_vec;\n+\t\t\t}\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Rx (port %d).\",\n+\t\t\tif (use_avx512) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t\"Using AVX512 Vector Rx (port %d).\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t\t\tdev->rx_pkt_burst =\n+\t\t\t\t\tice_recv_pkts_vec_avx512;\n+\t\t\t} else {\n+\t\t\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t\t\t\"Using %sVector Rx (port %d).\",\n \t\t\t\t\tuse_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t\tdev->data->port_id);\n-\t\t\tdev->rx_pkt_burst = use_avx2 ?\n-\t\t\t\t\t\tice_recv_pkts_vec_avx2 :\n-\t\t\t\t\t\tice_recv_pkts_vec;\n+\t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n+\t\t\t\t\tice_recv_pkts_vec_avx2 :\n+\t\t\t\t\tice_recv_pkts_vec;\n+\t\t\t}\n \t\t}\n \t\treturn;\n \t}\n@@ -2987,6 +3017,10 @@ static const struct {\n \t{ ice_recv_pkts_bulk_alloc, \"Scalar Bulk Alloc\" },\n \t{ ice_recv_pkts, \"Scalar\" },\n #ifdef RTE_ARCH_X86\n+#ifdef CC_AVX512_SUPPORT\n+\t{ ice_recv_scattered_pkts_vec_avx512, \"Vector AVX512 Scattered\" },\n+\t{ ice_recv_pkts_vec_avx512, \"Vector AVX512\" },\n+#endif\n \t{ ice_recv_scattered_pkts_vec_avx2, \"Vector AVX2 Scattered\" },\n \t{ ice_recv_pkts_vec_avx2, \"Vector AVX2\" },\n \t{ ice_recv_scattered_pkts_vec, \"Vector SSE Scattered\" },\n@@ -3091,6 +3125,7 @@ ice_set_tx_function(struct rte_eth_dev *dev)\n #ifdef RTE_ARCH_X86\n \tstruct ice_tx_queue *txq;\n \tint i;\n+\tbool use_avx512 = false;\n \tbool use_avx2 = false;\n \n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n@@ -3106,10 +3141,18 @@ ice_set_tx_function(struct rte_eth_dev *dev)\n \t\t\t\t}\n \t\t\t}\n \n-\t\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t\tif (rte_get_max_simd_bitwidth() >= RTE_MAX_512_SIMD &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\t\tuse_avx512 = true;\n+#else\n+\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\"AVX512 is not supported in build env\");\n+#endif\n+\t\t\tif (!use_avx512 &&\n+\t\t\t(rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n \t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n-\t\t\t\t\trte_get_max_simd_bitwidth()\n-\t\t\t\t\t>= RTE_MAX_256_SIMD)\n+\t\t\trte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD)\n \t\t\t\tuse_avx2 = true;\n \n \t\t} else {\n@@ -3118,12 +3161,18 @@ ice_set_tx_function(struct rte_eth_dev *dev)\n \t}\n \n \tif (ad->tx_vec_allowed) {\n-\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n-\t\t\t use_avx2 ? \"avx2 \" : \"\",\n-\t\t\t dev->data->port_id);\n-\t\tdev->tx_pkt_burst = use_avx2 ?\n-\t\t\t\t ice_xmit_pkts_vec_avx2 :\n-\t\t\t\t ice_xmit_pkts_vec;\n+\t\tif (use_avx512) {\n+\t\t\tPMD_DRV_LOG(NOTICE, \"Using AVX512 Vector Tx (port %d).\",\n+\t\t\t\t dev->data->port_id);\n+\t\t\tdev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n+\t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n+\t\t\t\t dev->data->port_id);\n+\t\t\tdev->tx_pkt_burst = use_avx2 ?\n+\t\t\t\t\t ice_xmit_pkts_vec_avx2 :\n+\t\t\t\t\t ice_xmit_pkts_vec;\n+\t\t}\n \t\tdev->tx_pkt_prepare = NULL;\n \n \t\treturn;\n@@ -3148,6 +3197,9 @@ static const struct {\n \t{ ice_xmit_pkts_simple, \"Scalar Simple\" },\n \t{ ice_xmit_pkts, \"Scalar\" },\n #ifdef RTE_ARCH_X86\n+#ifdef CC_AVX512_SUPPORT\n+\t{ ice_xmit_pkts_vec_avx512, \"Vector AVX512\" },\n+#endif\n \t{ ice_xmit_pkts_vec_avx2, \"Vector AVX2\" },\n \t{ ice_xmit_pkts_vec, \"Vector SSE\" },\n #endif\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nindex 2fdcfb7d0..a39b41c05 100644\n--- a/drivers/net/ice/ice_rxtx.h\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -200,6 +200,13 @@ uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,\n \t\t\t\t\t uint16_t nb_pkts);\n uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\tuint16_t nb_pkts);\n+uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts);\n+uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue,\n+\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts);\n+uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\t uint16_t nb_pkts);\n int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);\n int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);\n \ndiff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c\nnew file mode 100644\nindex 000000000..6a9d0a8ea\n--- /dev/null\n+++ b/drivers/net/ice/ice_rxtx_vec_avx512.c\n@@ -0,0 +1,824 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#include \"ice_rxtx_vec_common.h\"\n+\n+#include <x86intrin.h>\n+\n+#ifndef __INTEL_COMPILER\n+#pragma GCC diagnostic ignored \"-Wcast-qual\"\n+#endif\n+\n+#define ICE_DESCS_PER_LOOP_AVX 8\n+\n+static inline void\n+ice_rxq_rearm(struct ice_rx_queue *rxq)\n+{\n+\tint i;\n+\tuint16_t rx_id;\n+\tvolatile union ice_rx_flex_desc *rxdp;\n+\tstruct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\n+\tstruct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,\n+\t\t\trte_lcore_id());\n+\n+\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\n+\t/* We need to pull 'n' more MBUFs into the software ring */\n+\tif (cache->len < ICE_RXQ_REARM_THRESH) {\n+\t\tuint32_t req = ICE_RXQ_REARM_THRESH + (cache->size -\n+\t\t\t\tcache->len);\n+\n+\t\tint ret = rte_mempool_ops_dequeue_bulk(rxq->mp,\n+\t\t\t\t&cache->objs[cache->len], req);\n+\t\tif (ret == 0) {\n+\t\t\tcache->len += req;\n+\t\t} else {\n+\t\t\tif (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=\n+\t\t\t rxq->nb_rx_desc) {\n+\t\t\t\t__m128i dma_addr0;\n+\n+\t\t\t\tdma_addr0 = _mm_setzero_si128();\n+\t\t\t\tfor (i = 0; i < ICE_DESCS_PER_LOOP; i++) {\n+\t\t\t\t\trxep[i].mbuf = &rxq->fake_mbuf;\n+\t\t\t\t\t_mm_store_si128\n+\t\t\t\t\t\t((__m128i *)&rxdp[i].read,\n+\t\t\t\t\t\t\tdma_addr0);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n+\t\t\t\tICE_RXQ_REARM_THRESH;\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tconst __m512i iova_offsets = _mm512_set1_epi64\n+\t\t(offsetof(struct rte_mbuf, buf_iova));\n+\tconst __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);\n+\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\t/* shuffle the iova into correct slots. Values 4-7 will contain\n+\t * zeros, so use 7 for a zero-value.\n+\t */\n+\tconst __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);\n+#else\n+\tconst __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);\n+#endif\n+\n+\t/* fill up the rxd in vector, process 8 mbufs in one loop */\n+\tfor (i = 0; i < ICE_RXQ_REARM_THRESH / 8; i++) {\n+\t\tconst __m512i mbuf_ptrs = _mm512_loadu_si512\n+\t\t\t(&cache->objs[cache->len - 8]);\n+\t\t_mm512_store_si512(rxep, mbuf_ptrs);\n+\n+\t\t/* gather iova of mbuf0-7 into one zmm reg */\n+\t\tconst __m512i iova_base_addrs = _mm512_i64gather_epi64\n+\t\t\t(_mm512_add_epi64(mbuf_ptrs, iova_offsets),\n+\t\t\t\t0, /* base */\n+\t\t\t\t1 /* scale */);\n+\t\tconst __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,\n+\t\t\t\theadroom);\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\t\tconst __m512i iovas0 = _mm512_castsi256_si512\n+\t\t\t(_mm512_extracti64x4_epi64(iova_addrs, 0));\n+\t\tconst __m512i iovas1 = _mm512_castsi256_si512\n+\t\t\t(_mm512_extracti64x4_epi64(iova_addrs, 1));\n+\n+\t\t/* permute leaves iova 2-3 in hdr_addr of desc 0-1\n+\t\t * but these are ignored by driver since header split not\n+\t\t * enabled. Similarly for desc 4 & 5.\n+\t\t */\n+\t\tconst __m512i desc0_1 = _mm512_permutexvar_epi64\n+\t\t\t(permute_idx, iovas0);\n+\t\tconst __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);\n+\n+\t\tconst __m512i desc4_5 = _mm512_permutexvar_epi64\n+\t\t\t(permute_idx, iovas1);\n+\t\tconst __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);\n+\n+\t\t_mm512_store_si512((void *)rxdp, desc0_1);\n+\t\t_mm512_store_si512((void *)(rxdp + 2), desc2_3);\n+\t\t_mm512_store_si512((void *)(rxdp + 4), desc4_5);\n+\t\t_mm512_store_si512((void *)(rxdp + 6), desc6_7);\n+#else\n+\t\t/* permute leaves iova 4-7 in hdr_addr of desc 0-3\n+\t\t * but these are ignored by driver since header split not\n+\t\t * enabled.\n+\t\t */\n+\t\tconst __m512i desc0_3 = _mm512_permutexvar_epi64\n+\t\t\t(permute_idx, iova_addrs);\n+\t\tconst __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);\n+\n+\t\t_mm512_store_si512((void *)rxdp, desc0_3);\n+\t\t_mm512_store_si512((void *)(rxdp + 4), desc4_7);\n+#endif\n+\t\trxep += 8, rxdp += 8, cache->len -= 8;\n+\t}\n+\n+\trxq->rxrearm_start += ICE_RXQ_REARM_THRESH;\n+\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n+\t\trxq->rxrearm_start = 0;\n+\n+\trxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;\n+\n+\trx_id = (uint16_t)((rxq->rxrearm_start == 0) ?\n+\t\t\t (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n+\n+\t/* Update the tail pointer on the NIC */\n+\tICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n+}\n+\n+static inline uint16_t\n+_ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq,\n+\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts, uint8_t *split_packet)\n+{\n+\tconst uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;\n+\tconst __m256i mbuf_init = _mm256_set_epi64x(0, 0,\n+\t\t\t0, rxq->mbuf_initializer);\n+\tstruct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];\n+\tvolatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;\n+\n+\trte_prefetch0(rxdp);\n+\n+\t/* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */\n+\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);\n+\n+\t/* See if we need to rearm the RX queue - gives the prefetch a bit\n+\t * of time to act\n+\t */\n+\tif (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)\n+\t\tice_rxq_rearm(rxq);\n+\n+\t/* Before we start moving massive data around, check to see if\n+\t * there is actually a packet available\n+\t */\n+\tif (!(rxdp->wb.status_error0 &\n+\t\t\trte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))\n+\t\treturn 0;\n+\n+\t/* constants used in processing loop */\n+\tconst __m512i crc_adjust =\n+\t\t_mm512_set4_epi32\n+\t\t\t(0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0 /* ignore non-length fields */\n+\t\t\t);\n+\n+\t/* 8 packets DD mask, LSB in each 32-bit value */\n+\tconst __m256i dd_check = _mm256_set1_epi32(1);\n+\n+\t/* 8 packets EOP mask, second-LSB in each 32-bit value */\n+\tconst __m256i eop_check = _mm256_slli_epi32(dd_check,\n+\t\t\tICE_RX_DESC_STATUS_EOF_S);\n+\n+\t/* mask to shuffle from desc. to mbuf (4 descriptors)*/\n+\tconst __m512i shuf_msk =\n+\t\t_mm512_set4_epi32\n+\t\t\t(/* octet 12~15, 32 bits rss */\n+\t\t\t 15 << 24 | 14 << 16 | 13 << 8 | 12,\n+\t\t\t /* octet 10~11, 16 bits vlan_macip */\n+\t\t\t /* octet 4~5, 16 bits data_len */\n+\t\t\t 11 << 24 | 10 << 16 | 5 << 8 | 4,\n+\t\t\t /* skip hi 16 bits pkt_len, zero out */\n+\t\t\t /* octet 4~5, 16 bits pkt_len */\n+\t\t\t 0xFFFF << 16 | 5 << 8 | 4,\n+\t\t\t /* pkt_type set as unknown */\n+\t\t\t 0xFFFFFFFF\n+\t\t\t);\n+\n+\t/**\n+\t * compile-time check the above crc and shuffle layout is correct.\n+\t * NOTE: the first field (lowest address) is given last in set_epi\n+\t * calls above.\n+\t */\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n+\n+\t/* Status/Error flag masks */\n+\t/**\n+\t * mask everything except Checksum Reports, RSS indication\n+\t * and VLAN indication.\n+\t * bit6:4 for IP/L4 checksum errors.\n+\t * bit12 is for RSS indication.\n+\t * bit13 is for VLAN indication.\n+\t */\n+\tconst __m256i flags_mask =\n+\t\t _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));\n+\t/**\n+\t * data to be shuffled by the result of the flags mask shifted by 4\n+\t * bits. This gives use the l3_l4 flags.\n+\t */\n+\tconst __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t/* shift right 1 bit to make sure it not exceed 255 */\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t/* 2nd 128-bits */\n+\t\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);\n+\tconst __m256i cksum_mask =\n+\t\t _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t PKT_RX_EIP_CKSUM_BAD);\n+\t/**\n+\t * data to be shuffled by result of flag mask, shifted down 12.\n+\t * If RSS(bit12)/VLAN(bit13) are set,\n+\t * shuffle moves appropriate flags in place.\n+\t */\n+\tconst __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_RSS_HASH, 0,\n+\t\t\t/* 2nd 128-bits */\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_RSS_HASH, 0);\n+\n+\tuint16_t i, received;\n+\n+\tfor (i = 0, received = 0; i < nb_pkts;\n+\t i += ICE_DESCS_PER_LOOP_AVX,\n+\t rxdp += ICE_DESCS_PER_LOOP_AVX) {\n+\t\t/* step 1, copy over 8 mbuf pointers to rx_pkts array */\n+\t\t_mm256_storeu_si256((void *)&rx_pkts[i],\n+\t\t\t\t _mm256_loadu_si256((void *)&sw_ring[i]));\n+#ifdef RTE_ARCH_X86_64\n+\t\t_mm256_storeu_si256\n+\t\t\t((void *)&rx_pkts[i + 4],\n+\t\t\t _mm256_loadu_si256((void *)&sw_ring[i + 4]));\n+#endif\n+\n+\t\t__m512i raw_desc0_3, raw_desc4_7;\n+\t\t__m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;\n+\n+\t\t/* load in descriptors, in reverse order */\n+\t\tconst __m128i raw_desc7 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 7));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc6 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 6));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc5 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 5));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc4 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 4));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc3 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 3));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc2 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 2));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc1 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 1));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc0 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 0));\n+\n+\t\traw_desc6_7 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc6),\n+\t\t\t\t raw_desc7, 1);\n+\t\traw_desc4_5 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc4),\n+\t\t\t\t raw_desc5, 1);\n+\t\traw_desc2_3 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc2),\n+\t\t\t\t raw_desc3, 1);\n+\t\traw_desc0_1 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc0),\n+\t\t\t\t raw_desc1, 1);\n+\n+\t\traw_desc4_7 =\n+\t\t\t_mm512_inserti64x4\n+\t\t\t\t(_mm512_castsi256_si512(raw_desc4_5),\n+\t\t\t\t raw_desc6_7, 1);\n+\t\traw_desc0_3 =\n+\t\t\t_mm512_inserti64x4\n+\t\t\t\t(_mm512_castsi256_si512(raw_desc0_1),\n+\t\t\t\t raw_desc2_3, 1);\n+\n+\t\tif (split_packet) {\n+\t\t\tint j;\n+\n+\t\t\tfor (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)\n+\t\t\t\trte_mbuf_prefetch_part2(rx_pkts[i + j]);\n+\t\t}\n+\n+\t\t/**\n+\t\t * convert descriptors 0-7 into mbufs, re-arrange fields.\n+\t\t * Then write into the mbuf.\n+\t\t */\n+\t\t__m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);\n+\t\t__m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);\n+\n+\t\tmb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);\n+\t\tmb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);\n+\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m512i ptype_mask =\n+\t\t\t_mm512_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);\n+\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m512i ptypes4_7 =\n+\t\t\t_mm512_and_si512(raw_desc4_7, ptype_mask);\n+\t\tconst __m512i ptypes0_3 =\n+\t\t\t_mm512_and_si512(raw_desc0_3, ptype_mask);\n+\n+\t\tconst __m256i ptypes6_7 =\n+\t\t\t_mm512_extracti64x4_epi64(ptypes4_7, 1);\n+\t\tconst __m256i ptypes4_5 =\n+\t\t\t_mm512_extracti64x4_epi64(ptypes4_7, 0);\n+\t\tconst __m256i ptypes2_3 =\n+\t\t\t_mm512_extracti64x4_epi64(ptypes0_3, 1);\n+\t\tconst __m256i ptypes0_1 =\n+\t\t\t_mm512_extracti64x4_epi64(ptypes0_3, 0);\n+\t\tconst uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);\n+\t\tconst uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);\n+\t\tconst uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);\n+\t\tconst uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);\n+\t\tconst uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);\n+\t\tconst uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);\n+\t\tconst uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);\n+\t\tconst uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);\n+\n+\t\tconst __m512i ptype4_7 = _mm512_set_epi32\n+\t\t\t(0, 0, 0, ptype_tbl[ptype7],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype6],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype5],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype4]);\n+\t\tconst __m512i ptype0_3 = _mm512_set_epi32\n+\t\t\t(0, 0, 0, ptype_tbl[ptype3],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype2],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype1],\n+\t\t\t 0, 0, 0, ptype_tbl[ptype0]);\n+\n+\t\tmb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);\n+\t\tmb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);\n+\n+\t\t/**\n+\t\t * use permute/extract to get status content\n+\t\t * After the operations, the packets status flags are in the\n+\t\t * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]\n+\t\t */\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m512i status_permute_msk = _mm512_set_epi32\n+\t\t\t(0, 0, 0, 0,\n+\t\t\t 0, 0, 0, 0,\n+\t\t\t 22, 30, 6, 14,\n+\t\t\t 18, 26, 2, 10);\n+\t\tconst __m512i raw_status0_7 = _mm512_permutex2var_epi32\n+\t\t\t(raw_desc4_7, status_permute_msk, raw_desc0_3);\n+\t\t__m256i status0_7 = _mm512_extracti64x4_epi64\n+\t\t\t(raw_status0_7, 0);\n+\n+\t\t/* now do flag manipulation */\n+\n+\t\t/* get only flag/error bits we want */\n+\t\tconst __m256i flag_bits =\n+\t\t\t_mm256_and_si256(status0_7, flags_mask);\n+\t\t/**\n+\t\t * l3_l4_error flags, shuffle, then shift to correct adjustment\n+\t\t * of flags in flags_shuf, and finally mask out extra bits\n+\t\t */\n+\t\t__m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,\n+\t\t\t\t_mm256_srli_epi32(flag_bits, 4));\n+\t\tl3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);\n+\t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);\n+\t\t/* set rss and vlan flags */\n+\t\tconst __m256i rss_vlan_flag_bits =\n+\t\t\t_mm256_srli_epi32(flag_bits, 12);\n+\t\tconst __m256i rss_vlan_flags =\n+\t\t\t_mm256_shuffle_epi8(rss_vlan_flags_shuf,\n+\t\t\t\t\t rss_vlan_flag_bits);\n+\n+\t\t/* merge flags */\n+\t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t\t\trss_vlan_flags);\n+\t\t/**\n+\t\t * At this point, we have the 8 sets of flags in the low 16-bits\n+\t\t * of each 32-bit value in vlan0.\n+\t\t * We want to extract these, and merge them with the mbuf init\n+\t\t * data so we can do a single write to the mbuf to set the flags\n+\t\t * and all the other initialization fields. Extracting the\n+\t\t * appropriate flags means that we have to do a shift and blend\n+\t\t * for each mbuf before we do the write. However, we can also\n+\t\t * add in the previously computed rx_descriptor fields to\n+\t\t * make a single 256-bit write per mbuf\n+\t\t */\n+\t\t/* check the structure matches expectations */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n+\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n+\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n+\t\t\t\t\t\t rearm_data),\n+\t\t\t\t\t 16));\n+\t\t/* build up data and do writes */\n+\t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n+\t\t\trearm6, rearm7;\n+\n+\t\trearm6 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm4 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);\n+\t\trearm0 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\n+\t\tconst __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);\n+\t\tconst __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);\n+\t\tconst __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);\n+\t\tconst __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);\n+\n+\t\t/* permute to add in the rx_descriptor e.g. rss fields */\n+\t\trearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);\n+\t\trearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);\n+\t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n+\t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n+\n+\t\t/* write to mbuf */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t\t\t rearm6);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t\t\t rearm4);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t\t\t rearm2);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t\t\t rearm0);\n+\n+\t\t/* repeat for the odd mbufs */\n+\t\tconst __m256i odd_flags =\n+\t\t\t_mm256_castsi128_si256\n+\t\t\t\t(_mm256_extracti128_si256(mbuf_flags, 1));\n+\t\trearm7 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm5 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);\n+\t\trearm1 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\n+\t\t/* since odd mbufs are already in hi 128-bits use blend */\n+\t\trearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);\n+\t\trearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);\n+\t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n+\t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n+\t\t/* again write to mbufs */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t\t\t rearm7);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t\t\t rearm5);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t\t\t rearm3);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t\t\t rearm1);\n+\n+\t\t/* extract and record EOP bit */\n+\t\tif (split_packet) {\n+\t\t\tconst __m128i eop_mask =\n+\t\t\t\t_mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);\n+\t\t\tconst __m256i eop_bits256 = _mm256_and_si256(status0_7,\n+\t\t\t\t\t\t\t\t eop_check);\n+\t\t\t/* pack status bits into a single 128-bit register */\n+\t\t\tconst __m128i eop_bits =\n+\t\t\t\t_mm_packus_epi32\n+\t\t\t\t\t(_mm256_castsi256_si128(eop_bits256),\n+\t\t\t\t\t _mm256_extractf128_si256(eop_bits256,\n+\t\t\t\t\t\t\t\t 1));\n+\t\t\t/**\n+\t\t\t * flip bits, and mask out the EOP bit, which is now\n+\t\t\t * a split-packet bit i.e. !EOP, rather than EOP one.\n+\t\t\t */\n+\t\t\t__m128i split_bits = _mm_andnot_si128(eop_bits,\n+\t\t\t\t\teop_mask);\n+\t\t\t/**\n+\t\t\t * eop bits are out of order, so we need to shuffle them\n+\t\t\t * back into order again. In doing so, only use low 8\n+\t\t\t * bits, which acts like another pack instruction\n+\t\t\t * The original order is (hi->lo): 1,3,5,7,0,2,4,6\n+\t\t\t * [Since we use epi8, the 16-bit positions are\n+\t\t\t * multiplied by 2 in the eop_shuffle value.]\n+\t\t\t */\n+\t\t\t__m128i eop_shuffle =\n+\t\t\t\t_mm_set_epi8(/* zero hi 64b */\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t /* move values to lo 64b */\n+\t\t\t\t\t 8, 0, 10, 2,\n+\t\t\t\t\t 12, 4, 14, 6);\n+\t\t\tsplit_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);\n+\t\t\t*(uint64_t *)split_packet =\n+\t\t\t\t_mm_cvtsi128_si64(split_bits);\n+\t\t\tsplit_packet += ICE_DESCS_PER_LOOP_AVX;\n+\t\t}\n+\n+\t\t/* perform dd_check */\n+\t\tstatus0_7 = _mm256_and_si256(status0_7, dd_check);\n+\t\tstatus0_7 = _mm256_packs_epi32(status0_7,\n+\t\t\t\t\t _mm256_setzero_si256());\n+\n+\t\tuint64_t burst = __builtin_popcountll\n+\t\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t\t(_mm256_extracti128_si256\n+\t\t\t\t\t\t\t(status0_7, 1)));\n+\t\tburst += __builtin_popcountll\n+\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t(_mm256_castsi256_si128(status0_7)));\n+\t\treceived += burst;\n+\t\tif (burst != ICE_DESCS_PER_LOOP_AVX)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* update tail pointers */\n+\trxq->rx_tail += received;\n+\trxq->rx_tail &= (rxq->nb_rx_desc - 1);\n+\tif ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */\n+\t\trxq->rx_tail--;\n+\t\treceived--;\n+\t}\n+\trxq->rxrearm_nb += received;\n+\treturn received;\n+}\n+\n+/**\n+ * Notice:\n+ * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\treturn _ice_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);\n+}\n+\n+/**\n+ * vPMD receive routine that reassembles single burst of 32 scattered packets\n+ * Notice:\n+ * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet\n+ */\n+static uint16_t\n+ice_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct ice_rx_queue *rxq = rx_queue;\n+\tuint8_t split_flags[ICE_VPMD_RX_BURST] = {0};\n+\n+\t/* get some new buffers */\n+\tuint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,\n+\t\t\t\t\t\t split_flags);\n+\tif (nb_bufs == 0)\n+\t\treturn 0;\n+\n+\t/* happy day case, full burst + no packets to be joined */\n+\tconst uint64_t *split_fl64 = (uint64_t *)split_flags;\n+\n+\tif (!rxq->pkt_first_seg &&\n+\t split_fl64[0] == 0 && split_fl64[1] == 0 &&\n+\t split_fl64[2] == 0 && split_fl64[3] == 0)\n+\t\treturn nb_bufs;\n+\n+\t/* reassemble any packets that need reassembly */\n+\tunsigned int i = 0;\n+\n+\tif (!rxq->pkt_first_seg) {\n+\t\t/* find the first split flag, and only reassemble then */\n+\t\twhile (i < nb_bufs && !split_flags[i])\n+\t\t\ti++;\n+\t\tif (i == nb_bufs)\n+\t\t\treturn nb_bufs;\n+\t\trxq->pkt_first_seg = rx_pkts[i];\n+\t}\n+\treturn i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,\n+\t\t\t\t\t &split_flags[i]);\n+}\n+\n+/**\n+ * vPMD receive routine that reassembles scattered packets.\n+ * Main receive routine that can handle arbitrary burst sizes\n+ * Notice:\n+ * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+ice_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t retval = 0;\n+\n+\twhile (nb_pkts > ICE_VPMD_RX_BURST) {\n+\t\tuint16_t burst = ice_recv_scattered_burst_vec_avx512(rx_queue,\n+\t\t\t\trx_pkts + retval, ICE_VPMD_RX_BURST);\n+\t\tretval += burst;\n+\t\tnb_pkts -= burst;\n+\t\tif (burst < ICE_VPMD_RX_BURST)\n+\t\t\treturn retval;\n+\t}\n+\treturn retval + ice_recv_scattered_burst_vec_avx512(rx_queue,\n+\t\t\t\trx_pkts + retval, nb_pkts);\n+}\n+\n+static inline void\n+ice_vtx1(volatile struct ice_tx_desc *txdp,\n+\t struct rte_mbuf *pkt, uint64_t flags)\n+{\n+\tuint64_t high_qw =\n+\t\t(ICE_TX_DESC_DTYPE_DATA |\n+\t\t ((uint64_t)flags << ICE_TXD_QW1_CMD_S) |\n+\t\t ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));\n+\n+\t__m128i descriptor = _mm_set_epi64x(high_qw,\n+\t\t\t\tpkt->buf_physaddr + pkt->data_off);\n+\t_mm_store_si128((__m128i *)txdp, descriptor);\n+}\n+\n+static inline void\n+ice_vtx(volatile struct ice_tx_desc *txdp,\n+\tstruct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n+{\n+\tconst uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |\n+\t\t\t((uint64_t)flags << ICE_TXD_QW1_CMD_S));\n+\n+\t/* if unaligned on 32-bit boundary, do one to align */\n+\tif (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {\n+\t\tice_vtx1(txdp, *pkt, flags);\n+\t\tnb_pkts--, txdp++, pkt++;\n+\t}\n+\n+\t/* do two at a time while possible, in bursts */\n+\tfor (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {\n+\t\tuint64_t hi_qw3 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[3]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw2 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[2]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw1 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[1]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw0 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[0]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\n+\t\t__m256i desc2_3 =\n+\t\t\t_mm256_set_epi64x\n+\t\t\t\t(hi_qw3,\n+\t\t\t\t pkt[3]->buf_physaddr + pkt[3]->data_off,\n+\t\t\t\t hi_qw2,\n+\t\t\t\t pkt[2]->buf_physaddr + pkt[2]->data_off);\n+\t\t__m256i desc0_1 =\n+\t\t\t_mm256_set_epi64x\n+\t\t\t\t(hi_qw1,\n+\t\t\t\t pkt[1]->buf_physaddr + pkt[1]->data_off,\n+\t\t\t\t hi_qw0,\n+\t\t\t\t pkt[0]->buf_physaddr + pkt[0]->data_off);\n+\t\t_mm256_store_si256((void *)(txdp + 2), desc2_3);\n+\t\t_mm256_store_si256((void *)txdp, desc0_1);\n+\t}\n+\n+\t/* do any last ones */\n+\twhile (nb_pkts) {\n+\t\tice_vtx1(txdp, *pkt, flags);\n+\t\ttxdp++, pkt++, nb_pkts--;\n+\t}\n+}\n+\n+static inline uint16_t\n+ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\tuint16_t nb_pkts)\n+{\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\tvolatile struct ice_tx_desc *txdp;\n+\tstruct ice_tx_entry *txep;\n+\tuint16_t n, nb_commit, tx_id;\n+\tuint64_t flags = ICE_TD_CMD;\n+\tuint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;\n+\n+\t/* cross rx_thresh boundary is not allowed */\n+\tnb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\n+\tif (txq->nb_tx_free < txq->tx_free_thresh)\n+\t\tice_tx_free_bufs(txq);\n+\n+\tnb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n+\tif (unlikely(nb_pkts == 0))\n+\t\treturn 0;\n+\n+\ttx_id = txq->tx_tail;\n+\ttxdp = &txq->tx_ring[tx_id];\n+\ttxep = &txq->sw_ring[tx_id];\n+\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n+\n+\tn = (uint16_t)(txq->nb_tx_desc - tx_id);\n+\tif (nb_commit >= n) {\n+\t\tice_tx_backlog_entry(txep, tx_pkts, n);\n+\n+\t\tice_vtx(txdp, tx_pkts, n - 1, flags);\n+\t\ttx_pkts += (n - 1);\n+\t\ttxdp += (n - 1);\n+\n+\t\tice_vtx1(txdp, *tx_pkts++, rs);\n+\n+\t\tnb_commit = (uint16_t)(nb_commit - n);\n+\n+\t\ttx_id = 0;\n+\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\t\t/* avoid reach the end of ring */\n+\t\ttxdp = &txq->tx_ring[tx_id];\n+\t\ttxep = &txq->sw_ring[tx_id];\n+\t}\n+\n+\tice_tx_backlog_entry(txep, tx_pkts, nb_commit);\n+\n+\tice_vtx(txdp, tx_pkts, nb_commit, flags);\n+\n+\ttx_id = (uint16_t)(tx_id + nb_commit);\n+\tif (tx_id > txq->tx_next_rs) {\n+\t\ttxq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=\n+\t\t\trte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<\n+\t\t\t\t\t ICE_TXD_QW1_CMD_S);\n+\t\ttxq->tx_next_rs =\n+\t\t\t(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);\n+\t}\n+\n+\ttxq->tx_tail = tx_id;\n+\n+\tICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n+\n+\treturn nb_pkts;\n+}\n+\n+uint16_t\n+ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t nb_tx = 0;\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\n+\twhile (nb_pkts) {\n+\t\tuint16_t ret, num;\n+\n+\t\tnum = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\t\tret = ice_xmit_fixed_burst_vec_avx512(tx_queue,\n+\t\t\t\t\t\t &tx_pkts[nb_tx], num);\n+\t\tnb_tx += ret;\n+\t\tnb_pkts -= ret;\n+\t\tif (ret < num)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn nb_tx;\n+}\ndiff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build\nindex e6fe74487..c0b23015e 100644\n--- a/drivers/net/ice/meson.build\n+++ b/drivers/net/ice/meson.build\n@@ -33,6 +33,19 @@ if arch_subdir == 'x86'\n \t\t\t\tc_args: [cflags, '-mavx2'])\n \t\tobjs += ice_avx2_lib.extract_objects('ice_rxtx_vec_avx2.c')\n \tendif\n+\n+\tif dpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512F') or not machine_args.contains('-mno-avx512f')\n+\t\tif cc.has_argument('-mavx512f') and cc.has_argument('-mavx512bw')\n+\t\t\tcflags += ['-DCC_AVX512_SUPPORT']\n+\t\t\tice_avx512_lib = static_library('ice_avx512_lib',\n+\t\t\t\t\t 'ice_rxtx_vec_avx512.c',\n+\t\t\t\t\t dependencies: [static_rte_ethdev,\n+\t\t\t\t\t\tstatic_rte_kvargs, static_rte_hash],\n+\t\t\t\t\t include_directories: includes,\n+\t\t\t\t\t c_args: [cflags, '-march=skylake-avx512', '-mavx512f'])\n+\t\t\tobjs += ice_avx512_lib.extract_objects('ice_rxtx_vec_avx512.c')\n+\t\tendif\n+\tendif\n endif\n \n sources += files('ice_dcf.c',\n", "prefixes": [ "v1", "1/2" ] }