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GET /api/patches/77107/?format=api
{ "id": 77107, "url": "http://patches.dpdk.org/api/patches/77107/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599717545-106571-2-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599717545-106571-2-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599717545-106571-2-git-send-email-wenzhuo.lu@intel.com", "date": "2020-09-10T05:59:03", "name": "[1/3] net/iavf: enable AVX512 for legacy RX", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "167f78064d2df0e35c11ab1160a157934ae927a9", "submitter": { "id": 258, "url": "http://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599717545-106571-2-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 12085, "url": "http://patches.dpdk.org/api/series/12085/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12085", "date": "2020-09-10T05:59:02", "name": "enable AVX512 for iavf", "version": 1, "mbox": "http://patches.dpdk.org/series/12085/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77107/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/77107/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 132A2A04B5;\n\tThu, 10 Sep 2020 07:59:50 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 591BB1C0D4;\n\tThu, 10 Sep 2020 07:59:47 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by dpdk.org (Postfix) with ESMTP id B9D531B9B7\n for <dev@dpdk.org>; Thu, 10 Sep 2020 07:59:43 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Sep 2020 22:59:43 -0700", "from dpdk-wenzhuo-haswell.sh.intel.com ([10.67.111.137])\n by orsmga004.jf.intel.com with ESMTP; 09 Sep 2020 22:59:41 -0700" ], "IronPort-SDR": [ "\n FTR+TtlZ+Fr2KcIDBZcLrWIggbWy2xJ2S/5cv9It/iM1FRvvgQARW3t4GFAmZcqdfbcbj6BqSN\n Hr8ey5k67CAQ==", "\n iDUreTlcBhXO5jQQoppRIfg8+HJ/I9fTY9HyvKWz+cnRRrywd9fBifpS4uYithtnkXXSSytagu\n w1bmqPBv3DpQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9739\"; a=\"158508469\"", "E=Sophos;i=\"5.76,412,1592895600\"; d=\"scan'208\";a=\"158508469\"", "E=Sophos;i=\"5.76,411,1592895600\"; d=\"scan'208\";a=\"449471213\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Leyi Rong <leyi.rong@intel.com>", "Date": "Thu, 10 Sep 2020 13:59:03 +0800", "Message-Id": "<1599717545-106571-2-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1599717545-106571-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1599717545-106571-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH 1/3] net/iavf: enable AVX512 for legacy RX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "To enhance the per-core performance, this patch adds some AVX512\ninstructions to the data path to handle the legacy RX descriptors.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/iavf/iavf_rxtx.c | 27 +-\n drivers/net/iavf/iavf_rxtx.h | 5 +\n drivers/net/iavf/iavf_rxtx_vec_avx512.c | 720 ++++++++++++++++++++++++++++++++\n drivers/net/iavf/meson.build | 7 +\n 4 files changed, 755 insertions(+), 4 deletions(-)\n create mode 100644 drivers/net/iavf/iavf_rxtx_vec_avx512.c", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\nindex 05a7dd8..c36e809 100644\n--- a/drivers/net/iavf/iavf_rxtx.c\n+++ b/drivers/net/iavf/iavf_rxtx.c\n@@ -2104,6 +2104,9 @@\n \tstruct iavf_rx_queue *rxq;\n \tint i;\n \tbool use_avx2 = false;\n+#ifdef CC_AVX512_SUPPORT\n+\tbool use_avx512 = false;\n+#endif\n \n \tif (!iavf_rx_vec_dev_check(dev)) {\n \t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n@@ -2114,6 +2117,10 @@\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n \t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)\n \t\t\tuse_avx2 = true;\n+#ifdef CC_AVX512_SUPPORT\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)\n+\t\t\tuse_avx512 = true;\n+#endif\n \n \t\tif (dev->data->scattered_rx) {\n \t\t\tPMD_DRV_LOG(DEBUG,\n@@ -2121,27 +2128,39 @@\n \t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t dev->data->port_id);\n \t\t\tif (vf->vf_res->vf_cap_flags &\n-\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)\n+\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {\n \t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n \t\t\t\t\tiavf_recv_scattered_pkts_vec_avx2_flex_rxd :\n \t\t\t\t\tiavf_recv_scattered_pkts_vec_flex_rxd;\n-\t\t\telse\n+\t\t\t} else {\n \t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n \t\t\t\t\tiavf_recv_scattered_pkts_vec_avx2 :\n \t\t\t\t\tiavf_recv_scattered_pkts_vec;\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\t\tif (use_avx512)\n+\t\t\t\t\tdev->rx_pkt_burst =\n+\t\t\t\t\t\tiavf_recv_scattered_pkts_vec_avx512;\n+#endif\n+\t\t\t}\n \t\t} else {\n \t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Rx (port %d).\",\n \t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n \t\t\t\t dev->data->port_id);\n \t\t\tif (vf->vf_res->vf_cap_flags &\n-\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)\n+\t\t\t\tVIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {\n \t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n \t\t\t\t\tiavf_recv_pkts_vec_avx2_flex_rxd :\n \t\t\t\t\tiavf_recv_pkts_vec_flex_rxd;\n-\t\t\telse\n+\t\t\t} else {\n \t\t\t\tdev->rx_pkt_burst = use_avx2 ?\n \t\t\t\t\tiavf_recv_pkts_vec_avx2 :\n \t\t\t\t\tiavf_recv_pkts_vec;\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\t\tif (use_avx512)\n+\t\t\t\t\tdev->rx_pkt_burst =\n+\t\t\t\t\t\tiavf_recv_pkts_vec_avx512;\n+#endif\n+\t\t\t}\n \t\t}\n \n \t\treturn;\ndiff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h\nindex 59625a9..cb12888 100644\n--- a/drivers/net/iavf/iavf_rxtx.h\n+++ b/drivers/net/iavf/iavf_rxtx.h\n@@ -437,6 +437,11 @@ uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);\n int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);\n int iavf_txq_vec_setup(struct iavf_tx_queue *txq);\n+uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts);\n+uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,\n+\t\t\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts);\n \n const uint32_t *iavf_get_default_ptype_table(void);\n \ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\nnew file mode 100644\nindex 0000000..b528ed3\n--- /dev/null\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n@@ -0,0 +1,720 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include \"iavf_rxtx_vec_common.h\"\n+\n+#include <x86intrin.h>\n+\n+#ifndef __INTEL_COMPILER\n+#pragma GCC diagnostic ignored \"-Wcast-qual\"\n+#endif\n+\n+#define IAVF_DESCS_PER_LOOP_AVX 8\n+#define PKTLEN_SHIFT 10\n+\n+__attribute__((optimize(\"unroll-loops\"))) __rte_always_inline\n+static inline void\n+iavf_rxq_rearm(struct iavf_rx_queue *rxq)\n+{\n+\tint i;\n+\tuint16_t rx_id;\n+\tvolatile union iavf_rx_desc *rxdp;\n+\tstruct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,\n+\t\t\trte_lcore_id());\n+\tstruct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];\n+\n+\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\n+\t/* We need to pull 'n' more MBUFs into the software ring from mempool\n+\t * We inline the mempool function here, so we can vectorize the copy\n+\t * from the cache into the shadow ring.\n+\t */\n+\n+\t/* Can this be satisfied from the cache? */\n+\tif (cache->len < IAVF_RXQ_REARM_THRESH) {\n+\t\t/* No. Backfill the cache first, and then fill from it */\n+\t\tuint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -\n+\t\t\t\tcache->len);\n+\n+\t\t/* How many do we require i.e. number to fill the cache + the request */\n+\t\tint ret = rte_mempool_ops_dequeue_bulk(rxq->mp,\n+\t\t\t\t&cache->objs[cache->len], req);\n+\t\tif (ret == 0) {\n+\t\t\tcache->len += req;\n+\t\t} else {\n+\t\t\tif (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=\n+\t\t\t\t\trxq->nb_rx_desc) {\n+\t\t\t\t__m128i dma_addr0;\n+\n+\t\t\t\tdma_addr0 = _mm_setzero_si128();\n+\t\t\t\tfor (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {\n+\t\t\t\t\trxp[i] = &rxq->fake_mbuf;\n+\t\t\t\t\t_mm_storeu_si128((__m128i *)&rxdp[i].read,\n+\t\t\t\t\t\t\t dma_addr0);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n+\t\t\t\t\tIAVF_RXQ_REARM_THRESH;\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tconst __m512i iova_offsets = _mm512_set1_epi64(offsetof\n+\t\t\t(struct rte_mbuf, buf_iova));\n+\tconst __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);\n+\n+#ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC\n+\t/* to shuffle the addresses to correct slots. Values 4-7 will contain\n+\t * zeros, so use 7 for a zero-value.\n+\t */\n+\tconst __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);\n+#else\n+\tconst __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);\n+#endif\n+\n+\t/* Initialize the mbufs in vector, process 8 mbufs in one loop, taking\n+\t * from mempool cache and populating both shadow and HW rings\n+\t */\n+\tfor (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {\n+\t\tconst __m512i mbuf_ptrs = _mm512_loadu_si512\n+\t\t\t(&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);\n+\t\t_mm512_storeu_si512(rxp, mbuf_ptrs);\n+\n+\t\tconst __m512i iova_base_addrs = _mm512_i64gather_epi64\n+\t\t\t\t(_mm512_add_epi64(mbuf_ptrs, iova_offsets),\n+\t\t\t\t 0, /* base */\n+\t\t\t\t 1 /* scale */);\n+\t\tconst __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,\n+\t\t\t\theadroom);\n+#ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC\n+\t\tconst __m512i iovas0 = _mm512_castsi256_si512\n+\t\t\t\t(_mm512_extracti64x4_epi64(iova_addrs, 0));\n+\t\tconst __m512i iovas1 = _mm512_castsi256_si512\n+\t\t\t\t(_mm512_extracti64x4_epi64(iova_addrs, 1));\n+\n+\t\t/* permute leaves desc 2-3 addresses in header address slots 0-1\n+\t\t * but these are ignored by driver since header split not\n+\t\t * enabled. Similarly for desc 6 & 7.\n+\t\t */\n+\t\tconst __m512i desc0_1 = _mm512_permutexvar_epi64\n+\t\t\t\t(permute_idx,\n+\t\t\t\t iovas0);\n+\t\tconst __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);\n+\n+\t\tconst __m512i desc4_5 = _mm512_permutexvar_epi64\n+\t\t\t\t(permute_idx,\n+\t\t\t\t iovas1);\n+\t\tconst __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);\n+\n+\t\t_mm512_storeu_si512((void *)rxdp, desc0_1);\n+\t\t_mm512_storeu_si512((void *)(rxdp + 2), desc2_3);\n+\t\t_mm512_storeu_si512((void *)(rxdp + 4), desc4_5);\n+\t\t_mm512_storeu_si512((void *)(rxdp + 6), desc6_7);\n+#else\n+\t\t/* permute leaves desc 4-7 addresses in header address slots 0-3\n+\t\t * but these are ignored by driver since header split not\n+\t\t * enabled.\n+\t\t */\n+\t\tconst __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx, iova_addrs);\n+\t\tconst __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);\n+\n+\t\t_mm512_storeu_si512((void *)rxdp, desc0_3);\n+\t\t_mm512_storeu_si512((void *)(rxdp + 4), desc4_7);\n+#endif\n+\t\trxp += IAVF_DESCS_PER_LOOP_AVX;\n+\t\trxdp += IAVF_DESCS_PER_LOOP_AVX;\n+\t\tcache->len -= IAVF_DESCS_PER_LOOP_AVX;\n+\t}\n+\n+\trxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;\n+\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n+\t\trxq->rxrearm_start = 0;\n+\n+\trxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;\n+\n+\trx_id = (uint16_t)((rxq->rxrearm_start == 0) ?\n+\t\t\t (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n+\n+\t/* Update the tail pointer on the NIC */\n+\tIAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n+}\n+\n+static inline uint16_t\n+_iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,\n+\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts, uint8_t *split_packet)\n+{\n+\t/* const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; */\n+\tconst uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;\n+\n+\tconst __m256i mbuf_init = _mm256_set_epi64x(0, 0,\n+\t\t\t0, rxq->mbuf_initializer);\n+\t/* struct iavf_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail]; */\n+\tstruct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];\n+\tvolatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;\n+\tconst __mmask32 len_mask = _cvtu32_mask32(0x80808080);\n+\n+\trte_prefetch0(rxdp);\n+\n+\t/* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */\n+\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);\n+\n+\t/* See if we need to rearm the RX queue - gives the prefetch a bit\n+\t * of time to act\n+\t */\n+\tif (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)\n+\t\tiavf_rxq_rearm(rxq);\n+\n+\t/* Before we start moving massive data around, check to see if\n+\t * there is actually a packet available\n+\t */\n+\tif (!(rxdp->wb.qword1.status_error_len &\n+\t\t\trte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))\n+\t\treturn 0;\n+\n+\t/* constants used in processing loop */\n+\tconst __m512i crc_adjust =\n+\t\t_mm512_set_epi16\n+\t\t\t(/* 1st descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0, /* ignore pkt_type field */\n+\t\t\t /* 2nd descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0, /* ignore pkt_type field */\n+\t\t\t /* 3rd descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0, /* ignore pkt_type field */\n+\t\t\t /* 4th descriptor */\n+\t\t\t 0, 0, 0, /* ignore non-length fields */\n+\t\t\t -rxq->crc_len, /* sub crc on data_len */\n+\t\t\t 0, /* ignore high-16bits of pkt_len */\n+\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n+\t\t\t 0, 0 /* ignore pkt_type field */\n+\t\t\t);\n+\n+\t/* 8 packets DD mask, LSB in each 32-bit value */\n+\tconst __m256i dd_check = _mm256_set1_epi32(1);\n+\n+\t/* 8 packets EOP mask, second-LSB in each 32-bit value */\n+\tconst __m256i eop_check = _mm256_slli_epi32(dd_check,\n+\t\t\tIAVF_RX_DESC_STATUS_EOF_SHIFT);\n+\n+\t/* mask to shuffle from desc. to mbuf (4 descriptors)*/\n+\tconst __m512i shuf_msk =\n+\t\t_mm512_set_epi8\n+\t\t\t(/* 1st descriptor */\n+\t\t\t 7, 6, 5, 4, /* octet 4~7, 32bits rss */\n+\t\t\t 3, 2, /* octet 2~3, low 16 bits vlan_macip */\n+\t\t\t 15, 14, /* octet 15~14, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t 15, 14, /* octet 15~14, low 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF, /*pkt_type set as unknown */\n+\t\t\t /* 2nd descriptor */\n+\t\t\t 7, 6, 5, 4, /* octet 4~7, 32bits rss */\n+\t\t\t 3, 2, /* octet 2~3, low 16 bits vlan_macip */\n+\t\t\t 15, 14, /* octet 15~14, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t 15, 14, /* octet 15~14, low 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF, /*pkt_type set as unknown */\n+\t\t\t /* 3rd descriptor */\n+\t\t\t 7, 6, 5, 4, /* octet 4~7, 32bits rss */\n+\t\t\t 3, 2, /* octet 2~3, low 16 bits vlan_macip */\n+\t\t\t 15, 14, /* octet 15~14, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t 15, 14, /* octet 15~14, low 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF, /*pkt_type set as unknown */\n+\t\t\t /* 4th descriptor */\n+\t\t\t 7, 6, 5, 4, /* octet 4~7, 32bits rss */\n+\t\t\t 3, 2, /* octet 2~3, low 16 bits vlan_macip */\n+\t\t\t 15, 14, /* octet 15~14, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t 15, 14, /* octet 15~14, low 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF /*pkt_type set as unknown */\n+\t\t\t);\n+\t/**\n+\t * compile-time check the above crc and shuffle layout is correct.\n+\t * NOTE: the first field (lowest address) is given last in set_epi\n+\t * calls above.\n+\t */\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n+\n+\t/* Status/Error flag masks */\n+\t/**\n+\t * mask everything except RSS, flow director and VLAN flags\n+\t * bit2 is for VLAN tag, bit11 for flow director indication\n+\t * bit13:12 for RSS indication. Bits 3-5 of error\n+\t * field (bits 22-24) are for IP/L4 checksum errors\n+\t */\n+\tconst __m256i flags_mask =\n+\t\t _mm256_set1_epi32((1 << 2) | (1 << 11) |\n+\t\t\t\t (3 << 12) | (7 << 22));\n+\t/**\n+\t * data to be shuffled by result of flag mask. If VLAN bit is set,\n+\t * (bit 2), then position 4 in this array will be used in the\n+\t * destination\n+\t */\n+\tconst __m256i vlan_flags_shuf =\n+\t\t_mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,\n+\t\t\t\t 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);\n+\t/**\n+\t * data to be shuffled by result of flag mask, shifted down 11.\n+\t * If RSS/FDIR bits are set, shuffle moves appropriate flags in\n+\t * place.\n+\t */\n+\tconst __m256i rss_flags_shuf =\n+\t\t_mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t\tPKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,\n+\t\t\t\t0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */\n+\t\t\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t\tPKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,\n+\t\t\t\t0, 0, 0, 0, PKT_RX_FDIR, 0);\n+\n+\t/**\n+\t * data to be shuffled by the result of the flags mask shifted by 22\n+\t * bits. This gives use the l3_l4 flags.\n+\t */\n+\tconst __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t/* shift right 1 bit to make sure it not exceed 255 */\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |\n+\t\t\t PKT_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\tPKT_RX_IP_CKSUM_BAD >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t/* second 128-bits */\n+\t\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |\n+\t\t\t PKT_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\tPKT_RX_IP_CKSUM_BAD >> 1,\n+\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);\n+\n+\tconst __m256i cksum_mask =\n+\t\t _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t PKT_RX_EIP_CKSUM_BAD);\n+\n+\tuint16_t i, received;\n+\n+\tfor (i = 0, received = 0; i < nb_pkts;\n+\t i += IAVF_DESCS_PER_LOOP_AVX,\n+\t rxdp += IAVF_DESCS_PER_LOOP_AVX) {\n+\t\t/* step 1, copy over 8 mbuf pointers to rx_pkts array */\n+\t\t_mm256_storeu_si256((void *)&rx_pkts[i],\n+\t\t\t\t _mm256_loadu_si256((void *)&sw_ring[i]));\n+#ifdef RTE_ARCH_X86_64\n+\t\t_mm256_storeu_si256\n+\t\t\t((void *)&rx_pkts[i + 4],\n+\t\t\t _mm256_loadu_si256((void *)&sw_ring[i + 4]));\n+#endif\n+\n+\t\t__m512i raw_desc0_3, raw_desc4_7;\n+\t\tconst __m128i raw_desc7 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 7));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc6 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 6));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc5 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 5));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc4 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 4));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc3 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 3));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc2 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 2));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc1 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 1));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc0 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 0));\n+\n+\t\traw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);\n+\t\traw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);\n+\t\traw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);\n+\t\traw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);\n+\t\traw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);\n+\t\traw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);\n+\t\traw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);\n+\t\traw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);\n+\n+\t\tif (split_packet) {\n+\t\t\tint j;\n+\n+\t\t\tfor (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)\n+\t\t\t\trte_mbuf_prefetch_part2(rx_pkts[i + j]);\n+\t\t}\n+\n+\t\t/**\n+\t\t * convert descriptors 4-7 into mbufs, adjusting length and\n+\t\t * re-arranging fields. Then write into the mbuf\n+\t\t */\n+\t\tconst __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,\n+\t\t\t\t\t\t\t PKTLEN_SHIFT);\n+\t\tconst __m512i desc4_7 = _mm512_mask_blend_epi16(len_mask,\n+\t\t\t\t\t\t\t\traw_desc4_7,\n+\t\t\t\t\t\t\t\tlen4_7);\n+\t\t__m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);\n+\n+\t\tmb4_7 = _mm512_add_epi16(mb4_7, crc_adjust);\n+\t\t/**\n+\t\t * to get packet types, shift 64-bit values down 30 bits\n+\t\t * and so ptype is in lower 8-bits in each\n+\t\t */\n+\t\tconst __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);\n+\t\tconst __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);\n+\t\tconst __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);\n+\t\tconst uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);\n+\t\tconst uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);\n+\t\tconst uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);\n+\t\tconst uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);\n+\n+\t\tconst __m512i ptype4_7 = _mm512_set_epi32\n+\t\t\t(0, 0, 0, type_table[ptype7],\n+\t\t\t 0, 0, 0, type_table[ptype6],\n+\t\t\t 0, 0, 0, type_table[ptype5],\n+\t\t\t 0, 0, 0, type_table[ptype4]);\n+\t\tmb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);\n+\n+\t\t/**\n+\t\t * convert descriptors 0-3 into mbufs, adjusting length and\n+\t\t * re-arranging fields. Then write into the mbuf\n+\t\t */\n+\t\tconst __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,\n+\t\t\t\t\t\t\t PKTLEN_SHIFT);\n+\t\tconst __m512i desc0_3 = _mm512_mask_blend_epi16(len_mask,\n+\t\t\t\t\t\t\t\traw_desc0_3,\n+\t\t\t\t\t\t\t\tlen0_3);\n+\t\t__m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);\n+\n+\t\tmb0_3 = _mm512_add_epi16(mb0_3, crc_adjust);\n+\t\t/* get the packet types */\n+\t\tconst __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);\n+\t\tconst __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);\n+\t\tconst __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);\n+\t\tconst uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);\n+\t\tconst uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);\n+\t\tconst uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);\n+\t\tconst uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);\n+\n+\t\tconst __m512i ptype0_3 = _mm512_set_epi32\n+\t\t\t(0, 0, 0, type_table[ptype3],\n+\t\t\t 0, 0, 0, type_table[ptype2],\n+\t\t\t 0, 0, 0, type_table[ptype1],\n+\t\t\t 0, 0, 0, type_table[ptype0]);\n+\t\tmb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);\n+\n+\t\t/**\n+\t\t * use permute/extract to get status content\n+\t\t * After the operations, the packets status flags are in the\n+\t\t * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]\n+\t\t */\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m512i status_permute_msk = _mm512_set_epi32\n+\t\t\t(0, 0, 0, 0,\n+\t\t\t 0, 0, 0, 0,\n+\t\t\t 22, 30, 6, 14,\n+\t\t\t 18, 26, 2, 10);\n+\t\tconst __m512i raw_status0_7 = _mm512_permutex2var_epi32\n+\t\t\t(raw_desc4_7, status_permute_msk, raw_desc0_3);\n+\t\t__m256i status0_7 = _mm512_extracti64x4_epi64\n+\t\t\t(raw_status0_7, 0);\n+\n+\t\t/* now do flag manipulation */\n+\n+\t\t/* get only flag/error bits we want */\n+\t\tconst __m256i flag_bits =\n+\t\t\t_mm256_and_si256(status0_7, flags_mask);\n+\t\t/* set vlan and rss flags */\n+\t\tconst __m256i vlan_flags =\n+\t\t\t_mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);\n+\t\tconst __m256i rss_flags =\n+\t\t\t_mm256_shuffle_epi8(rss_flags_shuf,\n+\t\t\t\t\t _mm256_srli_epi32(flag_bits, 11));\n+\t\t/**\n+\t\t * l3_l4_error flags, shuffle, then shift to correct adjustment\n+\t\t * of flags in flags_shuf, and finally mask out extra bits\n+\t\t */\n+\t\t__m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,\n+\t\t\t\t_mm256_srli_epi32(flag_bits, 22));\n+\t\tl3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);\n+\t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);\n+\n+\t\t/* merge flags */\n+\t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t\t\t_mm256_or_si256(rss_flags, vlan_flags));\n+\t\t/**\n+\t\t * At this point, we have the 8 sets of flags in the low 16-bits\n+\t\t * of each 32-bit value in vlan0.\n+\t\t * We want to extract these, and merge them with the mbuf init\n+\t\t * data so we can do a single write to the mbuf to set the flags\n+\t\t * and all the other initialization fields. Extracting the\n+\t\t * appropriate flags means that we have to do a shift and blend\n+\t\t * for each mbuf before we do the write. However, we can also\n+\t\t * add in the previously computed rx_descriptor fields to\n+\t\t * make a single 256-bit write per mbuf\n+\t\t */\n+\t\t/* check the structure matches expectations */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n+\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n+\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n+\t\t\t\t\t\t rearm_data),\n+\t\t\t\t\t 16));\n+\t\t/* build up data and do writes */\n+\t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n+\t\t\trearm6, rearm7;\n+\t\tconst __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);\n+\t\tconst __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);\n+\t\tconst __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);\n+\t\tconst __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);\n+\n+\t\trearm6 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm4 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);\n+\t\trearm0 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(mbuf_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\t/* permute to add in the rx_descriptor e.g. rss fields */\n+\t\trearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);\n+\t\trearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);\n+\t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n+\t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n+\t\t/* write to mbuf */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t\t\t rearm6);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t\t\t rearm4);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t\t\t rearm2);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t\t\t rearm0);\n+\n+\t\t/* repeat for the odd mbufs */\n+\t\tconst __m256i odd_flags =\n+\t\t\t_mm256_castsi128_si256\n+\t\t\t\t(_mm256_extracti128_si256(mbuf_flags, 1));\n+\t\trearm7 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 8),\n+\t\t\t\t\t 0x04);\n+\t\trearm5 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_slli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\trearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);\n+\t\trearm1 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t _mm256_srli_si256(odd_flags, 4),\n+\t\t\t\t\t 0x04);\n+\t\t/* since odd mbufs are already in hi 128-bits use blend */\n+\t\trearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);\n+\t\trearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);\n+\t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n+\t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n+\t\t/* again write to mbufs */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t\t\t rearm7);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t\t\t rearm5);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t\t\t rearm3);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t\t\t rearm1);\n+\n+\t\t/* extract and record EOP bit */\n+\t\tif (split_packet) {\n+\t\t\tconst __m128i eop_mask =\n+\t\t\t\t_mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);\n+\t\t\tconst __m256i eop_bits256 = _mm256_and_si256(status0_7,\n+\t\t\t\t\t\t\t\t eop_check);\n+\t\t\t/* pack status bits into a single 128-bit register */\n+\t\t\tconst __m128i eop_bits =\n+\t\t\t\t_mm_packus_epi32\n+\t\t\t\t\t(_mm256_castsi256_si128(eop_bits256),\n+\t\t\t\t\t _mm256_extractf128_si256(eop_bits256,\n+\t\t\t\t\t\t\t\t 1));\n+\t\t\t/**\n+\t\t\t * flip bits, and mask out the EOP bit, which is now\n+\t\t\t * a split-packet bit i.e. !EOP, rather than EOP one.\n+\t\t\t */\n+\t\t\t__m128i split_bits = _mm_andnot_si128(eop_bits,\n+\t\t\t\t\teop_mask);\n+\t\t\t/**\n+\t\t\t * eop bits are out of order, so we need to shuffle them\n+\t\t\t * back into order again. In doing so, only use low 8\n+\t\t\t * bits, which acts like another pack instruction\n+\t\t\t * The original order is (hi->lo): 1,3,5,7,0,2,4,6\n+\t\t\t * [Since we use epi8, the 16-bit positions are\n+\t\t\t * multiplied by 2 in the eop_shuffle value.]\n+\t\t\t */\n+\t\t\t__m128i eop_shuffle =\n+\t\t\t\t_mm_set_epi8(/* zero hi 64b */\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t 0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t /* move values to lo 64b */\n+\t\t\t\t\t 8, 0, 10, 2,\n+\t\t\t\t\t 12, 4, 14, 6);\n+\t\t\tsplit_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);\n+\t\t\t*(uint64_t *)split_packet =\n+\t\t\t\t_mm_cvtsi128_si64(split_bits);\n+\t\t\tsplit_packet += IAVF_DESCS_PER_LOOP_AVX;\n+\t\t}\n+\n+\t\t/* perform dd_check */\n+\t\tstatus0_7 = _mm256_and_si256(status0_7, dd_check);\n+\t\tstatus0_7 = _mm256_packs_epi32(status0_7,\n+\t\t\t\t\t _mm256_setzero_si256());\n+\n+\t\tuint64_t burst = __builtin_popcountll\n+\t\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t\t(_mm256_extracti128_si256\n+\t\t\t\t\t\t\t(status0_7, 1)));\n+\t\tburst += __builtin_popcountll\n+\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t(_mm256_castsi256_si128(status0_7)));\n+\t\treceived += burst;\n+\t\tif (burst != IAVF_DESCS_PER_LOOP_AVX)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* update tail pointers */\n+\trxq->rx_tail += received;\n+\trxq->rx_tail &= (rxq->nb_rx_desc - 1);\n+\tif ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */\n+\t\trxq->rx_tail--;\n+\t\treceived--;\n+\t}\n+\trxq->rxrearm_nb += received;\n+\treturn received;\n+}\n+\n+static inline __m256i\n+flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)\n+{\n+#define FDID_MIS_MAGIC 0xFFFFFFFF\n+\tRTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));\n+\tRTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));\n+\tconst __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |\n+\t\t\tPKT_RX_FDIR_ID);\n+\t/* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */\n+\tconst __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);\n+\t__m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,\n+\t\t\tfdir_mis_mask);\n+\t/* this XOR op results to bit-reverse the fdir_mask */\n+\tfdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);\n+\tconst __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);\n+\n+\treturn fdir_flags;\n+}\n+\n+/**\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\treturn _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);\n+}\n+\n+/**\n+ * vPMD receive routine that reassembles single burst of 32 scattered packets\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+static uint16_t\n+iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct iavf_rx_queue *rxq = rx_queue;\n+\tuint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};\n+\n+\t/* get some new buffers */\n+\tuint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,\n+\t\t\t\t\t\t\t split_flags);\n+\tif (nb_bufs == 0)\n+\t\treturn 0;\n+\n+\t/* happy day case, full burst + no packets to be joined */\n+\tconst uint64_t *split_fl64 = (uint64_t *)split_flags;\n+\n+\tif (!rxq->pkt_first_seg &&\n+\t split_fl64[0] == 0 && split_fl64[1] == 0 &&\n+\t split_fl64[2] == 0 && split_fl64[3] == 0)\n+\t\treturn nb_bufs;\n+\n+\t/* reassemble any packets that need reassembly*/\n+\tunsigned int i = 0;\n+\n+\tif (!rxq->pkt_first_seg) {\n+\t\t/* find the first split flag, and only reassemble then*/\n+\t\twhile (i < nb_bufs && !split_flags[i])\n+\t\t\ti++;\n+\t\tif (i == nb_bufs)\n+\t\t\treturn nb_bufs;\n+\t\trxq->pkt_first_seg = rx_pkts[i];\n+\t}\n+\treturn i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,\n+\t\t\t\t\t &split_flags[i]);\n+}\n+\n+/**\n+ * vPMD receive routine that reassembles scattered packets.\n+ * Main receive routine that can handle arbitrary burst sizes\n+ * Notice:\n+ * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t retval = 0;\n+\n+\twhile (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {\n+\t\tuint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,\n+\t\t\t\trx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);\n+\t\tretval += burst;\n+\t\tnb_pkts -= burst;\n+\t\tif (burst < IAVF_VPMD_RX_MAX_BURST)\n+\t\t\treturn retval;\n+\t}\n+\treturn retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,\n+\t\t\t\trx_pkts + retval, nb_pkts);\n+}\ndiff --git a/drivers/net/iavf/meson.build b/drivers/net/iavf/meson.build\nindex a3fad36..6427885 100644\n--- a/drivers/net/iavf/meson.build\n+++ b/drivers/net/iavf/meson.build\n@@ -34,4 +34,11 @@ if arch_subdir == 'x86'\n \t\t\t\tc_args: [cflags, '-mavx2'])\n \t\tobjs += iavf_avx2_lib.extract_objects('iavf_rxtx_vec_avx2.c')\n \tendif\n+\n+\tif dpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512F')\n+\t\tcflags += ['-DCC_AVX512_SUPPORT']\n+\t\tcflags += ['-mavx512f']\n+\t\tcflags += ['-march=skylake-avx512']\n+\t\tsources += files('iavf_rxtx_vec_avx512.c')\n+\tendif\n endif\n", "prefixes": [ "1/3" ] }