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GET /api/patches/77007/?format=api
{ "id": 77007, "url": "http://patches.dpdk.org/api/patches/77007/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599634114-148013-4-git-send-email-jiaweiw@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599634114-148013-4-git-send-email-jiaweiw@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599634114-148013-4-git-send-email-jiaweiw@nvidia.com", "date": "2020-09-09T06:48:25", "name": "[v6,03/12] common/mlx5: query sampler object capability via DevX", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8e2ad20b11b6020e031f46e1c93efd23fd5677ee", "submitter": { "id": 1939, "url": "http://patches.dpdk.org/api/people/1939/?format=api", "name": "Jiawei Wang", "email": "jiaweiw@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599634114-148013-4-git-send-email-jiaweiw@nvidia.com/mbox/", "series": [ { "id": 12045, "url": "http://patches.dpdk.org/api/series/12045/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12045", "date": "2020-09-09T06:48:29", "name": "support the flow-based traffic sampling", "version": 6, "mbox": "http://patches.dpdk.org/series/12045/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77007/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77007/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B31F4A04B1;\n\tWed, 9 Sep 2020 08:50:01 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5CBD61C136;\n\tWed, 9 Sep 2020 08:48:49 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id B89931C0D0\n for <dev@dpdk.org>; Wed, 9 Sep 2020 08:48:36 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n jiaweiw@nvidia.com) with SMTP; 9 Sep 2020 09:48:34 +0300", "from nvidia.com (gen-l-vrt-280.mtl.labs.mlnx [10.237.45.1])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0896mYFw029471;\n Wed, 9 Sep 2020 09:48:34 +0300" ], "From": "Jiawei Wang <jiaweiw@nvidia.com>", "To": "orika@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com,\n thomas@monjalon.net, ferruh.yigit@intel.com, marko.kovacevic@intel.com,\n arybchenko@solarflare.com", "Cc": "dev@dpdk.org, rasland@nvidia.com, ian.stokes@intel.com, fbl@redhat.com,\n asafp@nvidia.com", "Date": "Wed, 9 Sep 2020 09:48:25 +0300", "Message-Id": "<1599634114-148013-4-git-send-email-jiaweiw@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599634114-148013-1-git-send-email-jiaweiw@nvidia.com>", "References": "<1598540492-406340-1-git-send-email-jiaweiw@nvidia.com>\n <1599634114-148013-1-git-send-email-jiaweiw@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v6 03/12] common/mlx5: query sampler object\n\tcapability via DevX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update function mlx5_devx_cmd_query_hca_attr() to add the NIC Flow\nTable attributes query, then get the log_max_flow_sampler_num from\nflow table properties.\n\nAdd the related structs definition in mlx5_prm.h.\n\nSigned-off-by: Jiawei Wang <jiaweiw@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 27 +++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 51 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 79 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 7c81ae1..fd4e3f2 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -751,6 +751,33 @@ struct mlx5_devx_obj *\n \tif (!attr->eth_net_offloads)\n \t\treturn 0;\n \n+\t/* Query Flow Sampler Capability From FLow Table Properties Layout. */\n+\tmemset(in, 0, sizeof(in));\n+\tmemset(out, 0, sizeof(out));\n+\tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\trc = mlx5_glue->devx_general_cmd(ctx,\n+\t\t\t\t\t in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (rc)\n+\t\tgoto error;\n+\tstatus = MLX5_GET(query_hca_cap_out, out, status);\n+\tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n+\tif (status) {\n+\t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n+\t\t\t\"status %x, syndrome = %x\",\n+\t\t\tstatus, syndrome);\n+\t\tattr->log_max_ft_sampler_num = 0;\n+\t\treturn -1;\n+\t}\n+\thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n+\tattr->log_max_ft_sampler_num =\n+\t\t\tMLX5_GET(flow_table_nic_cap,\n+\t\t\thcattr, flow_table_properties.log_max_ft_sampler_num);\n+\n \t/* Query HCA offloads for Ethernet protocol. */\n \tmemset(in, 0, sizeof(in));\n \tmemset(out, 0, sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 1c84cea..cfa7a7b 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -102,6 +102,7 @@ struct mlx5_hca_attr {\n \tuint32_t scatter_fcs_w_decap_disable:1;\n \tuint32_t regex:1;\n \tuint32_t regexp_num_of_engines;\n+\tuint32_t log_max_ft_sampler_num:8;\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n };\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 0a270a2..b312b3d 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1036,6 +1036,7 @@ enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n };\n \n@@ -1470,12 +1471,62 @@ struct mlx5_ifc_virtio_emulation_cap_bits {\n \tu8 reserved_at_1c0[0x620];\n };\n \n+struct mlx5_ifc_flow_table_prop_layout_bits {\n+\tu8 ft_support[0x1];\n+\tu8 flow_tag[0x1];\n+\tu8 flow_counter[0x1];\n+\tu8 flow_modify_en[0x1];\n+\tu8 modify_root[0x1];\n+\tu8 identified_miss_table[0x1];\n+\tu8 flow_table_modify[0x1];\n+\tu8 reformat[0x1];\n+\tu8 decap[0x1];\n+\tu8 reset_root_to_default[0x1];\n+\tu8 pop_vlan[0x1];\n+\tu8 push_vlan[0x1];\n+\tu8 fpga_vendor_acceleration[0x1];\n+\tu8 pop_vlan_2[0x1];\n+\tu8 push_vlan_2[0x1];\n+\tu8 reformat_and_vlan_action[0x1];\n+\tu8 modify_and_vlan_action[0x1];\n+\tu8 sw_owner[0x1];\n+\tu8 reformat_l3_tunnel_to_l2[0x1];\n+\tu8 reformat_l2_to_l3_tunnel[0x1];\n+\tu8 reformat_and_modify_action[0x1];\n+\tu8 reserved_at_15[0x9];\n+\tu8 sw_owner_v2[0x1];\n+\tu8 reserved_at_1f[0x1];\n+\tu8 reserved_at_20[0x2];\n+\tu8 log_max_ft_size[0x6];\n+\tu8 log_max_modify_header_context[0x8];\n+\tu8 max_modify_header_actions[0x8];\n+\tu8 max_ft_level[0x8];\n+\tu8 reserved_at_40[0x8];\n+\tu8 log_max_ft_sampler_num[8];\n+\tu8 metadata_reg_b_width[0x8];\n+\tu8 metadata_reg_a_width[0x8];\n+\tu8 reserved_at_60[0x18];\n+\tu8 log_max_ft_num[0x8];\n+\tu8 reserved_at_80[0x10];\n+\tu8 log_max_flow_counter[0x8];\n+\tu8 log_max_destination[0x8];\n+\tu8 reserved_at_a0[0x18];\n+\tu8 log_max_flow[0x8];\n+\tu8 reserved_at_c0[0x140];\n+};\n+\n+struct mlx5_ifc_flow_table_nic_cap_bits {\n+\tu8\t reserved_at_0[0x200];\n+\tstruct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;\n+};\n+\n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n \tstruct mlx5_ifc_per_protocol_networking_offload_caps_bits\n \t per_protocol_networking_offload_caps;\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n \tstruct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;\n+\tstruct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;\n \tu8 reserved_at_0[0x8000];\n };\n \n", "prefixes": [ "v6", "03/12" ] }