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GET /api/patches/76974/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 76974,
    "url": "http://patches.dpdk.org/api/patches/76974/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-42-cristian.dumitrescu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200908201830.74206-42-cristian.dumitrescu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-42-cristian.dumitrescu@intel.com",
    "date": "2020-09-08T20:18:30",
    "name": "[v3,41/41] examples/pipeline: add VXLAN encapsulation example",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "68a6cbbccf6419345579a0b6adec2291508cd107",
    "submitter": {
        "id": 19,
        "url": "http://patches.dpdk.org/api/people/19/?format=api",
        "name": "Cristian Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-42-cristian.dumitrescu@intel.com/mbox/",
    "series": [
        {
            "id": 12034,
            "url": "http://patches.dpdk.org/api/series/12034/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034",
            "date": "2020-09-08T20:17:52",
            "name": "Pipeline alignment with the P4 language",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/12034/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/76974/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/76974/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 51767A04B1;\n\tTue,  8 Sep 2020 22:25:37 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5E16C1C2F3;\n\tTue,  8 Sep 2020 22:19:52 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id B5B6F1C19F\n for <dev@dpdk.org>; Tue,  8 Sep 2020 22:19:14 +0200 (CEST)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:19:14 -0700",
            "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:19:13 -0700"
        ],
        "IronPort-SDR": [
            "\n p8W+kH++HheticJ/Zbx4h7REYBlR4NDwXT6g/ZajXL2Yx5xmKKsHvDkAgpoESFDWY40yMigRu3\n RvRaQIhV17wA==",
            "\n 4pOhgAeHSit6zPtbqo7cMVFAXdSYoP0qOdVgMBCMAsPtpjXThuWUCi7Lh/0OXuN0NPO8mTB8+1\n qZXRZZMUDIuQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9738\"; a=\"145939471\"",
            "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939471\"",
            "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493580\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue,  8 Sep 2020 21:18:30 +0100",
        "Message-Id": "<20200908201830.74206-42-cristian.dumitrescu@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>",
        "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 41/41] examples/pipeline: add VXLAN\n\tencapsulation example",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add VXLAN encapsulation example to the SWX pipeline application. The\nVXLAN tunnels can be generated with the vxlan_table.py script. Example\ncommand line: ./build/pipeline -l0-1 -- -s ./examples/vxlan.cli\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n examples/pipeline/examples/vxlan.cli       |  27 ++++\n examples/pipeline/examples/vxlan.spec      | 173 +++++++++++++++++++++\n examples/pipeline/examples/vxlan_pcap.cli  |  22 +++\n examples/pipeline/examples/vxlan_table.py  |  71 +++++++++\n examples/pipeline/examples/vxlan_table.txt |  16 ++\n 5 files changed, 309 insertions(+)\n create mode 100644 examples/pipeline/examples/vxlan.cli\n create mode 100644 examples/pipeline/examples/vxlan.spec\n create mode 100644 examples/pipeline/examples/vxlan_pcap.cli\n create mode 100644 examples/pipeline/examples/vxlan_table.py\n create mode 100644 examples/pipeline/examples/vxlan_table.txt",
    "diff": "diff --git a/examples/pipeline/examples/vxlan.cli b/examples/pipeline/examples/vxlan.cli\nnew file mode 100644\nindex 000000000..f1efd177e\n--- /dev/null\n+++ b/examples/pipeline/examples/vxlan.cli\n@@ -0,0 +1,27 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2020 Intel Corporation\n+\n+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0\n+\n+link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on\n+link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on\n+link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on\n+link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on\n+\n+pipeline PIPELINE0 create 0\n+\n+pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32\n+pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32\n+pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32\n+pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32\n+\n+pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32\n+pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32\n+pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32\n+pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32\n+pipeline PIPELINE0 port out 4 sink none\n+\n+pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec\n+pipeline PIPELINE0 table vxlan_table update ./examples/pipeline/examples/vxlan_table.txt none none\n+\n+thread 1 pipeline PIPELINE0 enable\ndiff --git a/examples/pipeline/examples/vxlan.spec b/examples/pipeline/examples/vxlan.spec\nnew file mode 100644\nindex 000000000..47106471f\n--- /dev/null\n+++ b/examples/pipeline/examples/vxlan.spec\n@@ -0,0 +1,173 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2020 Intel Corporation\n+\n+//\n+// Headers\n+//\n+struct ethernet_h {\n+\tbit<48> dst_addr\n+\tbit<48> src_addr\n+\tbit<16> ethertype\n+}\n+\n+struct ipv4_h {\n+\tbit<8> ver_ihl\n+\tbit<8> diffserv\n+\tbit<16> total_len\n+\tbit<16> identification\n+\tbit<16> flags_offset\n+\tbit<8> ttl\n+\tbit<8> protocol\n+\tbit<16> hdr_checksum\n+\tbit<32> src_addr\n+\tbit<32> dst_addr\n+}\n+\n+struct udp_h {\n+\tbit<16> src_port\n+\tbit<16> dst_port\n+\tbit<16> length\n+\tbit<16> checksum\n+}\n+\n+struct vxlan_h {\n+\tbit<8> flags\n+\tbit<24> reserved\n+\tbit<24> vni\n+\tbit<8> reserved2\n+}\n+\n+header ethernet instanceof ethernet_h\n+header ipv4 instanceof ipv4_h\n+header outer_ethernet instanceof ethernet_h\n+header outer_ipv4 instanceof ipv4_h\n+header outer_udp instanceof udp_h\n+header outer_vxlan instanceof vxlan_h\n+\n+//\n+// Meta-data\n+//\n+struct metadata_t {\n+\tbit<32> port_in\n+\tbit<32> port_out\n+}\n+\n+metadata instanceof metadata_t\n+\n+//\n+// Actions\n+//\n+struct vxlan_encap_args_t {\n+\tbit<48> ethernet_dst_addr\n+\tbit<48> ethernet_src_addr\n+\tbit<16> ethernet_ether_type\n+\tbit<8> ipv4_ver_ihl\n+\tbit<8> ipv4_diffserv\n+\tbit<16> ipv4_total_len\n+\tbit<16> ipv4_identification\n+\tbit<16> ipv4_flags_offset\n+\tbit<8> ipv4_ttl\n+\tbit<8> ipv4_protocol\n+\tbit<16> ipv4_hdr_checksum\n+\tbit<32> ipv4_src_addr\n+\tbit<32> ipv4_dst_addr\n+\tbit<16> udp_src_port\n+\tbit<16> udp_dst_port\n+\tbit<16> udp_length\n+\tbit<16> udp_checksum\n+\tbit<8> vxlan_flags\n+\tbit<24> vxlan_reserved\n+\tbit<24> vxlan_vni\n+\tbit<8> vxlan_reserved2\n+\tbit<32> port_out\n+}\n+\n+// Input frame:\n+//    Ethernet (14) | IPv4 (total_len)\n+//\n+// Output frame:\n+//    Ethernet (14) | IPv4 (20) | UDP (8) | VXLAN (8) | Input frame | Ethernet FCS (4)\n+//\n+// Note: The input frame has its FCS removed before encapsulation in the output\n+// frame.\n+//\n+// Assumption: When read from the table, the outer IPv4 and UDP headers contain\n+// the following fields:\n+//    - t.ipv4_total_len: Set to 50, which covers the length of:\n+//         - The outer IPv4 header (20 bytes);\n+//         - The outer UDP header (8 bytes);\n+//         - The outer VXLAN header (8 bytes);\n+//         - The inner Ethernet header (14 bytes);\n+//    - t.ipv4_hdr_checksum: Includes the above total length.\n+//    - t.udp_length: Set to 30, which covers the length of:\n+//         - The outer UDP header (8 bytes);\n+//         - The outer VXLAN header (8 bytes);\n+//         - The inner Ethernet header (14 bytes);\n+//    - t.udp_checksum: Set to 0.\n+//\n+// Once the total length of the inner IPv4 packet (h.ipv4.total_len) is known,\n+// the outer IPv4 and UDP headers are updated as follows:\n+//    - h.outer_ipv4.total_len = t.ipv4_total_len + h.ipv4.total_len\n+//    - h.outer_ipv4.hdr_checksum = t.ipv4_hdr_checksum + h.ipv4.total_len\n+//    - h.outer_udp.length = t.udp_length + h.ipv4.total_len\n+//    - h.outer_udp.checksum: No change.\n+//\n+\n+action vxlan_encap args instanceof vxlan_encap_args_t {\n+\t//Copy from table entry to haders and metadata.\n+\tdma h.outer_ethernet t.ethernet_dst_addr\n+\tdma h.outer_ipv4 t.ipv4_ver_ihl\n+\tdma h.outer_udp t.udp_src_port\n+\tdma h.outer_vxlan t.vxlan_flags\n+\tmov m.port_out t.port_out\n+\n+\t//Update h.outer_ipv4.total_len field.\n+\tadd h.outer_ipv4.total_len h.ipv4.total_len\n+\n+\t//Update h.outer_ipv4.hdr_checksum field.\n+\tckadd h.outer_ipv4.hdr_checksum h.ipv4.total_len\n+\n+\t//Update h.outer_udp.length field.\n+\tadd h.outer_udp.length h.ipv4.total_len\n+\n+\treturn\n+}\n+\n+action drop args none {\n+\tmov m.port_out 4\n+\ttx m.port_out\n+}\n+\n+//\n+// Tables.\n+//\n+table vxlan_table {\n+\tkey {\n+\t\th.ethernet.dst_addr exact\n+\t}\n+\n+\tactions {\n+\t\tvxlan_encap\n+\t\tdrop\n+\t}\n+\n+\tdefault_action drop args none\n+\tsize 1048576\n+}\n+\n+//\n+// Pipeline.\n+//\n+apply {\n+\trx m.port_in\n+\textract h.ethernet\n+\textract h.ipv4\n+\ttable vxlan_table\n+\temit h.outer_ethernet\n+\temit h.outer_ipv4\n+\temit h.outer_udp\n+\temit h.outer_vxlan\n+\temit h.ethernet\n+\temit h.ipv4\n+\ttx m.port_out\n+}\ndiff --git a/examples/pipeline/examples/vxlan_pcap.cli b/examples/pipeline/examples/vxlan_pcap.cli\nnew file mode 100644\nindex 000000000..c6975343e\n--- /dev/null\n+++ b/examples/pipeline/examples/vxlan_pcap.cli\n@@ -0,0 +1,22 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2020 Intel Corporation\n+\n+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0\n+\n+pipeline PIPELINE0 create 0\n+\n+pipeline PIPELINE0 port in 0 source MEMPOOL0 ./examples/packet.pcap\n+pipeline PIPELINE0 port in 1 source MEMPOOL0 ./examples/packet.pcap\n+pipeline PIPELINE0 port in 2 source MEMPOOL0 ./examples/packet.pcap\n+pipeline PIPELINE0 port in 3 source MEMPOOL0 ./examples/packet.pcap\n+\n+pipeline PIPELINE0 port out 0 sink none\n+pipeline PIPELINE0 port out 1 sink none\n+pipeline PIPELINE0 port out 2 sink none\n+pipeline PIPELINE0 port out 3 sink none\n+pipeline PIPELINE0 port out 4 sink none\n+\n+pipeline PIPELINE0 build ./examples/vxlan.spec\n+pipeline PIPELINE0 table vxlan_table update ./examples/vxlan_table.txt none none\n+\n+thread 1 pipeline PIPELINE0 enable\ndiff --git a/examples/pipeline/examples/vxlan_table.py b/examples/pipeline/examples/vxlan_table.py\nnew file mode 100644\nindex 000000000..179d31b53\n--- /dev/null\n+++ b/examples/pipeline/examples/vxlan_table.py\n@@ -0,0 +1,71 @@\n+#!/usr/bin/env python2\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Intel Corporation\n+#\n+\n+from __future__ import print_function\n+import argparse\n+import re\n+import os\n+\n+DESCRIPTION = 'Table Generator'\n+\n+KEY = '0xaabbccdd{0:04x}'\n+ACTION = 'vxlan_encap'\n+ETHERNET_HEADER = 'ethernet_dst_addr N(0xa0a1a2a3{0:04x}) ' \\\n+\t'ethernet_src_addr N(0xb0b1b2b3{0:04x}) ' \\\n+\t'ethernet_ether_type N(0x0800)'\n+IPV4_HEADER = 'ipv4_ver_ihl N(0x45) ' \\\n+\t'ipv4_diffserv N(0) ' \\\n+\t'ipv4_total_len N(50) ' \\\n+\t'ipv4_identification N(0) ' \\\n+\t'ipv4_flags_offset N(0) ' \\\n+\t'ipv4_ttl N(64) ' \\\n+\t'ipv4_protocol N(17) ' \\\n+\t'ipv4_hdr_checksum N(0x{1:04x}) ' \\\n+\t'ipv4_src_addr N(0xc0c1{0:04x}) ' \\\n+\t'ipv4_dst_addr N(0xd0d1{0:04x})'\n+UDP_HEADER = 'udp_src_port N(0xe0{0:02x}) ' \\\n+\t'udp_dst_port N(4789) ' \\\n+\t'udp_length N(30) ' \\\n+\t'udp_checksum N(0)'\n+VXLAN_HEADER = 'vxlan_flags N(0) ' \\\n+\t'vxlan_reserved N(0) ' \\\n+\t'vxlan_vni N({0:d}) ' \\\n+\t'vxlan_reserved2 N(0)'\n+PORT_OUT = 'port_out H({0:d})'\n+\n+def ipv4_header_checksum(i):\n+\tcksum = (0x4500 + 0x0032) + (0x0000 + 0x0000) + (0x4011 + 0x0000) + (0xc0c1 + i) + (0xd0d1 + i)\n+\tcksum = (cksum & 0xFFFF) + (cksum >> 16)\n+\tcksum = (cksum & 0xFFFF) + (cksum >> 16)\n+\tcksum = ~cksum & 0xFFFF\n+\treturn cksum\n+\n+def table_generate(n, p):\n+\tfor i in range(0, n):\n+\t\tprint(\"match %s action %s %s %s %s %s %s\" % (KEY.format(i),\n+\t\t\tACTION,\n+\t\t\tETHERNET_HEADER.format(i),\n+\t\t\tIPV4_HEADER.format(i, ipv4_header_checksum(i)),\n+\t\t\tUDP_HEADER.format(i % 256),\n+\t\t\tVXLAN_HEADER.format(i),\n+\t\t\tPORT_OUT.format(i % p)))\n+\n+if __name__ == '__main__':\n+\tparser = argparse.ArgumentParser(description=DESCRIPTION)\n+\n+\tparser.add_argument(\n+\t\t'-n',\n+\t\thelp='number of table entries (default: 65536)',\n+\t\trequired=False,\n+\t\tdefault=65536)\n+\n+\tparser.add_argument(\n+\t\t'-p',\n+\t\thelp='number of network ports (default: 4)',\n+\t\trequired=False,\n+\t\tdefault=4)\n+\n+\targs = parser.parse_args()\n+\ttable_generate(int(args.n), int(args.p))\ndiff --git a/examples/pipeline/examples/vxlan_table.txt b/examples/pipeline/examples/vxlan_table.txt\nnew file mode 100644\nindex 000000000..acac80a38\n--- /dev/null\n+++ b/examples/pipeline/examples/vxlan_table.txt\n@@ -0,0 +1,16 @@\n+match 0xaabbccdd0000 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30000) ethernet_src_addr N(0xb0b1b2b30000) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe928) ipv4_src_addr N(0xc0c10000) ipv4_dst_addr N(0xd0d10000) udp_src_port N(0xe000) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(0) vxlan_reserved2 N(0) port_out H(0)\n+match 0xaabbccdd0001 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30001) ethernet_src_addr N(0xb0b1b2b30001) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe926) ipv4_src_addr N(0xc0c10001) ipv4_dst_addr N(0xd0d10001) udp_src_port N(0xe001) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(1) vxlan_reserved2 N(0) port_out H(1)\n+match 0xaabbccdd0002 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30002) ethernet_src_addr N(0xb0b1b2b30002) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe924) ipv4_src_addr N(0xc0c10002) ipv4_dst_addr N(0xd0d10002) udp_src_port N(0xe002) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(2) vxlan_reserved2 N(0) port_out H(2)\n+match 0xaabbccdd0003 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30003) ethernet_src_addr N(0xb0b1b2b30003) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe922) ipv4_src_addr N(0xc0c10003) ipv4_dst_addr N(0xd0d10003) udp_src_port N(0xe003) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(3) vxlan_reserved2 N(0) port_out H(3)\n+match 0xaabbccdd0004 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30004) ethernet_src_addr N(0xb0b1b2b30004) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe920) ipv4_src_addr N(0xc0c10004) ipv4_dst_addr N(0xd0d10004) udp_src_port N(0xe004) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(4) vxlan_reserved2 N(0) port_out H(0)\n+match 0xaabbccdd0005 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30005) ethernet_src_addr N(0xb0b1b2b30005) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91e) ipv4_src_addr N(0xc0c10005) ipv4_dst_addr N(0xd0d10005) udp_src_port N(0xe005) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(5) vxlan_reserved2 N(0) port_out H(1)\n+match 0xaabbccdd0006 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30006) ethernet_src_addr N(0xb0b1b2b30006) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91c) ipv4_src_addr N(0xc0c10006) ipv4_dst_addr N(0xd0d10006) udp_src_port N(0xe006) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(6) vxlan_reserved2 N(0) port_out H(2)\n+match 0xaabbccdd0007 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30007) ethernet_src_addr N(0xb0b1b2b30007) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91a) ipv4_src_addr N(0xc0c10007) ipv4_dst_addr N(0xd0d10007) udp_src_port N(0xe007) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(7) vxlan_reserved2 N(0) port_out H(3)\n+match 0xaabbccdd0008 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30008) ethernet_src_addr N(0xb0b1b2b30008) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe918) ipv4_src_addr N(0xc0c10008) ipv4_dst_addr N(0xd0d10008) udp_src_port N(0xe008) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(8) vxlan_reserved2 N(0) port_out H(0)\n+match 0xaabbccdd0009 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30009) ethernet_src_addr N(0xb0b1b2b30009) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe916) ipv4_src_addr N(0xc0c10009) ipv4_dst_addr N(0xd0d10009) udp_src_port N(0xe009) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(9) vxlan_reserved2 N(0) port_out H(1)\n+match 0xaabbccdd000a action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000a) ethernet_src_addr N(0xb0b1b2b3000a) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe914) ipv4_src_addr N(0xc0c1000a) ipv4_dst_addr N(0xd0d1000a) udp_src_port N(0xe00a) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(10) vxlan_reserved2 N(0) port_out H(2)\n+match 0xaabbccdd000b action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000b) ethernet_src_addr N(0xb0b1b2b3000b) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe912) ipv4_src_addr N(0xc0c1000b) ipv4_dst_addr N(0xd0d1000b) udp_src_port N(0xe00b) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(11) vxlan_reserved2 N(0) port_out H(3)\n+match 0xaabbccdd000c action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000c) ethernet_src_addr N(0xb0b1b2b3000c) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe910) ipv4_src_addr N(0xc0c1000c) ipv4_dst_addr N(0xd0d1000c) udp_src_port N(0xe00c) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(12) vxlan_reserved2 N(0) port_out H(0)\n+match 0xaabbccdd000d action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000d) ethernet_src_addr N(0xb0b1b2b3000d) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90e) ipv4_src_addr N(0xc0c1000d) ipv4_dst_addr N(0xd0d1000d) udp_src_port N(0xe00d) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(13) vxlan_reserved2 N(0) port_out H(1)\n+match 0xaabbccdd000e action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000e) ethernet_src_addr N(0xb0b1b2b3000e) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90c) ipv4_src_addr N(0xc0c1000e) ipv4_dst_addr N(0xd0d1000e) udp_src_port N(0xe00e) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(14) vxlan_reserved2 N(0) port_out H(2)\n+match 0xaabbccdd000f action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000f) ethernet_src_addr N(0xb0b1b2b3000f) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90a) ipv4_src_addr N(0xc0c1000f) ipv4_dst_addr N(0xd0d1000f) udp_src_port N(0xe00f) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(15) vxlan_reserved2 N(0) port_out H(3)\n",
    "prefixes": [
        "v3",
        "41/41"
    ]
}