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GET /api/patches/76952/?format=api
{ "id": 76952, "url": "http://patches.dpdk.org/api/patches/76952/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-22-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-22-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-22-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:18:10", "name": "[v3,21/41] pipeline: introduce SWX shl instruction", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7da794d90ce94bdf3d165e43ca5cd24257252110", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-22-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76952/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76952/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 79162A04B1;\n\tTue, 8 Sep 2020 22:22:09 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 307451C1D2;\n\tTue, 8 Sep 2020 22:19:27 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id BEC341C113\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:19:01 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:52 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:51 -0700" ], "IronPort-SDR": [ "\n RAnY8YPrdKeuZmBHOCIJJkVTtSJfgHOXK0taeeHg4ev57DImuuD6KpvtR/vR2qwcqumUiYRNJn\n ut/l2YuZfAdA==", "\n LToUaMmJ1UJj3xNk2i9FHUcYO+hk7OkkDZv0Uesure0ydQXHJCJcuWlSEA81HUd0lMYSIimkus\n z6/wXqpwNzZQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939413\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939413\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493462\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:18:10 +0100", "Message-Id": "<20200908201830.74206-22-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 21/41] pipeline: introduce SWX shl instruction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The shl (i.e. shift left) instruction source can be header field (H),\nmeta-data field (M), extern object (E) or function (F) mailbox field,\ntable entry action data field (T) or immediate value (I). The\ndestination is HMEF.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_swx_pipeline.c | 168 +++++++++++++++++++++++++\n 1 file changed, 168 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 6024c800c..419b676bd 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -327,6 +327,17 @@ enum instruction_type {\n \tINSTR_ALU_XOR, /* dst = MEF, src = MEFT */\n \tINSTR_ALU_XOR_S, /* (dst, src) = (MEF, H) or (dst, src) = (H, MEFT) */\n \tINSTR_ALU_XOR_I, /* dst = HMEF, src = I */\n+\n+\t/* shl dst src\n+\t * dst <<= src\n+\t * dst = HMEF, src = HMEFTI\n+\t */\n+\tINSTR_ALU_SHL, /* dst = MEF, src = MEF */\n+\tINSTR_ALU_SHL_MH, /* dst = MEF, src = H */\n+\tINSTR_ALU_SHL_HM, /* dst = H, src = MEF */\n+\tINSTR_ALU_SHL_HH, /* dst = H, src = H */\n+\tINSTR_ALU_SHL_MI, /* dst = MEF, src = I */\n+\tINSTR_ALU_SHL_HI, /* dst = H, src = I */\n };\n \n struct instr_operand {\n@@ -3094,6 +3105,58 @@ instr_alu_cksub_translate(struct rte_swx_pipeline *p,\n \treturn 0;\n }\n \n+static int\n+instr_alu_shl_translate(struct rte_swx_pipeline *p,\n+\t\t\tstruct action *action,\n+\t\t\tchar **tokens,\n+\t\t\tint n_tokens,\n+\t\t\tstruct instruction *instr,\n+\t\t\tstruct instruction_data *data __rte_unused)\n+{\n+\tchar *dst = tokens[1], *src = tokens[2];\n+\tstruct field *fdst, *fsrc;\n+\tuint32_t dst_struct_id, src_struct_id, src_val;\n+\n+\tCHECK(n_tokens == 3, EINVAL);\n+\n+\tfdst = struct_field_parse(p, NULL, dst, &dst_struct_id);\n+\tCHECK(fdst, EINVAL);\n+\n+\t/* SHL, SHL_HM, SHL_MH, SHL_HH. */\n+\tfsrc = struct_field_parse(p, action, src, &src_struct_id);\n+\tif (fsrc) {\n+\t\tinstr->type = INSTR_ALU_SHL;\n+\t\tif (dst[0] == 'h' && src[0] == 'm')\n+\t\t\tinstr->type = INSTR_ALU_SHL_HM;\n+\t\tif (dst[0] == 'm' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_SHL_MH;\n+\t\tif (dst[0] == 'h' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_SHL_HH;\n+\n+\t\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\t\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\t\tinstr->alu.dst.offset = fdst->offset / 8;\n+\t\tinstr->alu.src.struct_id = (uint8_t)src_struct_id;\n+\t\tinstr->alu.src.n_bits = fsrc->n_bits;\n+\t\tinstr->alu.src.offset = fsrc->offset / 8;\n+\t\treturn 0;\n+\t}\n+\n+\t/* SHL_MI, SHL_HI. */\n+\tsrc_val = strtoul(src, &src, 0);\n+\tCHECK(!src[0], EINVAL);\n+\n+\tinstr->type = INSTR_ALU_SHL_MI;\n+\tif (dst[0] == 'h')\n+\t\tinstr->type = INSTR_ALU_SHL_HI;\n+\n+\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\tinstr->alu.dst.offset = fdst->offset / 8;\n+\tinstr->alu.src_val = (uint32_t)src_val;\n+\treturn 0;\n+}\n+\n static int\n instr_alu_and_translate(struct rte_swx_pipeline *p,\n \t\t\tstruct action *action,\n@@ -3421,6 +3484,96 @@ instr_alu_sub_hi_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+static inline void\n+instr_alu_shl_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shl_mh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl (mh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MH(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shl_hm_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl (hm)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HM(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shl_hh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl (hh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HH(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shl_mi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl (mi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MI(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shl_hi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shl (hi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HI(t, ip, <<);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n static inline void\n instr_alu_and_exec(struct rte_swx_pipeline *p)\n {\n@@ -3947,6 +4100,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t instr,\n \t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"shl\"))\n+\t\treturn instr_alu_shl_translate(p,\n+\t\t\t\t\t action,\n+\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t instr,\n+\t\t\t\t\t data);\n+\n \tCHECK(0, EINVAL);\n }\n \n@@ -4135,6 +4296,13 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_ALU_XOR] = instr_alu_xor_exec,\n \t[INSTR_ALU_XOR_S] = instr_alu_xor_s_exec,\n \t[INSTR_ALU_XOR_I] = instr_alu_xor_i_exec,\n+\n+\t[INSTR_ALU_SHL] = instr_alu_shl_exec,\n+\t[INSTR_ALU_SHL_MH] = instr_alu_shl_mh_exec,\n+\t[INSTR_ALU_SHL_HM] = instr_alu_shl_hm_exec,\n+\t[INSTR_ALU_SHL_HH] = instr_alu_shl_hh_exec,\n+\t[INSTR_ALU_SHL_MI] = instr_alu_shl_mi_exec,\n+\t[INSTR_ALU_SHL_HI] = instr_alu_shl_hi_exec,\n };\n \n static inline void\n", "prefixes": [ "v3", "21/41" ] }