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GET /api/patches/76949/?format=api
{ "id": 76949, "url": "http://patches.dpdk.org/api/patches/76949/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-17-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-17-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-17-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:18:05", "name": "[v3,16/41] pipeline: introduce SWX ckadd instruction", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "597ee828dc10d3e8a778aa0a4d55ac2b3383d702", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-17-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76949/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76949/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 48628A04B1;\n\tTue, 8 Sep 2020 22:21:41 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 15A391C1BA;\n\tTue, 8 Sep 2020 22:19:23 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id D66AE1C113\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:19:00 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:48 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:47 -0700" ], "IronPort-SDR": [ "\n hMdWow6nTAUQo/Tw2JsMWau9xSVADHN/KOmDpgdJEic6E+aKWYp6SOtJXvPuW9eRbVA+CE7Aaa\n xV60thLT9vDQ==", "\n 8goXdAVGT3GFplKqT+O2hXVsNynHsxh9lkuO85ThEtOrqLgwLA2LG0wjnJyRepSZclchSc7nh5\n fvyX2maLyaxQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939407\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939407\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493442\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:18:05 +0100", "Message-Id": "<20200908201830.74206-17-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 16/41] pipeline: introduce SWX ckadd\n\tinstruction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The ckadd (i.e. checksum add) instruction is used to either compute,\nverify or update the 1's complement sum commonly used by protocols\nsuch as IPv4, TCP or UDP.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_swx_pipeline.c | 230 +++++++++++++++++++++++++\n 1 file changed, 230 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 245621dc3..96e6c98aa 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -289,6 +289,14 @@ enum instruction_type {\n \tINSTR_ALU_SUB_HH, /* dst = H, src = H */\n \tINSTR_ALU_SUB_MI, /* dst = MEF, src = I */\n \tINSTR_ALU_SUB_HI, /* dst = H, src = I */\n+\n+\t/* ckadd dst src\n+\t * dst = dst '+ src[0:1] '+ src[2:3] + ...\n+\t * dst = H, src = {H, h.header}\n+\t */\n+\tINSTR_ALU_CKADD_FIELD, /* src = H */\n+\tINSTR_ALU_CKADD_STRUCT20, /* src = h.header, with sizeof(header) = 20 */\n+\tINSTR_ALU_CKADD_STRUCT, /* src = h.hdeader, with any sizeof(header) */\n };\n \n struct instr_operand {\n@@ -2979,6 +2987,53 @@ instr_alu_sub_translate(struct rte_swx_pipeline *p,\n \treturn 0;\n }\n \n+static int\n+instr_alu_ckadd_translate(struct rte_swx_pipeline *p,\n+\t\t\t struct action *action __rte_unused,\n+\t\t\t char **tokens,\n+\t\t\t int n_tokens,\n+\t\t\t struct instruction *instr,\n+\t\t\t struct instruction_data *data __rte_unused)\n+{\n+\tchar *dst = tokens[1], *src = tokens[2];\n+\tstruct header *hdst, *hsrc;\n+\tstruct field *fdst, *fsrc;\n+\n+\tCHECK(n_tokens == 3, EINVAL);\n+\n+\tfdst = header_field_parse(p, dst, &hdst);\n+\tCHECK(fdst && (fdst->n_bits == 16), EINVAL);\n+\n+\t/* CKADD_FIELD. */\n+\tfsrc = header_field_parse(p, src, &hsrc);\n+\tif (fsrc) {\n+\t\tinstr->type = INSTR_ALU_CKADD_FIELD;\n+\t\tinstr->alu.dst.struct_id = (uint8_t)hdst->struct_id;\n+\t\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\t\tinstr->alu.dst.offset = fdst->offset / 8;\n+\t\tinstr->alu.src.struct_id = (uint8_t)hsrc->struct_id;\n+\t\tinstr->alu.src.n_bits = fsrc->n_bits;\n+\t\tinstr->alu.src.offset = fsrc->offset / 8;\n+\t\treturn 0;\n+\t}\n+\n+\t/* CKADD_STRUCT, CKADD_STRUCT20. */\n+\thsrc = header_parse(p, src);\n+\tCHECK(hsrc, EINVAL);\n+\n+\tinstr->type = INSTR_ALU_CKADD_STRUCT;\n+\tif ((hsrc->st->n_bits / 8) == 20)\n+\t\tinstr->type = INSTR_ALU_CKADD_STRUCT20;\n+\n+\tinstr->alu.dst.struct_id = (uint8_t)hdst->struct_id;\n+\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\tinstr->alu.dst.offset = fdst->offset / 8;\n+\tinstr->alu.src.struct_id = (uint8_t)hsrc->struct_id;\n+\tinstr->alu.src.n_bits = hsrc->st->n_bits;\n+\tinstr->alu.src.offset = 0; /* Unused. */\n+\treturn 0;\n+}\n+\n static inline void\n instr_alu_add_exec(struct rte_swx_pipeline *p)\n {\n@@ -3159,6 +3214,169 @@ instr_alu_sub_hi_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+static inline void\n+instr_alu_ckadd_field_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr, dst;\n+\tuint64_t *src64_ptr, src64, src64_mask, src;\n+\tuint64_t r;\n+\n+\tTRACE(\"[Thread %2u] ckadd (field)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\tdst = *dst16_ptr;\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc64_ptr = (uint64_t *)&src_struct[ip->alu.src.offset];\n+\tsrc64 = *src64_ptr;\n+\tsrc64_mask = UINT64_MAX >> (64 - ip->alu.src.n_bits);\n+\tsrc = src64 & src64_mask;\n+\n+\tr = dst;\n+\tr = ~r & 0xFFFF;\n+\n+\t/* The first input (r) is a 16-bit number. The second and the third\n+\t * inputs are 32-bit numbers. In the worst case scenario, the sum of the\n+\t * three numbers (output r) is a 34-bit number.\n+\t */\n+\tr += (src >> 32) + (src & 0xFFFFFFFF);\n+\n+\t/* The first input is a 16-bit number. The second input is an 18-bit\n+\t * number. In the worst case scenario, the sum of the two numbers is a\n+\t * 19-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 3-bit number (0 .. 7). Their sum is a 17-bit number (0 .. 0x10006).\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x10006), the output r is (0 .. 7). So no carry bit can be generated,\n+\t * therefore the output r is always a 16-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\tr = ~r & 0xFFFF;\n+\tr = r ? r : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r;\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_ckadd_struct20_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr;\n+\tuint32_t *src32_ptr;\n+\tuint64_t r0, r1;\n+\n+\tTRACE(\"[Thread %2u] ckadd (struct of 20 bytes)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc32_ptr = (uint32_t *)&src_struct[0];\n+\n+\tr0 = src32_ptr[0]; /* r0 is a 32-bit number. */\n+\tr1 = src32_ptr[1]; /* r1 is a 32-bit number. */\n+\tr0 += src32_ptr[2]; /* The output r0 is a 33-bit number. */\n+\tr1 += src32_ptr[3]; /* The output r1 is a 33-bit number. */\n+\tr0 += r1 + src32_ptr[4]; /* The output r0 is a 35-bit number. */\n+\n+\t/* The first input is a 16-bit number. The second input is a 19-bit\n+\t * number. Their sum is a 20-bit number.\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 4-bit number (0 .. 15). The sum is a 17-bit number (0 .. 0x1000E).\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x1000E), the output r is (0 .. 15). So no carry bit can be\n+\t * generated, therefore the output r is always a 16-bit number.\n+\t */\n+\tr0 = (r0 & 0xFFFF) + (r0 >> 16);\n+\n+\tr0 = ~r0 & 0xFFFF;\n+\tr0 = r0 ? r0 : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r0;\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_ckadd_struct_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint8_t *dst_struct, *src_struct;\n+\tuint16_t *dst16_ptr;\n+\tuint32_t *src32_ptr;\n+\tuint64_t r = 0;\n+\tuint32_t i;\n+\n+\tTRACE(\"[Thread %2u] ckadd (struct)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tdst_struct = t->structs[ip->alu.dst.struct_id];\n+\tdst16_ptr = (uint16_t *)&dst_struct[ip->alu.dst.offset];\n+\n+\tsrc_struct = t->structs[ip->alu.src.struct_id];\n+\tsrc32_ptr = (uint32_t *)&src_struct[0];\n+\n+\t/* The max number of 32-bit words in a 256-byte header is 8 = 2^3.\n+\t * Therefore, in the worst case scenario, a 35-bit number is added to a\n+\t * 16-bit number (the input r), so the output r is 36-bit number.\n+\t */\n+\tfor (i = 0; i < ip->alu.src.n_bits / 32; i++, src32_ptr++)\n+\t\tr += *src32_ptr;\n+\n+\t/* The first input is a 16-bit number. The second input is a 20-bit\n+\t * number. Their sum is a 21-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* The first input is a 16-bit number (0 .. 0xFFFF). The second input is\n+\t * a 5-bit number (0 .. 31). The sum is a 17-bit number (0 .. 0x1000E).\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\t/* When the input r is (0 .. 0xFFFF), the output r is equal to the input\n+\t * r, so the output is (0 .. 0xFFFF). When the input r is (0x10000 ..\n+\t * 0x1001E), the output r is (0 .. 31). So no carry bit can be\n+\t * generated, therefore the output r is always a 16-bit number.\n+\t */\n+\tr = (r & 0xFFFF) + (r >> 16);\n+\n+\tr = ~r & 0xFFFF;\n+\tr = r ? r : 0xFFFF;\n+\n+\t*dst16_ptr = (uint16_t)r;\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n #define RTE_SWX_INSTRUCTION_TOKENS_MAX 16\n \n static int\n@@ -3276,6 +3494,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t instr,\n \t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"ckadd\"))\n+\t\treturn instr_alu_ckadd_translate(p,\n+\t\t\t\t\t\t action,\n+\t\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t\t instr,\n+\t\t\t\t\t\t data);\n+\n \tCHECK(0, EINVAL);\n }\n \n@@ -3447,6 +3673,10 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_ALU_SUB_HH] = instr_alu_sub_hh_exec,\n \t[INSTR_ALU_SUB_MI] = instr_alu_sub_mi_exec,\n \t[INSTR_ALU_SUB_HI] = instr_alu_sub_hi_exec,\n+\n+\t[INSTR_ALU_CKADD_FIELD] = instr_alu_ckadd_field_exec,\n+\t[INSTR_ALU_CKADD_STRUCT] = instr_alu_ckadd_struct_exec,\n+\t[INSTR_ALU_CKADD_STRUCT20] = instr_alu_ckadd_struct20_exec,\n };\n \n static inline void\n", "prefixes": [ "v3", "16/41" ] }