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GET /api/patches/76944/?format=api
{ "id": 76944, "url": "http://patches.dpdk.org/api/patches/76944/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-11-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-11-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-11-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:17:59", "name": "[v3,10/41] pipeline: add SWX tx and emit instructions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2cbcd99c4d560730433ed32e7090210f1fc5d2a3", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-11-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76944/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 06304A04B1;\n\tTue, 8 Sep 2020 22:20:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A6B1C1C19E;\n\tTue, 8 Sep 2020 22:19:14 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id C3C4C1C0D7\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:18:58 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:42 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:41 -0700" ], "IronPort-SDR": [ "\n bzsAC4dfm3Gvvde077UVsc+WyyCUoTP9XUwF1jrk/PA/pR1BToT6GLbUVHSl+yGUpA/YSCjB5U\n DZw5X1fckYBg==", "\n FWfCLIOynz4ROZF5za1b9iDQq78ASzIW8emdWoUnGqMjUTVPeLxgXoSpyk6LFOUcalSH0I3brl\n /Oo2yQIFZOiA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939393\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939393\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493404\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:17:59 +0100", "Message-Id": "<20200908201830.74206-11-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 10/41] pipeline: add SWX tx and emit\n\tinstructions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add header emit and packet transmission instructions. Emit adds to the\noutput packet a header that is either generated (e.g. read from table\nentry by action) or extracted from the input packet. TX ends the\npipeline processing; discard is implemented by tx to special port.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_swx_pipeline.c | 328 +++++++++++++++++++++++++\n 1 file changed, 328 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex d7af80e39..19bf2761d 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -213,6 +213,9 @@ enum instruction_type {\n \t/* rx m.port_in */\n \tINSTR_RX,\n \n+\t/* tx m.port_out */\n+\tINSTR_TX,\n+\n \t/* extract h.header */\n \tINSTR_HDR_EXTRACT,\n \tINSTR_HDR_EXTRACT2,\n@@ -222,6 +225,17 @@ enum instruction_type {\n \tINSTR_HDR_EXTRACT6,\n \tINSTR_HDR_EXTRACT7,\n \tINSTR_HDR_EXTRACT8,\n+\n+\t/* emit h.header */\n+\tINSTR_HDR_EMIT,\n+\tINSTR_HDR_EMIT_TX,\n+\tINSTR_HDR_EMIT2_TX,\n+\tINSTR_HDR_EMIT3_TX,\n+\tINSTR_HDR_EMIT4_TX,\n+\tINSTR_HDR_EMIT5_TX,\n+\tINSTR_HDR_EMIT6_TX,\n+\tINSTR_HDR_EMIT7_TX,\n+\tINSTR_HDR_EMIT8_TX,\n };\n \n struct instr_io {\n@@ -1635,6 +1649,114 @@ instr_rx_exec(struct rte_swx_pipeline *p)\n \tthread_yield(p);\n }\n \n+/*\n+ * tx.\n+ */\n+static int\n+instr_tx_translate(struct rte_swx_pipeline *p,\n+\t\t struct action *action __rte_unused,\n+\t\t char **tokens,\n+\t\t int n_tokens,\n+\t\t struct instruction *instr,\n+\t\t struct instruction_data *data __rte_unused)\n+{\n+\tstruct field *f;\n+\n+\tCHECK(n_tokens == 2, EINVAL);\n+\n+\tf = metadata_field_parse(p, tokens[1]);\n+\tCHECK(f, EINVAL);\n+\n+\tinstr->type = INSTR_TX;\n+\tinstr->io.io.offset = f->offset / 8;\n+\tinstr->io.io.n_bits = f->n_bits;\n+\treturn 0;\n+}\n+\n+static inline void\n+emit_handler(struct thread *t)\n+{\n+\tstruct header_out_runtime *h0 = &t->headers_out[0];\n+\tstruct header_out_runtime *h1 = &t->headers_out[1];\n+\tuint32_t offset = 0, i;\n+\n+\t/* No header change or header decapsulation. */\n+\tif ((t->n_headers_out == 1) &&\n+\t (h0->ptr + h0->n_bytes == t->ptr)) {\n+\t\tTRACE(\"Emit handler: no header change or header decap.\\n\");\n+\n+\t\tt->pkt.offset -= h0->n_bytes;\n+\t\tt->pkt.length += h0->n_bytes;\n+\n+\t\treturn;\n+\t}\n+\n+\t/* Header encapsulation (optionally, with prior header decasulation). */\n+\tif ((t->n_headers_out == 2) &&\n+\t (h1->ptr + h1->n_bytes == t->ptr) &&\n+\t (h0->ptr == h0->ptr0)) {\n+\t\tuint32_t offset;\n+\n+\t\tTRACE(\"Emit handler: header encapsulation.\\n\");\n+\n+\t\toffset = h0->n_bytes + h1->n_bytes;\n+\t\tmemcpy(t->ptr - offset, h0->ptr, h0->n_bytes);\n+\t\tt->pkt.offset -= offset;\n+\t\tt->pkt.length += offset;\n+\n+\t\treturn;\n+\t}\n+\n+\t/* Header insertion. */\n+\t/* TBD */\n+\n+\t/* Header extraction. */\n+\t/* TBD */\n+\n+\t/* For any other case. */\n+\tTRACE(\"Emit handler: complex case.\\n\");\n+\n+\tfor (i = 0; i < t->n_headers_out; i++) {\n+\t\tstruct header_out_runtime *h = &t->headers_out[i];\n+\n+\t\tmemcpy(&t->header_out_storage[offset], h->ptr, h->n_bytes);\n+\t\toffset += h->n_bytes;\n+\t}\n+\n+\tif (offset) {\n+\t\tmemcpy(t->ptr - offset, t->header_out_storage, offset);\n+\t\tt->pkt.offset -= offset;\n+\t\tt->pkt.length += offset;\n+\t}\n+}\n+\n+static inline void\n+instr_tx_exec(struct rte_swx_pipeline *p);\n+\n+static inline void\n+instr_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint64_t port_id = METADATA_READ(t, ip->io.io.offset, ip->io.io.n_bits);\n+\tstruct port_out_runtime *port = &p->out[port_id];\n+\tstruct rte_swx_pkt *pkt = &t->pkt;\n+\n+\tTRACE(\"[Thread %2u]: tx 1 pkt to port %u\\n\",\n+\t p->thread_id,\n+\t (uint32_t)port_id);\n+\n+\t/* Headers. */\n+\temit_handler(t);\n+\n+\t/* Packet. */\n+\tport->pkt_tx(port->obj, pkt);\n+\n+\t/* Thread. */\n+\tthread_ip_reset(p, t);\n+\tinstr_rx_exec(p);\n+}\n+\n /*\n * extract.\n */\n@@ -1797,6 +1919,185 @@ instr_hdr_extract8_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+/*\n+ * emit.\n+ */\n+static int\n+instr_hdr_emit_translate(struct rte_swx_pipeline *p,\n+\t\t\t struct action *action __rte_unused,\n+\t\t\t char **tokens,\n+\t\t\t int n_tokens,\n+\t\t\t struct instruction *instr,\n+\t\t\t struct instruction_data *data __rte_unused)\n+{\n+\tstruct header *h;\n+\n+\tCHECK(n_tokens == 2, EINVAL);\n+\n+\th = header_parse(p, tokens[1]);\n+\tCHECK(h, EINVAL);\n+\n+\tinstr->type = INSTR_HDR_EMIT;\n+\tinstr->io.hdr.header_id[0] = h->id;\n+\tinstr->io.hdr.struct_id[0] = h->struct_id;\n+\tinstr->io.hdr.n_bytes[0] = h->st->n_bits / 8;\n+\treturn 0;\n+}\n+\n+static inline void\n+__instr_hdr_emit_exec(struct rte_swx_pipeline *p, uint32_t n_emit);\n+\n+static inline void\n+__instr_hdr_emit_exec(struct rte_swx_pipeline *p, uint32_t n_emit)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint32_t n_headers_out = t->n_headers_out;\n+\tstruct header_out_runtime *ho = &t->headers_out[n_headers_out - 1];\n+\tuint8_t *ho_ptr = NULL;\n+\tuint32_t ho_nbytes = 0, i;\n+\n+\tfor (i = 0; i < n_emit; i++) {\n+\t\tuint32_t header_id = ip->io.hdr.header_id[i];\n+\t\tuint32_t struct_id = ip->io.hdr.struct_id[i];\n+\t\tuint32_t n_bytes = ip->io.hdr.n_bytes[i];\n+\n+\t\tstruct header_runtime *hi = &t->headers[header_id];\n+\t\tuint8_t *hi_ptr = t->structs[struct_id];\n+\n+\t\tTRACE(\"[Thread %2u]: emit header %u\\n\",\n+\t\t p->thread_id,\n+\t\t header_id);\n+\n+\t\t/* Headers. */\n+\t\tif (!i) {\n+\t\t\tif (!t->n_headers_out) {\n+\t\t\t\tho = &t->headers_out[0];\n+\n+\t\t\t\tho->ptr0 = hi->ptr0;\n+\t\t\t\tho->ptr = hi_ptr;\n+\n+\t\t\t\tho_ptr = hi_ptr;\n+\t\t\t\tho_nbytes = n_bytes;\n+\n+\t\t\t\tn_headers_out = 1;\n+\n+\t\t\t\tcontinue;\n+\t\t\t} else {\n+\t\t\t\tho_ptr = ho->ptr;\n+\t\t\t\tho_nbytes = ho->n_bytes;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (ho_ptr + ho_nbytes == hi_ptr) {\n+\t\t\tho_nbytes += n_bytes;\n+\t\t} else {\n+\t\t\tho->n_bytes = ho_nbytes;\n+\n+\t\t\tho++;\n+\t\t\tho->ptr0 = hi->ptr0;\n+\t\t\tho->ptr = hi_ptr;\n+\n+\t\t\tho_ptr = hi_ptr;\n+\t\t\tho_nbytes = n_bytes;\n+\n+\t\t\tn_headers_out++;\n+\t\t}\n+\t}\n+\n+\tho->n_bytes = ho_nbytes;\n+\tt->n_headers_out = n_headers_out;\n+}\n+\n+static inline void\n+instr_hdr_emit_exec(struct rte_swx_pipeline *p)\n+{\n+\t__instr_hdr_emit_exec(p, 1);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_emit_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 2 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 1);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit2_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 3 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 2);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit3_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 4 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 3);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit4_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 5 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 4);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit5_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 6 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 5);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit6_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 7 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 6);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit7_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 8 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 7);\n+\tinstr_tx_exec(p);\n+}\n+\n+static inline void\n+instr_hdr_emit8_tx_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 9 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_emit_exec(p, 8);\n+\tinstr_tx_exec(p);\n+}\n+\n #define RTE_SWX_INSTRUCTION_TOKENS_MAX 16\n \n static int\n@@ -1842,6 +2143,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t instr,\n \t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"tx\"))\n+\t\treturn instr_tx_translate(p,\n+\t\t\t\t\t action,\n+\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t instr,\n+\t\t\t\t\t data);\n+\n \tif (!strcmp(tokens[tpos], \"extract\"))\n \t\treturn instr_hdr_extract_translate(p,\n \t\t\t\t\t\t action,\n@@ -1850,6 +2159,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t\t instr,\n \t\t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"emit\"))\n+\t\treturn instr_hdr_emit_translate(p,\n+\t\t\t\t\t\taction,\n+\t\t\t\t\t\t&tokens[tpos],\n+\t\t\t\t\t\tn_tokens - tpos,\n+\t\t\t\t\t\tinstr,\n+\t\t\t\t\t\tdata);\n+\n \tCHECK(0, EINVAL);\n }\n \n@@ -1971,6 +2288,7 @@ typedef void (*instr_exec_t)(struct rte_swx_pipeline *);\n \n static instr_exec_t instruction_table[] = {\n \t[INSTR_RX] = instr_rx_exec,\n+\t[INSTR_TX] = instr_tx_exec,\n \n \t[INSTR_HDR_EXTRACT] = instr_hdr_extract_exec,\n \t[INSTR_HDR_EXTRACT2] = instr_hdr_extract2_exec,\n@@ -1980,6 +2298,16 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_HDR_EXTRACT6] = instr_hdr_extract6_exec,\n \t[INSTR_HDR_EXTRACT7] = instr_hdr_extract7_exec,\n \t[INSTR_HDR_EXTRACT8] = instr_hdr_extract8_exec,\n+\n+\t[INSTR_HDR_EMIT] = instr_hdr_emit_exec,\n+\t[INSTR_HDR_EMIT_TX] = instr_hdr_emit_tx_exec,\n+\t[INSTR_HDR_EMIT2_TX] = instr_hdr_emit2_tx_exec,\n+\t[INSTR_HDR_EMIT3_TX] = instr_hdr_emit3_tx_exec,\n+\t[INSTR_HDR_EMIT4_TX] = instr_hdr_emit4_tx_exec,\n+\t[INSTR_HDR_EMIT5_TX] = instr_hdr_emit5_tx_exec,\n+\t[INSTR_HDR_EMIT6_TX] = instr_hdr_emit6_tx_exec,\n+\t[INSTR_HDR_EMIT7_TX] = instr_hdr_emit7_tx_exec,\n+\t[INSTR_HDR_EMIT8_TX] = instr_hdr_emit8_tx_exec,\n };\n \n static inline void\n", "prefixes": [ "v3", "10/41" ] }