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GET /api/patches/76942/?format=api
{ "id": 76942, "url": "http://patches.dpdk.org/api/patches/76942/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-10-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-10-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-10-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:17:58", "name": "[v3,09/41] pipeline: add SWX rx and extract instructions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d32e1af40f8a5a2208e7687198b7cf2b5a941095", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-10-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76942/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76942/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 30A32A04B1;\n\tTue, 8 Sep 2020 22:20:34 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 86C971C19A;\n\tTue, 8 Sep 2020 22:19:11 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id E456F1C0D0\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:18:57 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:41 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:40 -0700" ], "IronPort-SDR": [ "\n itHIbAa+Kv0zc3JRoZEkbvipI7dGW89nWCf2MxvjO3SjROFNndacye7GTZi0677telT32N6RbD\n upOz/Ev77m5Q==", "\n EViQ/PHwx1f5IeDQof7/SAU//cEETmMXfHpL990ZQeHP4wvyCGgjZNQNX9N+oc2FNwGqaAnCLn\n zI7c27kfNFbg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939388\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939388\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493397\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:17:58 +0100", "Message-Id": "<20200908201830.74206-10-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 09/41] pipeline: add SWX rx and extract\n\tinstructions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add packet reception and header extraction instructions. The RX must\nbe the first pipeline instruction. Each extracted header is logically\nremoved from the packet, then it can be read/written by instructions,\nemitted into the outgoing packet or discarded.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_pipeline_version.map | 1 +\n lib/librte_pipeline/rte_swx_pipeline.c | 564 ++++++++++++++++++-\n lib/librte_pipeline/rte_swx_pipeline.h | 13 +\n 3 files changed, 574 insertions(+), 4 deletions(-)", "diff": "diff --git a/lib/librte_pipeline/rte_pipeline_version.map b/lib/librte_pipeline/rte_pipeline_version.map\nindex 7139df0d3..793957eb9 100644\n--- a/lib/librte_pipeline/rte_pipeline_version.map\n+++ b/lib/librte_pipeline/rte_pipeline_version.map\n@@ -73,6 +73,7 @@ EXPERIMENTAL {\n \trte_swx_pipeline_instructions_config;\n \trte_swx_pipeline_build;\n \trte_swx_pipeline_free;\n+\trte_swx_pipeline_run;\n \trte_swx_pipeline_table_state_get;\n \trte_swx_pipeline_table_state_set;\n };\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 2ae6229d0..d7af80e39 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -8,6 +8,7 @@\n #include <sys/queue.h>\n \n #include <rte_common.h>\n+#include <rte_prefetch.h>\n \n #include \"rte_swx_pipeline.h\"\n #include \"rte_swx_ctl.h\"\n@@ -21,6 +22,16 @@ do { \\\n #define CHECK_NAME(name, err_code) \\\n \tCHECK((name) && (name)[0], err_code)\n \n+#ifndef TRACE_LEVEL\n+#define TRACE_LEVEL 0\n+#endif\n+\n+#if TRACE_LEVEL\n+#define TRACE(...) printf(__VA_ARGS__)\n+#else\n+#define TRACE(...)\n+#endif\n+\n /*\n * Struct.\n */\n@@ -181,7 +192,64 @@ struct header_out_runtime {\n /*\n * Instruction.\n */\n+\n+/* Packet headers are always in Network Byte Order (NBO), i.e. big endian.\n+ * Packet meta-data fields are always assumed to be in Host Byte Order (HBO).\n+ * Table entry fields can be in either NBO or HBO; they are assumed to be in HBO\n+ * when transferred to packet meta-data and in NBO when transferred to packet\n+ * headers.\n+ */\n+\n+/* Notation conventions:\n+ * -Header field: H = h.header.field (dst/src)\n+ * -Meta-data field: M = m.field (dst/src)\n+ * -Extern object mailbox field: E = e.field (dst/src)\n+ * -Extern function mailbox field: F = f.field (dst/src)\n+ * -Table action data field: T = t.field (src only)\n+ * -Immediate value: I = 32-bit unsigned value (src only)\n+ */\n+\n+enum instruction_type {\n+\t/* rx m.port_in */\n+\tINSTR_RX,\n+\n+\t/* extract h.header */\n+\tINSTR_HDR_EXTRACT,\n+\tINSTR_HDR_EXTRACT2,\n+\tINSTR_HDR_EXTRACT3,\n+\tINSTR_HDR_EXTRACT4,\n+\tINSTR_HDR_EXTRACT5,\n+\tINSTR_HDR_EXTRACT6,\n+\tINSTR_HDR_EXTRACT7,\n+\tINSTR_HDR_EXTRACT8,\n+};\n+\n+struct instr_io {\n+\tstruct {\n+\t\tuint8_t offset;\n+\t\tuint8_t n_bits;\n+\t\tuint8_t pad[2];\n+\t} io;\n+\n+\tstruct {\n+\t\tuint8_t header_id[8];\n+\t\tuint8_t struct_id[8];\n+\t\tuint8_t n_bytes[8];\n+\t} hdr;\n+};\n+\n struct instruction {\n+\tenum instruction_type type;\n+\tunion {\n+\t\tstruct instr_io io;\n+\t};\n+};\n+\n+struct instruction_data {\n+\tchar label[RTE_SWX_NAME_SIZE];\n+\tchar jmp_label[RTE_SWX_NAME_SIZE];\n+\tuint32_t n_users; /* user = jmp instruction to this instruction. */\n+\tint invalid;\n };\n \n /*\n@@ -251,6 +319,10 @@ struct table_runtime {\n * Pipeline.\n */\n struct thread {\n+\t/* Packet. */\n+\tstruct rte_swx_pkt pkt;\n+\tuint8_t *ptr;\n+\n \t/* Structures. */\n \tuint8_t **structs;\n \n@@ -280,6 +352,29 @@ struct thread {\n \tstruct instruction *ret;\n };\n \n+#define MASK64_BIT_GET(mask, pos) ((mask) & (1LLU << (pos)))\n+#define MASK64_BIT_SET(mask, pos) ((mask) | (1LLU << (pos)))\n+#define MASK64_BIT_CLR(mask, pos) ((mask) & ~(1LLU << (pos)))\n+\n+#define METADATA_READ(thread, offset, n_bits) \\\n+({ \\\n+\tuint64_t *m64_ptr = (uint64_t *)&(thread)->metadata[offset]; \\\n+\tuint64_t m64 = *m64_ptr; \\\n+\tuint64_t m64_mask = UINT64_MAX >> (64 - (n_bits)); \\\n+\t(m64 & m64_mask); \\\n+})\n+\n+#define METADATA_WRITE(thread, offset, n_bits, value) \\\n+{ \\\n+\tuint64_t *m64_ptr = (uint64_t *)&(thread)->metadata[offset]; \\\n+\tuint64_t m64 = *m64_ptr; \\\n+\tuint64_t m64_mask = UINT64_MAX >> (64 - (n_bits)); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t m_new = value; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*m64_ptr = (m64 & ~m64_mask) | (m_new & m64_mask); \\\n+}\n+\n #ifndef RTE_SWX_PIPELINE_THREADS_MAX\n #define RTE_SWX_PIPELINE_THREADS_MAX 16\n #endif\n@@ -315,6 +410,8 @@ struct rte_swx_pipeline {\n \tuint32_t n_actions;\n \tuint32_t n_tables;\n \tuint32_t n_headers;\n+\tuint32_t thread_id;\n+\tuint32_t port_id;\n \tuint32_t n_instructions;\n \tint build_done;\n \tint numa_node;\n@@ -1187,6 +1284,16 @@ header_find(struct rte_swx_pipeline *p, const char *name)\n \treturn NULL;\n }\n \n+static struct header *\n+header_parse(struct rte_swx_pipeline *p,\n+\t const char *name)\n+{\n+\tif (name[0] != 'h' || name[1] != '.')\n+\t\treturn NULL;\n+\n+\treturn header_find(p, &name[2]);\n+}\n+\n static struct field *\n header_field_parse(struct rte_swx_pipeline *p,\n \t\t const char *name,\n@@ -1430,19 +1537,459 @@ metadata_free(struct rte_swx_pipeline *p)\n /*\n * Instruction.\n */\n+static inline void\n+pipeline_port_inc(struct rte_swx_pipeline *p)\n+{\n+\tp->port_id = (p->port_id + 1) & (p->n_ports_in - 1);\n+}\n+\n static inline void\n thread_ip_reset(struct rte_swx_pipeline *p, struct thread *t)\n {\n \tt->ip = p->instructions;\n }\n \n+static inline void\n+thread_ip_inc(struct rte_swx_pipeline *p);\n+\n+static inline void\n+thread_ip_inc(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\n+\tt->ip++;\n+}\n+\n+static inline void\n+thread_ip_inc_cond(struct thread *t, int cond)\n+{\n+\tt->ip += cond;\n+}\n+\n+static inline void\n+thread_yield(struct rte_swx_pipeline *p)\n+{\n+\tp->thread_id = (p->thread_id + 1) & (RTE_SWX_PIPELINE_THREADS_MAX - 1);\n+}\n+\n+/*\n+ * rx.\n+ */\n+static int\n+instr_rx_translate(struct rte_swx_pipeline *p,\n+\t\t struct action *action,\n+\t\t char **tokens,\n+\t\t int n_tokens,\n+\t\t struct instruction *instr,\n+\t\t struct instruction_data *data __rte_unused)\n+{\n+\tstruct field *f;\n+\n+\tCHECK(!action, EINVAL);\n+\tCHECK(n_tokens == 2, EINVAL);\n+\n+\tf = metadata_field_parse(p, tokens[1]);\n+\tCHECK(f, EINVAL);\n+\n+\tinstr->type = INSTR_RX;\n+\tinstr->io.io.offset = f->offset / 8;\n+\tinstr->io.io.n_bits = f->n_bits;\n+\treturn 0;\n+}\n+\n+static inline void\n+instr_rx_exec(struct rte_swx_pipeline *p);\n+\n+static inline void\n+instr_rx_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tstruct port_in_runtime *port = &p->in[p->port_id];\n+\tstruct rte_swx_pkt *pkt = &t->pkt;\n+\tint pkt_received;\n+\n+\t/* Packet. */\n+\tpkt_received = port->pkt_rx(port->obj, pkt);\n+\tt->ptr = &pkt->pkt[pkt->offset];\n+\trte_prefetch0(t->ptr);\n+\n+\tTRACE(\"[Thread %2u] rx %s from port %u\\n\",\n+\t p->thread_id,\n+\t pkt_received ? \"1 pkt\" : \"0 pkts\",\n+\t p->port_id);\n+\n+\t/* Headers. */\n+\tt->valid_headers = 0;\n+\tt->n_headers_out = 0;\n+\n+\t/* Meta-data. */\n+\tMETADATA_WRITE(t, ip->io.io.offset, ip->io.io.n_bits, p->port_id);\n+\n+\t/* Tables. */\n+\tt->table_state = p->table_state;\n+\n+\t/* Thread. */\n+\tpipeline_port_inc(p);\n+\tthread_ip_inc_cond(t, pkt_received);\n+\tthread_yield(p);\n+}\n+\n+/*\n+ * extract.\n+ */\n+static int\n+instr_hdr_extract_translate(struct rte_swx_pipeline *p,\n+\t\t\t struct action *action,\n+\t\t\t char **tokens,\n+\t\t\t int n_tokens,\n+\t\t\t struct instruction *instr,\n+\t\t\t struct instruction_data *data __rte_unused)\n+{\n+\tstruct header *h;\n+\n+\tCHECK(!action, EINVAL);\n+\tCHECK(n_tokens == 2, EINVAL);\n+\n+\th = header_parse(p, tokens[1]);\n+\tCHECK(h, EINVAL);\n+\n+\tinstr->type = INSTR_HDR_EXTRACT;\n+\tinstr->io.hdr.header_id[0] = h->id;\n+\tinstr->io.hdr.struct_id[0] = h->struct_id;\n+\tinstr->io.hdr.n_bytes[0] = h->st->n_bits / 8;\n+\treturn 0;\n+}\n+\n+static inline void\n+__instr_hdr_extract_exec(struct rte_swx_pipeline *p, uint32_t n_extract);\n+\n+static inline void\n+__instr_hdr_extract_exec(struct rte_swx_pipeline *p, uint32_t n_extract)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tuint64_t valid_headers = t->valid_headers;\n+\tuint8_t *ptr = t->ptr;\n+\tuint32_t offset = t->pkt.offset;\n+\tuint32_t length = t->pkt.length;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < n_extract; i++) {\n+\t\tuint32_t header_id = ip->io.hdr.header_id[i];\n+\t\tuint32_t struct_id = ip->io.hdr.struct_id[i];\n+\t\tuint32_t n_bytes = ip->io.hdr.n_bytes[i];\n+\n+\t\tTRACE(\"[Thread %2u]: extract header %u (%u bytes)\\n\",\n+\t\t p->thread_id,\n+\t\t header_id,\n+\t\t n_bytes);\n+\n+\t\t/* Headers. */\n+\t\tt->structs[struct_id] = ptr;\n+\t\tvalid_headers = MASK64_BIT_SET(valid_headers, header_id);\n+\n+\t\t/* Packet. */\n+\t\toffset += n_bytes;\n+\t\tlength -= n_bytes;\n+\t\tptr += n_bytes;\n+\t}\n+\n+\t/* Headers. */\n+\tt->valid_headers = valid_headers;\n+\n+\t/* Packet. */\n+\tt->pkt.offset = offset;\n+\tt->pkt.length = length;\n+\tt->ptr = ptr;\n+}\n+\n+static inline void\n+instr_hdr_extract_exec(struct rte_swx_pipeline *p)\n+{\n+\t__instr_hdr_extract_exec(p, 1);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract2_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 2 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 2);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract3_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 3 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 3);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract4_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 4 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 4);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract5_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 5 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 5);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract6_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 6 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 6);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract7_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 7 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 7);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_hdr_extract8_exec(struct rte_swx_pipeline *p)\n+{\n+\tTRACE(\"[Thread %2u] *** The next 8 instructions are fused. ***\\n\",\n+\t p->thread_id);\n+\n+\t__instr_hdr_extract_exec(p, 8);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+#define RTE_SWX_INSTRUCTION_TOKENS_MAX 16\n+\n+static int\n+instr_translate(struct rte_swx_pipeline *p,\n+\t\tstruct action *action,\n+\t\tchar *string,\n+\t\tstruct instruction *instr,\n+\t\tstruct instruction_data *data)\n+{\n+\tchar *tokens[RTE_SWX_INSTRUCTION_TOKENS_MAX];\n+\tint n_tokens = 0, tpos = 0;\n+\n+\t/* Parse the instruction string into tokens. */\n+\tfor ( ; ; ) {\n+\t\tchar *token;\n+\n+\t\ttoken = strtok_r(string, \" \\t\\v\", &string);\n+\t\tif (!token)\n+\t\t\tbreak;\n+\n+\t\tCHECK(n_tokens < RTE_SWX_INSTRUCTION_TOKENS_MAX, EINVAL);\n+\n+\t\ttokens[n_tokens] = token;\n+\t\tn_tokens++;\n+\t}\n+\n+\tCHECK(n_tokens, EINVAL);\n+\n+\t/* Handle the optional instruction label. */\n+\tif ((n_tokens >= 2) && !strcmp(tokens[1], \":\")) {\n+\t\tstrcpy(data->label, tokens[0]);\n+\n+\t\ttpos += 2;\n+\t\tCHECK(n_tokens - tpos, EINVAL);\n+\t}\n+\n+\t/* Identify the instruction type. */\n+\tif (!strcmp(tokens[tpos], \"rx\"))\n+\t\treturn instr_rx_translate(p,\n+\t\t\t\t\t action,\n+\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t instr,\n+\t\t\t\t\t data);\n+\n+\tif (!strcmp(tokens[tpos], \"extract\"))\n+\t\treturn instr_hdr_extract_translate(p,\n+\t\t\t\t\t\t action,\n+\t\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t\t instr,\n+\t\t\t\t\t\t data);\n+\n+\tCHECK(0, EINVAL);\n+}\n+\n+static uint32_t\n+label_is_used(struct instruction_data *data, uint32_t n, const char *label)\n+{\n+\tuint32_t count = 0, i;\n+\n+\tif (!label[0])\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < n; i++)\n+\t\tif (!strcmp(label, data[i].jmp_label))\n+\t\t\tcount++;\n+\n+\treturn count;\n+}\n+\n static int\n-instruction_config(struct rte_swx_pipeline *p __rte_unused,\n-\t\t struct action *a __rte_unused,\n-\t\t const char **instructions __rte_unused,\n-\t\t uint32_t n_instructions __rte_unused)\n+instr_label_check(struct instruction_data *instruction_data,\n+\t\t uint32_t n_instructions)\n {\n+\tuint32_t i;\n+\n+\t/* Check that all instruction labels are unique. */\n+\tfor (i = 0; i < n_instructions; i++) {\n+\t\tstruct instruction_data *data = &instruction_data[i];\n+\t\tchar *label = data->label;\n+\t\tuint32_t j;\n+\n+\t\tif (!label[0])\n+\t\t\tcontinue;\n+\n+\t\tfor (j = i + 1; j < n_instructions; j++)\n+\t\t\tCHECK(strcmp(label, data[j].label), EINVAL);\n+\t}\n+\n+\t/* Get users for each instruction label. */\n+\tfor (i = 0; i < n_instructions; i++) {\n+\t\tstruct instruction_data *data = &instruction_data[i];\n+\t\tchar *label = data->label;\n+\n+\t\tdata->n_users = label_is_used(instruction_data,\n+\t\t\t\t\t n_instructions,\n+\t\t\t\t\t label);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+instruction_config(struct rte_swx_pipeline *p,\n+\t\t struct action *a,\n+\t\t const char **instructions,\n+\t\t uint32_t n_instructions)\n+{\n+\tstruct instruction *instr = NULL;\n+\tstruct instruction_data *data = NULL;\n+\tchar *string = NULL;\n+\tint err = 0;\n+\tuint32_t i;\n+\n+\tCHECK(n_instructions, EINVAL);\n+\tCHECK(instructions, EINVAL);\n+\tfor (i = 0; i < n_instructions; i++)\n+\t\tCHECK(instructions[i], EINVAL);\n+\n+\t/* Memory allocation. */\n+\tinstr = calloc(n_instructions, sizeof(struct instruction));\n+\tif (!instr) {\n+\t\terr = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tdata = calloc(n_instructions, sizeof(struct instruction_data));\n+\tif (!data) {\n+\t\terr = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tfor (i = 0; i < n_instructions; i++) {\n+\t\tstring = strdup(instructions[i]);\n+\t\tif (!string) {\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\n+\t\terr = instr_translate(p, a, string, &instr[i], &data[i]);\n+\t\tif (err)\n+\t\t\tgoto error;\n+\n+\t\tfree(string);\n+\t}\n+\n+\terr = instr_label_check(data, n_instructions);\n+\tif (err)\n+\t\tgoto error;\n+\n+\tfree(data);\n+\n+\tif (a) {\n+\t\ta->instructions = instr;\n+\t\ta->n_instructions = n_instructions;\n+\t} else {\n+\t\tp->instructions = instr;\n+\t\tp->n_instructions = n_instructions;\n+\t}\n+\n \treturn 0;\n+\n+error:\n+\tfree(string);\n+\tfree(data);\n+\tfree(instr);\n+\treturn err;\n+}\n+\n+typedef void (*instr_exec_t)(struct rte_swx_pipeline *);\n+\n+static instr_exec_t instruction_table[] = {\n+\t[INSTR_RX] = instr_rx_exec,\n+\n+\t[INSTR_HDR_EXTRACT] = instr_hdr_extract_exec,\n+\t[INSTR_HDR_EXTRACT2] = instr_hdr_extract2_exec,\n+\t[INSTR_HDR_EXTRACT3] = instr_hdr_extract3_exec,\n+\t[INSTR_HDR_EXTRACT4] = instr_hdr_extract4_exec,\n+\t[INSTR_HDR_EXTRACT5] = instr_hdr_extract5_exec,\n+\t[INSTR_HDR_EXTRACT6] = instr_hdr_extract6_exec,\n+\t[INSTR_HDR_EXTRACT7] = instr_hdr_extract7_exec,\n+\t[INSTR_HDR_EXTRACT8] = instr_hdr_extract8_exec,\n+};\n+\n+static inline void\n+instr_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\tinstr_exec_t instr = instruction_table[ip->type];\n+\n+\tinstr(p);\n }\n \n /*\n@@ -2226,6 +2773,15 @@ rte_swx_pipeline_build(struct rte_swx_pipeline *p)\n \treturn status;\n }\n \n+void\n+rte_swx_pipeline_run(struct rte_swx_pipeline *p, uint32_t n_instructions)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < n_instructions; i++)\n+\t\tinstr_exec(p);\n+}\n+\n /*\n * Control.\n */\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.h b/lib/librte_pipeline/rte_swx_pipeline.h\nindex 47a0f8dcc..fb83a8820 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.h\n+++ b/lib/librte_pipeline/rte_swx_pipeline.h\n@@ -534,6 +534,19 @@ __rte_experimental\n int\n rte_swx_pipeline_build(struct rte_swx_pipeline *p);\n \n+/**\n+ * Pipeline run\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] n_instructions\n+ * Number of instructions to execute.\n+ */\n+__rte_experimental\n+void\n+rte_swx_pipeline_run(struct rte_swx_pipeline *p,\n+\t\t uint32_t n_instructions);\n+\n /**\n * Pipeline free\n *\n", "prefixes": [ "v3", "09/41" ] }