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GET /api/patches/76936/?format=api
{ "id": 76936, "url": "http://patches.dpdk.org/api/patches/76936/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-3-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-3-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-3-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:17:51", "name": "[v3,02/41] pipeline: add SWX pipeline input port", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "515080f4faaaf8f136fc49b0824547bc74f8659c", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-3-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76936/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76936/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 818DFA04B1;\n\tTue, 8 Sep 2020 22:19:20 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CEFB91C10A;\n\tTue, 8 Sep 2020 22:18:59 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 22EB21DB8\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:18:53 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:33 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:32 -0700" ], "IronPort-SDR": [ "\n 3hni/BASWHMeEGzydw2CjhMwoKa7qbvFnQ+nrqbF1Vefj0oluHp4JcCAmHDkmtxkURxGUC2jiE\n g1YYTF6RidTw==", "\n eWNtEwWYxbpoKTCRkp2z743wR08EAlUdo1p5XAvEPpTxr5OwufpFReMz59LZUKRAQr6Lf2MZ+r\n 3fFOz3QklXRA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939362\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939362\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493357\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:17:51 +0100", "Message-Id": "<20200908201830.74206-3-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 02/41] pipeline: add SWX pipeline input port", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add input ports to the newly introduced SWX pipeline type. Each port\ninstantiates a port type that defines the port operations, e.g. ethdev\nport, PCAP port, etc. The RX interface is single packet, with packet\nbatching internally for performance.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_pipeline_version.map | 2 +\n lib/librte_pipeline/rte_swx_pipeline.c | 209 +++++++++++++++++++\n lib/librte_pipeline/rte_swx_pipeline.h | 54 +++++\n lib/librte_port/meson.build | 3 +-\n lib/librte_port/rte_swx_port.h | 118 +++++++++++\n 5 files changed, 385 insertions(+), 1 deletion(-)\n create mode 100644 lib/librte_port/rte_swx_port.h", "diff": "diff --git a/lib/librte_pipeline/rte_pipeline_version.map b/lib/librte_pipeline/rte_pipeline_version.map\nindex 39593f1ee..a9ebd3b1f 100644\n--- a/lib/librte_pipeline/rte_pipeline_version.map\n+++ b/lib/librte_pipeline/rte_pipeline_version.map\n@@ -56,6 +56,8 @@ EXPERIMENTAL {\n \trte_table_action_ttl_read;\n \trte_table_action_crypto_sym_session_get;\n \trte_swx_pipeline_config;\n+\trte_swx_pipeline_port_in_type_register;\n+\trte_swx_pipeline_port_in_config;\n \trte_swx_pipeline_build;\n \trte_swx_pipeline_free;\n };\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 2319d4570..5b1559209 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -5,6 +5,7 @@\n #include <string.h>\n #include <stdio.h>\n #include <errno.h>\n+#include <sys/queue.h>\n \n #include <rte_common.h>\n \n@@ -19,14 +20,206 @@ do { \\\n #define CHECK_NAME(name, err_code) \\\n \tCHECK((name) && (name)[0], err_code)\n \n+/*\n+ * Input port.\n+ */\n+struct port_in_type {\n+\tTAILQ_ENTRY(port_in_type) node;\n+\tchar name[RTE_SWX_NAME_SIZE];\n+\tstruct rte_swx_port_in_ops ops;\n+};\n+\n+TAILQ_HEAD(port_in_type_tailq, port_in_type);\n+\n+struct port_in {\n+\tTAILQ_ENTRY(port_in) node;\n+\tstruct port_in_type *type;\n+\tvoid *obj;\n+\tuint32_t id;\n+};\n+\n+TAILQ_HEAD(port_in_tailq, port_in);\n+\n+struct port_in_runtime {\n+\trte_swx_port_in_pkt_rx_t pkt_rx;\n+\tvoid *obj;\n+};\n+\n /*\n * Pipeline.\n */\n struct rte_swx_pipeline {\n+\tstruct port_in_type_tailq port_in_types;\n+\tstruct port_in_tailq ports_in;\n+\n+\tstruct port_in_runtime *in;\n+\n+\tuint32_t n_ports_in;\n \tint build_done;\n \tint numa_node;\n };\n \n+/*\n+ * Input port.\n+ */\n+static struct port_in_type *\n+port_in_type_find(struct rte_swx_pipeline *p, const char *name)\n+{\n+\tstruct port_in_type *elem;\n+\n+\tif (!name)\n+\t\treturn NULL;\n+\n+\tTAILQ_FOREACH(elem, &p->port_in_types, node)\n+\t\tif (strcmp(elem->name, name) == 0)\n+\t\t\treturn elem;\n+\n+\treturn NULL;\n+}\n+\n+int\n+rte_swx_pipeline_port_in_type_register(struct rte_swx_pipeline *p,\n+\t\t\t\t const char *name,\n+\t\t\t\t struct rte_swx_port_in_ops *ops)\n+{\n+\tstruct port_in_type *elem;\n+\n+\tCHECK(p, EINVAL);\n+\tCHECK_NAME(name, EINVAL);\n+\tCHECK(ops, EINVAL);\n+\tCHECK(ops->create, EINVAL);\n+\tCHECK(ops->free, EINVAL);\n+\tCHECK(ops->pkt_rx, EINVAL);\n+\tCHECK(ops->stats_read, EINVAL);\n+\n+\tCHECK(!port_in_type_find(p, name), EEXIST);\n+\n+\t/* Node allocation. */\n+\telem = calloc(1, sizeof(struct port_in_type));\n+\tCHECK(elem, ENOMEM);\n+\n+\t/* Node initialization. */\n+\tstrcpy(elem->name, name);\n+\tmemcpy(&elem->ops, ops, sizeof(*ops));\n+\n+\t/* Node add to tailq. */\n+\tTAILQ_INSERT_TAIL(&p->port_in_types, elem, node);\n+\n+\treturn 0;\n+}\n+\n+static struct port_in *\n+port_in_find(struct rte_swx_pipeline *p, uint32_t port_id)\n+{\n+\tstruct port_in *port;\n+\n+\tTAILQ_FOREACH(port, &p->ports_in, node)\n+\t\tif (port->id == port_id)\n+\t\t\treturn port;\n+\n+\treturn NULL;\n+}\n+\n+int\n+rte_swx_pipeline_port_in_config(struct rte_swx_pipeline *p,\n+\t\t\t\tuint32_t port_id,\n+\t\t\t\tconst char *port_type_name,\n+\t\t\t\tvoid *args)\n+{\n+\tstruct port_in_type *type = NULL;\n+\tstruct port_in *port = NULL;\n+\tvoid *obj = NULL;\n+\n+\tCHECK(p, EINVAL);\n+\n+\tCHECK(!port_in_find(p, port_id), EINVAL);\n+\n+\tCHECK_NAME(port_type_name, EINVAL);\n+\ttype = port_in_type_find(p, port_type_name);\n+\tCHECK(type, EINVAL);\n+\n+\tobj = type->ops.create(args);\n+\tCHECK(obj, ENODEV);\n+\n+\t/* Node allocation. */\n+\tport = calloc(1, sizeof(struct port_in));\n+\tCHECK(port, ENOMEM);\n+\n+\t/* Node initialization. */\n+\tport->type = type;\n+\tport->obj = obj;\n+\tport->id = port_id;\n+\n+\t/* Node add to tailq. */\n+\tTAILQ_INSERT_TAIL(&p->ports_in, port, node);\n+\tif (p->n_ports_in < port_id + 1)\n+\t\tp->n_ports_in = port_id + 1;\n+\n+\treturn 0;\n+}\n+\n+static int\n+port_in_build(struct rte_swx_pipeline *p)\n+{\n+\tstruct port_in *port;\n+\tuint32_t i;\n+\n+\tCHECK(p->n_ports_in, EINVAL);\n+\tCHECK(rte_is_power_of_2(p->n_ports_in), EINVAL);\n+\n+\tfor (i = 0; i < p->n_ports_in; i++)\n+\t\tCHECK(port_in_find(p, i), EINVAL);\n+\n+\tp->in = calloc(p->n_ports_in, sizeof(struct port_in_runtime));\n+\tCHECK(p->in, ENOMEM);\n+\n+\tTAILQ_FOREACH(port, &p->ports_in, node) {\n+\t\tstruct port_in_runtime *in = &p->in[port->id];\n+\n+\t\tin->pkt_rx = port->type->ops.pkt_rx;\n+\t\tin->obj = port->obj;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+port_in_build_free(struct rte_swx_pipeline *p)\n+{\n+\tfree(p->in);\n+\tp->in = NULL;\n+}\n+\n+static void\n+port_in_free(struct rte_swx_pipeline *p)\n+{\n+\tport_in_build_free(p);\n+\n+\t/* Input ports. */\n+\tfor ( ; ; ) {\n+\t\tstruct port_in *port;\n+\n+\t\tport = TAILQ_FIRST(&p->ports_in);\n+\t\tif (!port)\n+\t\t\tbreak;\n+\n+\t\tTAILQ_REMOVE(&p->ports_in, port, node);\n+\t\tport->type->ops.free(port->obj);\n+\t\tfree(port);\n+\t}\n+\n+\t/* Input port types. */\n+\tfor ( ; ; ) {\n+\t\tstruct port_in_type *elem;\n+\n+\t\telem = TAILQ_FIRST(&p->port_in_types);\n+\t\tif (!elem)\n+\t\t\tbreak;\n+\n+\t\tTAILQ_REMOVE(&p->port_in_types, elem, node);\n+\t\tfree(elem);\n+\t}\n+}\n \n /*\n * Pipeline.\n@@ -44,6 +237,9 @@ rte_swx_pipeline_config(struct rte_swx_pipeline **p, int numa_node)\n \tCHECK(pipeline, ENOMEM);\n \n \t/* Initialization. */\n+\tTAILQ_INIT(&pipeline->port_in_types);\n+\tTAILQ_INIT(&pipeline->ports_in);\n+\n \tpipeline->numa_node = numa_node;\n \n \t*p = pipeline;\n@@ -56,15 +252,28 @@ rte_swx_pipeline_free(struct rte_swx_pipeline *p)\n \tif (!p)\n \t\treturn;\n \n+\tport_in_free(p);\n+\n \tfree(p);\n }\n \n int\n rte_swx_pipeline_build(struct rte_swx_pipeline *p)\n {\n+\tint status;\n+\n \tCHECK(p, EINVAL);\n \tCHECK(p->build_done == 0, EEXIST);\n \n+\tstatus = port_in_build(p);\n+\tif (status)\n+\t\tgoto error;\n+\n \tp->build_done = 1;\n \treturn 0;\n+\n+error:\n+\tport_in_build_free(p);\n+\n+\treturn status;\n }\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.h b/lib/librte_pipeline/rte_swx_pipeline.h\nindex ded26a4e4..3dbe7ce0b 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.h\n+++ b/lib/librte_pipeline/rte_swx_pipeline.h\n@@ -18,6 +18,12 @@ extern \"C\" {\n \n #include <rte_compat.h>\n \n+#include \"rte_swx_port.h\"\n+\n+/** Name size. */\n+#ifndef RTE_SWX_NAME_SIZE\n+#define RTE_SWX_NAME_SIZE 64\n+#endif\n /*\n * Pipeline setup and operation\n */\n@@ -43,6 +49,54 @@ int\n rte_swx_pipeline_config(struct rte_swx_pipeline **p,\n \t\t\tint numa_node);\n \n+/*\n+ * Pipeline input ports\n+ */\n+\n+/**\n+ * Pipeline input port type register\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] name\n+ * Input port type name.\n+ * @param[in] ops\n+ * Input port type operations.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough space/cannot allocate memory;\n+ * -EEXIST: Input port type with this name already exists.\n+ */\n+__rte_experimental\n+int\n+rte_swx_pipeline_port_in_type_register(struct rte_swx_pipeline *p,\n+\t\t\t\t const char *name,\n+\t\t\t\t struct rte_swx_port_in_ops *ops);\n+\n+/**\n+ * Pipeline input port configure\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] port_id\n+ * Input port ID.\n+ * @param[in] port_type_name\n+ * Existing input port type name.\n+ * @param[in] args\n+ * Input port creation arguments.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough space/cannot allocate memory;\n+ * -ENODEV: Input port object creation error.\n+ */\n+__rte_experimental\n+int\n+rte_swx_pipeline_port_in_config(struct rte_swx_pipeline *p,\n+\t\t\t\tuint32_t port_id,\n+\t\t\t\tconst char *port_type_name,\n+\t\t\t\tvoid *args);\n /**\n * Pipeline build\n *\ndiff --git a/lib/librte_port/meson.build b/lib/librte_port/meson.build\nindex 0d5ede44a..5b5fbf6c4 100644\n--- a/lib/librte_port/meson.build\n+++ b/lib/librte_port/meson.build\n@@ -21,7 +21,8 @@ headers = files(\n \t'rte_port_sched.h',\n \t'rte_port_source_sink.h',\n \t'rte_port_sym_crypto.h',\n-\t'rte_port_eventdev.h')\n+\t'rte_port_eventdev.h',\n+\t'rte_swx_port.h',)\n deps += ['ethdev', 'sched', 'ip_frag', 'cryptodev', 'eventdev']\n \n if dpdk_conf.has('RTE_PORT_PCAP')\ndiff --git a/lib/librte_port/rte_swx_port.h b/lib/librte_port/rte_swx_port.h\nnew file mode 100644\nindex 000000000..a6f80de9a\n--- /dev/null\n+++ b/lib/librte_port/rte_swx_port.h\n@@ -0,0 +1,118 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+#ifndef __INCLUDE_RTE_SWX_PORT_H__\n+#define __INCLUDE_RTE_SWX_PORT_H__\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * @file\n+ * RTE SWX Port\n+ *\n+ * Packet I/O port interface.\n+ */\n+\n+#include <stdint.h>\n+\n+/** Packet. */\n+struct rte_swx_pkt {\n+\t/** Opaque packet handle. */\n+\tvoid *handle;\n+\n+\t/** Buffer where the packet is stored. */\n+\tuint8_t *pkt;\n+\n+\t/** Packet buffer offset of the first packet byte. */\n+\tuint32_t offset;\n+\n+\t/** Packet length in bytes. */\n+\tuint32_t length;\n+};\n+\n+/*\n+ * Input port\n+ */\n+\n+/**\n+ * Input port create\n+ *\n+ * @param[in] args\n+ * Arguments for input port creation. Format specific to each port type.\n+ * @return\n+ * Handle to input port instance on success, NULL on error.\n+ */\n+typedef void *\n+(*rte_swx_port_in_create_t)(void *args);\n+\n+/**\n+ * Input port free\n+ *\n+ * @param[in] args\n+ * Input port handle.\n+ */\n+typedef void\n+(*rte_swx_port_in_free_t)(void *port);\n+\n+/**\n+ * Input port packet receive\n+ *\n+ * @param[in] port\n+ * Input port handle.\n+ * @param[out] pkt\n+ * Received packet. Only valid when the function returns 1. Must point to\n+ * valid memory.\n+ * @return\n+ * 0 when no packet was received, 1 when a packet was received. No other\n+ * return values are allowed.\n+ */\n+typedef int\n+(*rte_swx_port_in_pkt_rx_t)(void *port,\n+\t\t\t struct rte_swx_pkt *pkt);\n+\n+/** Input port statistics counters. */\n+struct rte_swx_port_in_stats {\n+\t/** Number of packets. */\n+\tuint64_t n_pkts;\n+\n+\t/** Number of bytes. */\n+\tuint64_t n_bytes;\n+\n+\t/** Number of empty polls. */\n+\tuint64_t n_empty;\n+};\n+\n+/**\n+ * Input port statistics counters read\n+ *\n+ * @param[in] port\n+ * Input port handle.\n+ * @param[out] stats\n+ * Input port statistics counters. Must point to valid memory.\n+ */\n+typedef void\n+(*rte_swx_port_in_stats_read_t)(void *port,\n+\t\t\t\tstruct rte_swx_port_in_stats *stats);\n+\n+/** Input port operations. */\n+struct rte_swx_port_in_ops {\n+\t/** Create. Must be non-NULL. */\n+\trte_swx_port_in_create_t create;\n+\n+\t/** Free. Must be non-NULL. */\n+\trte_swx_port_in_free_t free;\n+\n+\t/** Packet reception. Must be non-NULL. */\n+\trte_swx_port_in_pkt_rx_t pkt_rx;\n+\n+\t/** Statistics counters read. Must be non-NULL. */\n+\trte_swx_port_in_stats_read_t stats_read;\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n", "prefixes": [ "v3", "02/41" ] }