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GET /api/patches/76912/?format=api
{ "id": 76912, "url": "http://patches.dpdk.org/api/patches/76912/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908100956.25868-4-adwivedi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908100956.25868-4-adwivedi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908100956.25868-4-adwivedi@marvell.com", "date": "2020-09-08T10:09:56", "name": "[3/3] event/octeontx2: add crypto adapter datapath", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1a895021b58291c3e7dab15b1fbaf4e3057e8d9d", "submitter": { "id": 1561, "url": "http://patches.dpdk.org/api/people/1561/?format=api", "name": "Ankur Dwivedi", "email": "adwivedi@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908100956.25868-4-adwivedi@marvell.com/mbox/", "series": [ { "id": 12021, "url": "http://patches.dpdk.org/api/series/12021/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12021", "date": "2020-09-08T10:09:53", "name": "event/octeontx2: add support for event crypto adapter", "version": 1, "mbox": "http://patches.dpdk.org/series/12021/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76912/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/76912/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F1288A04AA;\n\tTue, 8 Sep 2020 12:10:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CE05B2BAB;\n\tTue, 8 Sep 2020 12:10:53 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A03021C0D2\n for <dev@dpdk.org>; Tue, 8 Sep 2020 12:10:52 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 088A57pb020476; Tue, 8 Sep 2020 03:10:51 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0a-0016f401.pphosted.com with ESMTP id 33c81pu22q-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 08 Sep 2020 03:10:51 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 8 Sep 2020 03:10:50 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 8 Sep 2020 03:10:49 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 8 Sep 2020 03:10:49 -0700", "from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13])\n by maili.marvell.com (Postfix) with ESMTP id AEDA63F703F;\n Tue, 8 Sep 2020 03:10:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=R43x4jYdVSOhpDAbdt57Lc7kb1meNx5oJiuOKW3h9U4=;\n b=eiuo4Ysf73VBUz/DPsM6JNqJK1AiEScqbfH0t+lQDPtJbqYAFlbfD0k2hiLD0jAdX59j\n tnKLf7yRFME+DZ9TndDlp1CCaELA893xU8hCop4MqsVZac/JtWZTZEtEEtHMHUVTy8pi\n VSyLO83IXEgcNQnbVUJ7qQM+Kg6OFuiPr55fhJPv/rMoCIHG8WkN6I03KALVNyU6H+dC\n tmg0GpD05eS2ZAwtjwNw19LPghqVnyWEquuTEvG1uVV3GM80imY2O716G5CE5f3XNaLU\n /4mqbCAIkYQFLGXkMsVurR1bIkhdd07KgFCH/b37RKHWmtLOJ4Bb0EaZPjcqE/+X1Q9o 2A==", "From": "Ankur Dwivedi <adwivedi@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <pbhagavatula@marvell.com>, <akhil.goyal@nxp.com>,\n <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>", "Date": "Tue, 8 Sep 2020 15:39:56 +0530", "Message-ID": "<20200908100956.25868-4-adwivedi@marvell.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20200908100956.25868-1-adwivedi@marvell.com>", "References": "<20200908100956.25868-1-adwivedi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-09-08_05:2020-09-08,\n 2020-09-08 signatures=0", "Subject": "[dpdk-dev] [PATCH 3/3] event/octeontx2: add crypto adapter datapath", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In the op new mode of crypto adapter, the completed crypto operation\nis submitted to the event device by the OCTEON TX2 crypto PMD.\nDuring event device dequeue the result of crypto operation is checked.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\n---\n drivers/common/cpt/cpt_common.h | 1 +\n drivers/crypto/octeontx2/otx2_ca_helper.h | 75 +++++++++++++++++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 47 ++++++++++++\n .../rte_pmd_octeontx2_crypto_version.map | 1 +\n drivers/event/octeontx2/meson.build | 1 +\n drivers/event/octeontx2/otx2_worker.h | 10 ++-\n drivers/event/octeontx2/otx2_worker_dual.h | 11 ++-\n 7 files changed, 142 insertions(+), 4 deletions(-)\n create mode 100644 drivers/crypto/octeontx2/otx2_ca_helper.h", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nindex 0141b2aed..1ce28e90b 100644\n--- a/drivers/common/cpt/cpt_common.h\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -72,6 +72,7 @@ struct cpt_request_info {\n \t\tuint64_t ei3;\n \t} ist;\n \tuint8_t *rptr;\n+\tconst struct otx2_cpt_qp *qp;\n \n \t/** Control path fields */\n \tuint64_t time_out;\ndiff --git a/drivers/crypto/octeontx2/otx2_ca_helper.h b/drivers/crypto/octeontx2/otx2_ca_helper.h\nnew file mode 100644\nindex 000000000..a6c758cf9\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_ca_helper.h\n@@ -0,0 +1,75 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CA_HELPER_H_\n+#define _OTX2_CA_HELPER_H_\n+\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_eventdev.h>\n+\n+#include \"cpt_pmd_logs.h\"\n+#include \"cpt_ucode.h\"\n+\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_hw_access.h\"\n+#include \"otx2_cryptodev_ops_helper.h\"\n+#include \"otx2_cryptodev_qp.h\"\n+\n+static inline void\n+otx2_ca_deq_post_process(const struct otx2_cpt_qp *qp,\n+\t\t\t struct rte_crypto_op *cop, uintptr_t *rsp,\n+\t\t\t uint8_t cc)\n+{\n+\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\tif (likely(cc == NO_ERR)) {\n+\t\t\t/* Verify authentication data if required */\n+\t\t\tif (unlikely(rsp[2]))\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n+\t\t\t\t\t\t rsp[3]);\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t} else {\n+\t\t\tif (cc == ERR_GC_ICV_MISCOMPARE)\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t}\n+\n+\t\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\t\tsym_session_clear(otx2_cryptodev_driver_id,\n+\t\t\t\t\t cop->sym->session);\n+\t\t\tmemset(cop->sym->session, 0,\n+\t\t\trte_cryptodev_sym_get_existing_header_session_size(\n+\t\t\t\tcop->sym->session));\n+\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n+\t\t\tcop->sym->session = NULL;\n+\t\t}\n+\t}\n+\n+}\n+\n+static __rte_always_inline uint64_t\n+otx2_handle_crypto_event(uint64_t get_work1)\n+{\n+\tstruct cpt_request_info *req;\n+\tstruct rte_crypto_op *cop;\n+\tuintptr_t *rsp;\n+\tvoid *metabuf;\n+\tuint8_t cc;\n+\n+\treq = (struct cpt_request_info *)(get_work1 >> 3);\n+\tcc = otx2_cpt_compcode_get(req);\n+\n+\trsp = req->op;\n+\tmetabuf = (void *)rsp[0];\n+\tcop = (void *)rsp[1];\n+\n+\totx2_ca_deq_post_process(req->qp, cop, rsp, cc);\n+\n+\trte_mempool_put(req->qp->meta_info.pool, metabuf);\n+\n+\treturn (uint64_t)(cop);\n+}\n+#endif /* _OTX2_CA_HELPER_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 77842b4ad..53c118287 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -417,6 +417,48 @@ sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,\n \treturn -ENOTSUP;\n }\n \n+static __rte_always_inline void __rte_hot\n+otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n+\t\t struct cpt_request_info *req,\n+\t\t void *lmtline)\n+{\n+\tunion cpt_inst_s inst;\n+\tuint64_t lmt_status;\n+\n+\tinst.u[0] = 0;\n+\tinst.s9x.res_addr = req->comp_baddr;\n+\tinst.u[2] = 0;\n+\tinst.u[3] = 0;\n+\n+\tinst.s9x.ei0 = req->ist.ei0;\n+\tinst.s9x.ei1 = req->ist.ei1;\n+\tinst.s9x.ei2 = req->ist.ei2;\n+\tinst.s9x.ei3 = req->ist.ei3;\n+\n+\tinst.s9x.qord = 1;\n+\tinst.s9x.grp = qp->ev.queue_id;\n+\tinst.s9x.tt = qp->ev.sched_type;\n+\tinst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |\n+\t\t\tqp->ev.flow_id;\n+\tinst.s9x.wq_ptr = (uint64_t)req;\n+\treq->qp = qp;\n+\n+\tdo {\n+\t\t/* Copy CPT command to LMTLINE */\n+\t\tmemcpy(lmtline, &inst, sizeof(inst));\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_cio_wmb();\n+\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n+\t} while (lmt_status == 0);\n+\n+}\n+\n static __rte_always_inline int32_t __rte_hot\n otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\t struct pending_queue *pend_q,\n@@ -426,6 +468,11 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \tunion cpt_inst_s inst;\n \tuint64_t lmt_status;\n \n+\tif (qp->ca_enable) {\n+\t\totx2_ca_enqueue_req(qp, req, lmtline);\n+\t\treturn 0;\n+\t}\n+\n \tif (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))\n \t\treturn -EAGAIN;\n \ndiff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\nindex b47a7ad3e..d23764d2c 100644\n--- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n@@ -5,6 +5,7 @@ DPDK_21 {\n INTERNAL {\n \tglobal:\n \n+\totx2_cryptodev_driver_id;\n \totx2_ca_caps_get;\n \totx2_ca_qp_add;\n \totx2_ca_qp_del;\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex 8585c54e4..08863a3e3 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -27,3 +27,4 @@ endforeach\n deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2', 'pmd_octeontx2_crypto']\n \n includes += include_directories('../../crypto/octeontx2')\n+includes += include_directories('../../common/cpt')\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\nindex 924ff7ff4..5ea2c2de2 100644\n--- a/drivers/event/octeontx2/otx2_worker.h\n+++ b/drivers/event/octeontx2/otx2_worker.h\n@@ -9,6 +9,7 @@\n #include <rte_branch_prediction.h>\n \n #include <otx2_common.h>\n+#include \"otx2_ca_helper.h\"\n #include \"otx2_evdev.h\"\n #include \"otx2_ethdev_sec_tx.h\"\n \n@@ -66,8 +67,10 @@ otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,\n \tws->cur_tt = event.sched_type;\n \tws->cur_grp = event.queue_id;\n \n-\tif (event.sched_type != SSO_TT_EMPTY &&\n-\t event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n+\tif (event.sched_type == SSO_TT_EMPTY)\n+\t\tgoto setev_and_return;\n+\n+\tif (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n \t\totx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,\n \t\t\t\t (uint32_t) event.get_work0, flags, lookup_mem);\n \t\t/* Extracting tstamp, if PTP enabled*/\n@@ -76,8 +79,11 @@ otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,\n \t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, ws->tstamp,\n \t\t\t\t\tflags, (uint64_t *)tstamp_ptr);\n \t\tget_work1 = mbuf;\n+\t} else if (event.event_type == RTE_EVENT_TYPE_CRYPTODEV) {\n+\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n \t}\n \n+setev_and_return:\n \tev->event = event.get_work0;\n \tev->u64 = get_work1;\n \ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h\nindex 60aa14cca..4bf4e0170 100644\n--- a/drivers/event/octeontx2/otx2_worker_dual.h\n+++ b/drivers/event/octeontx2/otx2_worker_dual.h\n@@ -9,6 +9,8 @@\n #include <rte_common.h>\n \n #include <otx2_common.h>\n+\n+#include \"otx2_ca_helper.h\"\n #include \"otx2_evdev.h\"\n \n /* SSO Operations */\n@@ -63,8 +65,10 @@ otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,\n \tws->cur_tt = event.sched_type;\n \tws->cur_grp = event.queue_id;\n \n-\tif (event.sched_type != SSO_TT_EMPTY &&\n-\t event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n+\tif (event.sched_type == SSO_TT_EMPTY)\n+\t\tgoto setev_and_return;\n+\n+\tif (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n \t\tuint8_t port = event.sub_event_type;\n \n \t\tevent.sub_event_type = 0;\n@@ -82,8 +86,11 @@ otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,\n \t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp, flags,\n \t\t\t\t\t(uint64_t *)tstamp_ptr);\n \t\tget_work1 = mbuf;\n+\t} else if (event.event_type == RTE_EVENT_TYPE_CRYPTODEV) {\n+\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n \t}\n \n+setev_and_return:\n \tev->event = event.get_work0;\n \tev->u64 = get_work1;\n \n", "prefixes": [ "3/3" ] }