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GET /api/patches/76664/?format=api
{ "id": 76664, "url": "http://patches.dpdk.org/api/patches/76664/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200907091711.5980-4-junyux.jiang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200907091711.5980-4-junyux.jiang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200907091711.5980-4-junyux.jiang@intel.com", "date": "2020-09-07T09:17:09", "name": "[v2,3/5] net/ice: support flow mark in AVX path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8272026b06e576a7053dbbad9392a5238de637e9", "submitter": { "id": 1408, "url": "http://patches.dpdk.org/api/people/1408/?format=api", "name": "Junyu Jiang", "email": "junyux.jiang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200907091711.5980-4-junyux.jiang@intel.com/mbox/", "series": [ { "id": 11987, "url": "http://patches.dpdk.org/api/series/11987/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11987", "date": "2020-09-07T09:17:06", "name": "supports RxDID #22 and FDID", "version": 2, "mbox": "http://patches.dpdk.org/series/11987/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76664/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A4F3A04B9;\n\tMon, 7 Sep 2020 11:27:02 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E1A91C10E;\n\tMon, 7 Sep 2020 11:26:41 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 5D8231C0D1\n for <dev@dpdk.org>; Mon, 7 Sep 2020 11:26:39 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Sep 2020 02:26:39 -0700", "from unknown (HELO intel.sh.intel.com) ([10.239.255.60])\n by fmsmga001.fm.intel.com with ESMTP; 07 Sep 2020 02:26:37 -0700" ], "IronPort-SDR": [ "\n 6UvYDMW2NwhgBftd/lxZmDvMmFmq6+66/7Nv8/boR6nrtp07zcog2VLeeJahUpFjQKJwR5v7ku\n Abzqu6X6DIzg==", "\n 65MYvCv0+A0/DPWpOdZCujcHwS7CGkA/ewAs19kcjDsIRcHy5hgi4R3Io5KbtuxLBR+4O7Sxqf\n 5pDM0EOA6dOQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9736\"; a=\"157241155\"", "E=Sophos;i=\"5.76,401,1592895600\"; d=\"scan'208\";a=\"157241155\"", "E=Sophos;i=\"5.76,401,1592895600\"; d=\"scan'208\";a=\"406783306\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Junyu Jiang <junyux.jiang@intel.com>", "To": "dev@dpdk.org", "Cc": "Qi Zhang <qi.z.zhang@intel.com>, Qiming Yang <qiming.yang@intel.com>,\n Guinan Sun <guinanx.sun@intel.com>", "Date": "Mon, 7 Sep 2020 09:17:09 +0000", "Message-Id": "<20200907091711.5980-4-junyux.jiang@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200907091711.5980-1-junyux.jiang@intel.com>", "References": "<20200826075501.50052-1-guinanx.sun@intel.com>\n <20200907091711.5980-1-junyux.jiang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 3/5] net/ice: support flow mark in AVX path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Guinan Sun <guinanx.sun@intel.com>\n\nSupport Flow Director mark ID parsing from Flex\nRx descriptor in AVX path.\n\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/ice/ice_rxtx_vec_avx2.c | 64 ++++++++++++++++++++++++++++-\n 1 file changed, 63 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c\nindex 07d129e3f..70e4b76db 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx2.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c\n@@ -132,6 +132,25 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)\n \tICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n }\n \n+static inline __m256i\n+ice_flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)\n+{\n+#define FDID_MIS_MAGIC 0xFFFFFFFF\n+\tRTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));\n+\tRTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));\n+\tconst __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |\n+\t\t\tPKT_RX_FDIR_ID);\n+\t/* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */\n+\tconst __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);\n+\t__m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,\n+\t\t\tfdir_mis_mask);\n+\t/* this XOR op results to bit-reverse the fdir_mask */\n+\tfdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);\n+\tconst __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);\n+\n+\treturn fdir_flags;\n+}\n+\n static inline uint16_t\n _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts, uint8_t *split_packet)\n@@ -459,9 +478,51 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\t\t\t rss_vlan_flag_bits);\n \n \t\t/* merge flags */\n-\t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t__m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n \t\t\t\trss_vlan_flags);\n \n+\t\tif (rxq->fdir_enabled) {\n+\t\t\tconst __m256i fdir_id4_7 =\n+\t\t\t\t_mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);\n+\n+\t\t\tconst __m256i fdir_id0_3 =\n+\t\t\t\t_mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);\n+\n+\t\t\tconst __m256i fdir_id0_7 =\n+\t\t\t\t_mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);\n+\n+\t\t\tconst __m256i fdir_flags =\n+\t\t\t\tice_flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7);\n+\n+\t\t\t/* merge with fdir_flags */\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);\n+\n+\t\t\t/* write to mbuf: have to use scalar store here */\n+\t\t\trx_pkts[i + 0]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 3);\n+\n+\t\t\trx_pkts[i + 1]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 7);\n+\n+\t\t\trx_pkts[i + 2]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 2);\n+\n+\t\t\trx_pkts[i + 3]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 6);\n+\n+\t\t\trx_pkts[i + 4]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 1);\n+\n+\t\t\trx_pkts[i + 5]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 5);\n+\n+\t\t\trx_pkts[i + 6]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 0);\n+\n+\t\t\trx_pkts[i + 7]->hash.fdir.hi =\n+\t\t\t\t_mm256_extract_epi32(fdir_id0_7, 4);\n+\t\t} /* if() on fdir_enabled */\n+\n #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n \t\t/**\n \t\t * needs to load 2nd 16B of each desc for RSS hash parsing,\n@@ -551,6 +612,7 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\tmb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);\n \t\t} /* if() on RSS hash parsing */\n #endif\n+\n \t\t/**\n \t\t * At this point, we have the 8 sets of flags in the low 16-bits\n \t\t * of each 32-bit value in vlan0.\n", "prefixes": [ "v2", "3/5" ] }