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{
    "id": 76409,
    "url": "http://patches.dpdk.org/api/patches/76409/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200903144942.671870-3-bruce.richardson@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200903144942.671870-3-bruce.richardson@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200903144942.671870-3-bruce.richardson@intel.com",
    "date": "2020-09-03T14:49:41",
    "name": "[v2,2/3] config: allow overriding some build defaults",
    "commit_ref": null,
    "pull_url": null,
    "state": "rejected",
    "archived": true,
    "hash": "9dece0c73b71536437eca6326aa640752acc0838",
    "submitter": {
        "id": 20,
        "url": "http://patches.dpdk.org/api/people/20/?format=api",
        "name": "Bruce Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200903144942.671870-3-bruce.richardson@intel.com/mbox/",
    "series": [
        {
            "id": 11928,
            "url": "http://patches.dpdk.org/api/series/11928/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11928",
            "date": "2020-09-03T14:49:39",
            "name": "Allow overriding of build-time constants",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/11928/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/76409/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/76409/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 04B30A04BF;\n\tThu,  3 Sep 2020 16:50:14 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DB9F41C0C5;\n\tThu,  3 Sep 2020 16:49:59 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 2F53F1C0C0\n for <dev@dpdk.org>; Thu,  3 Sep 2020 16:49:57 +0200 (CEST)",
            "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 Sep 2020 07:49:56 -0700",
            "from silpixa00399126.ir.intel.com ([10.237.222.27])\n by orsmga004.jf.intel.com with ESMTP; 03 Sep 2020 07:49:55 -0700"
        ],
        "IronPort-SDR": [
            "\n iZUVSCkXJeiUipRSFAW4dec0DWgLR72LE1mt6D8EIpb0HKeIRjnVUuEXXNIwBmii1fBTNYP6JH\n y3jsPDjdwgkg==",
            "\n d2wxgt3CN+Oiy9VhBeIb/8pALPqXAeOPMvHT9VDbPZkMYZ7Wob1hfujsRZQviIB4J0/Ez62DQL\n ah/BBKbpgZzQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9733\"; a=\"242403456\"",
            "E=Sophos;i=\"5.76,387,1592895600\"; d=\"scan'208\";a=\"242403456\"",
            "E=Sophos;i=\"5.76,387,1592895600\"; d=\"scan'208\";a=\"446930292\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Bruce Richardson <bruce.richardson@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Ma Lihong <lihongx.ma@intel.com>, Hemant Agrawal <hemant.agrawal@nxp.com>,\n Bruce Richardson <bruce.richardson@intel.com>",
        "Date": "Thu,  3 Sep 2020 15:49:41 +0100",
        "Message-Id": "<20200903144942.671870-3-bruce.richardson@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20200903144942.671870-1-bruce.richardson@intel.com>",
        "References": "<20200825114447.135030-1-bruce.richardson@intel.com>\n <20200903144942.671870-1-bruce.richardson@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 2/3] config: allow overriding some build\n\tdefaults",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "In case a developer uses CFLAGS to set different default values for the\ndefines in the rte_config.h file, use #ifndef / #endif guards around the\nsetting of those values. For those lines just \"defining\" a macro without\nassigning it a value to be used by code, drop the value argument (where\npossible) to make it clearer that that is what is happening, since those\ndon't need the #ifdef guard.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\nTested-by: Lihong Ma <lihongx.ma@intel.com>\n---\n config/rte_config.h | 110 +++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 99 insertions(+), 11 deletions(-)",
    "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex 1c5a86d6a..f39da76c1 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017 Intel Corporation\n+ * Copyright(c) 2017-2020 Intel Corporation\n  */\n \n /**\n@@ -20,10 +20,10 @@\n \n /* legacy defines */\n #ifdef RTE_EXEC_ENV_LINUX\n-#define RTE_EXEC_ENV_LINUXAPP 1\n+#define RTE_EXEC_ENV_LINUXAPP\n #endif\n #ifdef RTE_EXEC_ENV_FREEBSD\n-#define RTE_EXEC_ENV_BSDAPP 1\n+#define RTE_EXEC_ENV_BSDAPP\n #endif\n \n /* String that appears before the version number */\n@@ -32,107 +32,195 @@\n /****** library defines ********/\n \n /* EAL defines */\n+#define RTE_BACKTRACE\n+#ifndef RTE_MAX_HEAPS\n #define RTE_MAX_HEAPS 32\n+#endif\n+#ifndef RTE_MAX_MEMSEG_LISTS\n #define RTE_MAX_MEMSEG_LISTS 128\n+#endif\n+#ifndef RTE_MAX_MEMSEG_PER_LIST\n #define RTE_MAX_MEMSEG_PER_LIST 8192\n+#endif\n+#ifndef RTE_MAX_MEM_MB_PER_LIST\n #define RTE_MAX_MEM_MB_PER_LIST 32768\n+#endif\n+#ifndef RTE_MAX_MEMSEG_PER_TYPE\n #define RTE_MAX_MEMSEG_PER_TYPE 32768\n+#endif\n+#ifndef RTE_MAX_MEM_MB_PER_TYPE\n #define RTE_MAX_MEM_MB_PER_TYPE 65536\n+#endif\n+#ifndef RTE_MAX_MEMZONE\n #define RTE_MAX_MEMZONE 2560\n+#endif\n+#ifndef RTE_MAX_TAILQ\n #define RTE_MAX_TAILQ 32\n+#endif\n+#ifndef RTE_LOG_DP_LEVEL\n #define RTE_LOG_DP_LEVEL RTE_LOG_INFO\n-#define RTE_BACKTRACE 1\n+#endif\n+#ifndef RTE_MAX_VFIO_CONTAINERS\n #define RTE_MAX_VFIO_CONTAINERS 64\n+#endif\n \n /* bsd module defines */\n+#ifndef RTE_CONTIGMEM_MAX_NUM_BUFS\n #define RTE_CONTIGMEM_MAX_NUM_BUFS 64\n+#endif\n+#ifndef RTE_CONTIGMEM_DEFAULT_NUM_BUFS\n #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1\n+#endif\n+#ifndef RTE_CONTIGMEM_DEFAULT_BUF_SIZE\n #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)\n+#endif\n \n /* mempool defines */\n+#ifndef RTE_MEMPOOL_CACHE_MAX_SIZE\n #define RTE_MEMPOOL_CACHE_MAX_SIZE 512\n+#endif\n \n /* mbuf defines */\n+#define RTE_MBUF_REFCNT_ATOMIC\n+#ifndef RTE_MBUF_DEFAULT_MEMPOOL_OPS\n #define RTE_MBUF_DEFAULT_MEMPOOL_OPS \"ring_mp_mc\"\n-#define RTE_MBUF_REFCNT_ATOMIC 1\n+#endif\n+#ifndef RTE_PKTMBUF_HEADROOM\n #define RTE_PKTMBUF_HEADROOM 128\n+#endif\n \n /* ether defines */\n+#define RTE_ETHDEV_RXTX_CALLBACKS\n+#ifndef RTE_MAX_QUEUES_PER_PORT\n #define RTE_MAX_QUEUES_PER_PORT 1024\n+#endif\n+#ifndef RTE_ETHDEV_QUEUE_STAT_CNTRS\n #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16\n-#define RTE_ETHDEV_RXTX_CALLBACKS 1\n+#endif\n \n /* cryptodev defines */\n+#ifndef RTE_CRYPTO_MAX_DEVS\n #define RTE_CRYPTO_MAX_DEVS 64\n+#endif\n+#ifndef RTE_CRYPTODEV_NAME_LEN\n #define RTE_CRYPTODEV_NAME_LEN 64\n+#endif\n \n /* compressdev defines */\n+#ifndef RTE_COMPRESS_MAX_DEVS\n #define RTE_COMPRESS_MAX_DEVS 64\n+#endif\n \n /* regexdev defines */\n+#ifndef RTE_MAX_REGEXDEV_DEVS\n #define RTE_MAX_REGEXDEV_DEVS 32\n+#endif\n \n /* eventdev defines */\n+#ifndef RTE_EVENT_MAX_DEVS\n #define RTE_EVENT_MAX_DEVS 16\n+#endif\n+#ifndef RTE_EVENT_MAX_QUEUES_PER_DEV\n #define RTE_EVENT_MAX_QUEUES_PER_DEV 64\n+#endif\n+#ifndef RTE_EVENT_TIMER_ADAPTER_NUM_MAX\n #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32\n+#endif\n+#ifndef RTE_EVENT_ETH_INTR_RING_SIZE\n #define RTE_EVENT_ETH_INTR_RING_SIZE 1024\n+#endif\n+#ifndef RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE\n #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32\n+#endif\n+#ifndef RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE\n #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32\n+#endif\n \n /* rawdev defines */\n+#ifndef RTE_RAWDEV_MAX_DEVS\n #define RTE_RAWDEV_MAX_DEVS 64\n+#endif\n \n /* ip_fragmentation defines */\n+#ifndef RTE_LIBRTE_IP_FRAG_MAX_FRAG\n #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4\n+#endif\n // RTE_LIBRTE_IP_FRAG_TBL_STAT is not set\n \n /* rte_power defines */\n+#ifndef RTE_MAX_LCORE_FREQS\n #define RTE_MAX_LCORE_FREQS 64\n+#endif\n \n /* rte_sched defines */\n // RTE_SCHED_RED is not set\n // RTE_SCHED_COLLECT_STATS is not set\n // RTE_SCHED_SUBPORT_TC_OV is not set\n+#ifndef RTE_SCHED_PORT_N_GRINDERS\n #define RTE_SCHED_PORT_N_GRINDERS 8\n+#endif\n // RTE_SCHED_VECTOR is not set\n \n /* KNI defines */\n-#define RTE_KNI_PREEMPT_DEFAULT 1\n+#define RTE_KNI_PREEMPT_DEFAULT\n \n /* rte_graph defines */\n-#define RTE_GRAPH_BURST_SIZE 256\n #define RTE_LIBRTE_GRAPH_STATS 1\n+#ifndef RTE_GRAPH_BURST_SIZE\n+#define RTE_GRAPH_BURST_SIZE 256\n+#endif\n \n /****** driver defines ********/\n \n /* QuickAssist device */\n /* Max. number of QuickAssist devices which can be attached */\n+#ifndef RTE_PMD_QAT_MAX_PCI_DEVICES\n #define RTE_PMD_QAT_MAX_PCI_DEVICES 48\n+#endif\n+#ifndef RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS\n #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16\n+#endif\n+#ifndef RTE_PMD_QAT_COMP_IM_BUFFER_SIZE\n #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536\n+#endif\n \n /* virtio crypto defines */\n+#ifndef RTE_MAX_VIRTIO_CRYPTO\n #define RTE_MAX_VIRTIO_CRYPTO 32\n+#endif\n \n /* DPAA SEC max cryptodev devices*/\n-#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV\t4\n+#ifndef RTE_LIBRTE_DPAA_MAX_CRYPTODEV\n+#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4\n+#endif\n \n /* fm10k defines */\n-#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1\n+#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE\n \n /* i40e defines */\n-#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1\n+#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n // RTE_LIBRTE_I40E_16BYTE_RX_DESC is not set\n+#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF\n #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64\n+#endif\n+#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF\n #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4\n+#endif\n+#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM\n #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4\n+#endif\n \n /* Ring net PMD settings */\n+#ifndef RTE_PMD_RING_MAX_RX_RINGS\n #define RTE_PMD_RING_MAX_RX_RINGS 16\n+#endif\n+#ifndef RTE_PMD_RING_MAX_TX_RINGS\n #define RTE_PMD_RING_MAX_TX_RINGS 16\n+#endif\n \n /* QEDE PMD defines */\n+#ifndef RTE_LIBRTE_QEDE_FW\n #define RTE_LIBRTE_QEDE_FW \"\"\n+#endif\n \n #endif /* _RTE_CONFIG_H_ */\n",
    "prefixes": [
        "v2",
        "2/3"
    ]
}