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GET /api/patches/76399/?format=api
{ "id": 76399, "url": "http://patches.dpdk.org/api/patches/76399/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-17-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599128029-2092-17-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-17-git-send-email-michaelba@nvidia.com", "date": "2020-09-03T10:13:47", "name": "[v1,16/18] net/mlx5: share Rx hash queue code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "721d091342cce7d963d8c3d90ceb4c094db1e386", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-17-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 11924, "url": "http://patches.dpdk.org/api/series/11924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924", "date": "2020-09-03T10:13:31", "name": "mlx5 Rx DevX/Verbs separation", "version": 1, "mbox": "http://patches.dpdk.org/series/11924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76399/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76399/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B44F0A04DB;\n\tThu, 3 Sep 2020 12:17:29 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8165F1C1A9;\n\tThu, 3 Sep 2020 12:15:16 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 36BDF1C1A9\n for <dev@dpdk.org>; Thu, 3 Sep 2020 12:15:15 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:15:11 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP9E031645;\n Thu, 3 Sep 2020 13:15:11 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 3 Sep 2020 10:13:47 +0000", "Message-Id": "<1599128029-2092-17-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 16/18] net/mlx5: share Rx hash queue code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Move Rx hash queue object similar resources allocations from DevX and\nVerbs modules to a shared location.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_verbs.c | 58 ++++++-----------------------\n drivers/net/mlx5/mlx5.h | 6 +--\n drivers/net/mlx5/mlx5_devx.c | 73 ++++++++++---------------------------\n drivers/net/mlx5/mlx5_flow_dv.c | 2 +-\n drivers/net/mlx5/mlx5_flow_verbs.c | 4 +-\n drivers/net/mlx5/mlx5_rxq.c | 70 ++++++++++++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_rxtx.h | 8 ++--\n 7 files changed, 110 insertions(+), 111 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex be810b1..0745da9 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -503,45 +503,24 @@\n *\n * @param dev\n * Pointer to Ethernet device.\n- * @param rss_key\n- * RSS key for the Rx hash queue.\n- * @param rss_key_len\n- * RSS key length.\n- * @param hash_fields\n- * Verbs protocol hash field to make the RSS on.\n- * @param queues\n- * Queues entering in hash queue. In case of empty hash_fields only the\n- * first queue index will be taken for the indirection table.\n- * @param queues_n\n- * Number of queues.\n+ * @param hrxq\n+ * Pointer to Rx Hash queue.\n * @param tunnel\n * Tunnel type.\n *\n * @return\n- * The Verbs object initialized index, 0 otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static uint32_t\n-mlx5_ibv_hrxq_new(struct rte_eth_dev *dev,\n-\t\t const uint8_t *rss_key, uint32_t rss_key_len,\n-\t\t uint64_t hash_fields,\n-\t\t const uint16_t *queues, uint32_t queues_n,\n+static int\n+mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t int tunnel __rte_unused)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_hrxq *hrxq = NULL;\n-\tuint32_t hrxq_idx = 0;\n \tstruct ibv_qp *qp = NULL;\n-\tstruct mlx5_ind_table_obj *ind_tbl;\n+\tstruct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;\n+\tconst uint8_t *rss_key = hrxq->rss_key;\n+\tuint64_t hash_fields = hrxq->hash_fields;\n \tint err;\n-\n-\tqueues_n = hash_fields ? queues_n : 1;\n-\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n-\tif (!ind_tbl)\n-\t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n);\n-\tif (!ind_tbl) {\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n \tstruct mlx5dv_qp_init_attr qp_init_attr;\n \n@@ -571,7 +550,7 @@\n \t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n \t\t\t\t\t.rx_hash_function =\n \t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n-\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n+\t\t\t\t\t.rx_hash_key_len = hrxq->rss_key_len,\n \t\t\t\t\t.rx_hash_key =\n \t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n \t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n@@ -592,7 +571,7 @@\n \t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n \t\t\t\t\t.rx_hash_function =\n \t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n-\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n+\t\t\t\t\t.rx_hash_key_len = hrxq->rss_key_len,\n \t\t\t\t\t.rx_hash_key =\n \t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n \t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n@@ -605,10 +584,6 @@\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n-\tif (!hrxq)\n-\t\tgoto error;\n-\thrxq->ind_table = ind_tbl;\n \thrxq->qp = qp;\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \thrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);\n@@ -617,22 +592,13 @@\n \t\tgoto error;\n \t}\n #endif\n-\thrxq->rss_key_len = rss_key_len;\n-\thrxq->hash_fields = hash_fields;\n-\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n-\trte_atomic32_inc(&hrxq->refcnt);\n-\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n-\t\t hrxq, next);\n-\treturn hrxq_idx;\n+\treturn 0;\n error:\n \terr = rte_errno; /* Save rte_errno before cleanup. */\n-\tmlx5_ind_table_obj_release(dev, ind_tbl);\n \tif (qp)\n \t\tclaim_zero(mlx5_glue->destroy_qp(qp));\n-\tif (hrxq)\n-\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n \trte_errno = err; /* Restore rte_errno. */\n-\treturn 0;\n+\treturn -rte_errno;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 12017e8..579c961 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -745,10 +745,8 @@ struct mlx5_obj_ops {\n \tint (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,\n \t\t\t struct mlx5_ind_table_obj *ind_tbl);\n \tvoid (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);\n-\tuint32_t (*hrxq_new)(struct rte_eth_dev *dev, const uint8_t *rss_key,\n-\t\t\t uint32_t rss_key_len, uint64_t hash_fields,\n-\t\t\t const uint16_t *queues, uint32_t queues_n,\n-\t\t\t int tunnel __rte_unused);\n+\tint (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n+\t\t\tint tunnel __rte_unused);\n \tvoid (*hrxq_destroy)(struct mlx5_hrxq *hrxq);\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex ebc3929..cfb9264 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -679,54 +679,33 @@\n *\n * @param dev\n * Pointer to Ethernet device.\n- * @param rss_key\n- * RSS key for the Rx hash queue.\n- * @param rss_key_len\n- * RSS key length.\n- * @param hash_fields\n- * Verbs protocol hash field to make the RSS on.\n- * @param queues\n- * Queues entering in hash queue. In case of empty hash_fields only the\n- * first queue index will be taken for the indirection table.\n- * @param queues_n\n- * Number of queues.\n+ * @param hrxq\n+ * Pointer to Rx Hash queue.\n * @param tunnel\n * Tunnel type.\n *\n * @return\n- * The DevX object initialized index, 0 otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static uint32_t\n-mlx5_devx_hrxq_new(struct rte_eth_dev *dev,\n-\t\t const uint8_t *rss_key, uint32_t rss_key_len,\n-\t\t uint64_t hash_fields,\n-\t\t const uint16_t *queues, uint32_t queues_n,\n+static int\n+mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t int tunnel __rte_unused)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_hrxq *hrxq = NULL;\n-\tuint32_t hrxq_idx = 0;\n-\tstruct mlx5_ind_table_obj *ind_tbl;\n-\tstruct mlx5_devx_obj *tir = NULL;\n-\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];\n+\tstruct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]];\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct mlx5_devx_tir_attr tir_attr;\n-\tint err;\n-\tuint32_t i;\n+\tconst uint8_t *rss_key = hrxq->rss_key;\n+\tuint64_t hash_fields = hrxq->hash_fields;\n \tbool lro = true;\n+\tuint32_t i;\n+\tint err;\n \n-\tqueues_n = hash_fields ? queues_n : 1;\n-\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n-\tif (!ind_tbl)\n-\t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n);\n-\tif (!ind_tbl) {\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n \t/* Enable TIR LRO only if all the queues were configured for. */\n-\tfor (i = 0; i < queues_n; ++i) {\n-\t\tif (!(*priv->rxqs)[queues[i]]->lro) {\n+\tfor (i = 0; i < ind_tbl->queues_n; ++i) {\n+\t\tif (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) {\n \t\t\tlro = false;\n \t\t\tbreak;\n \t\t}\n@@ -776,18 +755,13 @@\n \t\ttir_attr.lro_enable_mask = MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |\n \t\t\t\t\t MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;\n \t}\n-\ttir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n-\tif (!tir) {\n+\thrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n+\tif (!hrxq->tir) {\n \t\tDRV_LOG(ERR, \"Port %u cannot create DevX TIR.\",\n \t\t\tdev->data->port_id);\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n-\tif (!hrxq)\n-\t\tgoto error;\n-\thrxq->ind_table = ind_tbl;\n-\thrxq->tir = tir;\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \thrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir\n \t\t\t\t\t\t\t (hrxq->tir->obj);\n@@ -796,22 +770,13 @@\n \t\tgoto error;\n \t}\n #endif\n-\thrxq->rss_key_len = rss_key_len;\n-\thrxq->hash_fields = hash_fields;\n-\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n-\trte_atomic32_inc(&hrxq->refcnt);\n-\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n-\t\t hrxq, next);\n-\treturn hrxq_idx;\n+\treturn 0;\n error:\n \terr = rte_errno; /* Save rte_errno before cleanup. */\n-\tmlx5_ind_table_obj_release(dev, ind_tbl);\n-\tif (tir)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(tir));\n-\tif (hrxq)\n-\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\tif (hrxq->tir)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(hrxq->tir));\n \trte_errno = err; /* Restore rte_errno. */\n-\treturn 0;\n+\treturn -rte_errno;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex fa41486..d636c57 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -8949,7 +8949,7 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t\t rss_desc->queue,\n \t\t\t\t\t\t rss_desc->queue_num);\n \t\t\tif (!hrxq_idx) {\n-\t\t\t\thrxq_idx = priv->obj_ops->hrxq_new\n+\t\t\t\thrxq_idx = mlx5_hrxq_new\n \t\t\t\t\t\t(dev, rss_desc->key,\n \t\t\t\t\t\t MLX5_RSS_HASH_KEY_LEN,\n \t\t\t\t\t\t dev_flow->hash_fields,\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex f8edae1..2ce91f7 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -1986,7 +1986,7 @@\n \t\t\t\t\t\t rss_desc->queue,\n \t\t\t\t\t\t rss_desc->queue_num);\n \t\t\tif (!hrxq_idx)\n-\t\t\t\thrxq_idx = priv->obj_ops->hrxq_new\n+\t\t\t\thrxq_idx = mlx5_hrxq_new\n \t\t\t\t\t\t(dev, rss_desc->key,\n \t\t\t\t\t\t MLX5_RSS_HASH_KEY_LEN,\n \t\t\t\t\t\t dev_flow->hash_fields,\n@@ -1995,7 +1995,7 @@\n \t\t\t\t\t\t !!(handle->layers &\n \t\t\t\t\t\t MLX5_FLOW_LAYER_TUNNEL));\n \t\t\thrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],\n-\t\t\t\t\t hrxq_idx);\n+\t\t\t\t\t hrxq_idx);\n \t\t\tif (!hrxq) {\n \t\t\t\trte_flow_error_set\n \t\t\t\t\t(error, rte_errno,\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex c353139..234ee28 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1811,7 +1811,7 @@ struct mlx5_ind_table_obj *\n * @return\n * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set.\n */\n-struct mlx5_ind_table_obj *\n+static struct mlx5_ind_table_obj *\n mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n \t\t uint32_t queues_n)\n {\n@@ -1938,6 +1938,74 @@ struct mlx5_ind_table_obj *\n }\n \n /**\n+ * Create an Rx Hash queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param rss_key\n+ * RSS key for the Rx hash queue.\n+ * @param rss_key_len\n+ * RSS key length.\n+ * @param hash_fields\n+ * Verbs protocol hash field to make the RSS on.\n+ * @param queues\n+ * Queues entering in hash queue. In case of empty hash_fields only the\n+ * first queue index will be taken for the indirection table.\n+ * @param queues_n\n+ * Number of queues.\n+ * @param tunnel\n+ * Tunnel type.\n+ *\n+ * @return\n+ * The DevX object initialized index, 0 otherwise and rte_errno is set.\n+ */\n+uint32_t\n+mlx5_hrxq_new(struct rte_eth_dev *dev,\n+\t const uint8_t *rss_key, uint32_t rss_key_len,\n+\t uint64_t hash_fields,\n+\t const uint16_t *queues, uint32_t queues_n,\n+\t int tunnel __rte_unused)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hrxq *hrxq = NULL;\n+\tuint32_t hrxq_idx = 0;\n+\tstruct mlx5_ind_table_obj *ind_tbl;\n+\tint ret;\n+\n+\tqueues_n = hash_fields ? queues_n : 1;\n+\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n+\tif (!ind_tbl)\n+\t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n);\n+\tif (!ind_tbl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn 0;\n+\t}\n+\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n+\tif (!hrxq)\n+\t\tgoto error;\n+\thrxq->ind_table = ind_tbl;\n+\thrxq->rss_key_len = rss_key_len;\n+\thrxq->hash_fields = hash_fields;\n+\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n+\tret = priv->obj_ops->hrxq_new(dev, hrxq, tunnel);\n+\tif (ret < 0) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\trte_atomic32_inc(&hrxq->refcnt);\n+\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n+\t\t hrxq, next);\n+\treturn hrxq_idx;\n+error:\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tmlx5_ind_table_obj_release(dev, ind_tbl);\n+\tif (hrxq)\n+\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\trte_errno = ret; /* Restore rte_errno. */\n+\treturn 0;\n+}\n+\n+/**\n * Verify the Rx Queue list is empty\n *\n * @param dev\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 237344f..164f36b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -365,14 +365,16 @@ struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new\n int mlx5_rxq_verify(struct rte_eth_dev *dev);\n int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);\n int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);\n-struct mlx5_ind_table_obj *mlx5_ind_table_obj_new(struct rte_eth_dev *dev,\n-\t\t\t\t\t\t const uint16_t *queues,\n-\t\t\t\t\t\t uint32_t queues_n);\n struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,\n \t\t\t\t\t\t const uint16_t *queues,\n \t\t\t\t\t\t uint32_t queues_n);\n int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_ind_table_obj *ind_tbl);\n+uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,\n+\t\t const uint8_t *rss_key, uint32_t rss_key_len,\n+\t\t uint64_t hash_fields,\n+\t\t const uint16_t *queues, uint32_t queues_n,\n+\t\t int tunnel __rte_unused);\n uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,\n \t\t const uint8_t *rss_key, uint32_t rss_key_len,\n \t\t uint64_t hash_fields,\n", "prefixes": [ "v1", "16/18" ] }