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{
    "id": 76396,
    "url": "http://patches.dpdk.org/api/patches/76396/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-14-git-send-email-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599128029-2092-14-git-send-email-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-14-git-send-email-michaelba@nvidia.com",
    "date": "2020-09-03T10:13:44",
    "name": "[v1,13/18] net/mlx5: separate Rx hash queue creation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "ab67f8f38947a620935c063d34a05c4823e79c5b",
    "submitter": {
        "id": 1949,
        "url": "http://patches.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-14-git-send-email-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 11924,
            "url": "http://patches.dpdk.org/api/series/11924/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924",
            "date": "2020-09-03T10:13:31",
            "name": "mlx5 Rx DevX/Verbs separation",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/11924/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/76396/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/76396/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC870A04DB;\n\tThu,  3 Sep 2020 12:16:54 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 837141C1A2;\n\tThu,  3 Sep 2020 12:15:07 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 226E01C0D1\n for <dev@dpdk.org>; Thu,  3 Sep 2020 12:15:05 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:15:03 +0300",
            "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP9B031645;\n Thu, 3 Sep 2020 13:15:03 +0300"
        ],
        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Date": "Thu,  3 Sep 2020 10:13:44 +0000",
        "Message-Id": "<1599128029-2092-14-git-send-email-michaelba@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>",
        "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v1 13/18] net/mlx5: separate Rx hash queue\n\tcreation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Separate Rx hash queue creation into both Verbs and DevX modules.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_verbs.c | 152 ++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h             |  23 ++++\n drivers/net/mlx5/mlx5_devx.c        | 155 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_dv.c     |  14 +--\n drivers/net/mlx5/mlx5_flow_verbs.c  |  15 +--\n drivers/net/mlx5/mlx5_rxq.c         | 243 +-----------------------------------\n drivers/net/mlx5/mlx5_rxtx.h        |  28 +----\n 7 files changed, 353 insertions(+), 277 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex d36d915..d92dd48 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -517,6 +517,156 @@\n \tclaim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));\n }\n \n+/**\n+ * Create an Rx Hash queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param rss_key\n+ *   RSS key for the Rx hash queue.\n+ * @param rss_key_len\n+ *   RSS key length.\n+ * @param hash_fields\n+ *   Verbs protocol hash field to make the RSS on.\n+ * @param queues\n+ *   Queues entering in hash queue. In case of empty hash_fields only the\n+ *   first queue index will be taken for the indirection table.\n+ * @param queues_n\n+ *   Number of queues.\n+ * @param tunnel\n+ *   Tunnel type.\n+ *\n+ * @return\n+ *   The Verbs object initialized index, 0 otherwise and rte_errno is set.\n+ */\n+static uint32_t\n+mlx5_ibv_hrxq_new(struct rte_eth_dev *dev,\n+\t\t  const uint8_t *rss_key, uint32_t rss_key_len,\n+\t\t  uint64_t hash_fields,\n+\t\t  const uint16_t *queues, uint32_t queues_n,\n+\t\t  int tunnel __rte_unused)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hrxq *hrxq = NULL;\n+\tuint32_t hrxq_idx = 0;\n+\tstruct ibv_qp *qp = NULL;\n+\tstruct mlx5_ind_table_obj *ind_tbl;\n+\tint err;\n+\n+\tqueues_n = hash_fields ? queues_n : 1;\n+\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n+\tif (!ind_tbl)\n+\t\tind_tbl = priv->obj_ops->ind_table_obj_new(dev, queues,\n+\t\t\t\t\t\t\t   queues_n);\n+\tif (!ind_tbl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn 0;\n+\t}\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\tstruct mlx5dv_qp_init_attr qp_init_attr;\n+\n+\tmemset(&qp_init_attr, 0, sizeof(qp_init_attr));\n+\tif (tunnel) {\n+\t\tqp_init_attr.comp_mask =\n+\t\t\t\t       MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n+\t\tqp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;\n+\t}\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tif (dev->data->dev_conf.lpbk_mode) {\n+\t\t/* Allow packet sent from NIC loop back w/o source MAC check. */\n+\t\tqp_init_attr.comp_mask |=\n+\t\t\t\tMLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n+\t\tqp_init_attr.create_flags |=\n+\t\t\t\tMLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;\n+\t}\n+#endif\n+\tqp = mlx5_glue->dv_create_qp\n+\t\t\t(priv->sh->ctx,\n+\t\t\t &(struct ibv_qp_init_attr_ex){\n+\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t\t.comp_mask =\n+\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n+\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n+\t\t\t\t\t.rx_hash_function =\n+\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n+\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n+\t\t\t\t\t.rx_hash_key =\n+\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n+\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n+\t\t\t\t},\n+\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n+\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t  },\n+\t\t\t  &qp_init_attr);\n+#else\n+\tqp = mlx5_glue->create_qp_ex\n+\t\t\t(priv->sh->ctx,\n+\t\t\t &(struct ibv_qp_init_attr_ex){\n+\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t\t.comp_mask =\n+\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n+\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n+\t\t\t\t\t.rx_hash_function =\n+\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n+\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n+\t\t\t\t\t.rx_hash_key =\n+\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n+\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n+\t\t\t\t},\n+\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n+\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t });\n+#endif\n+\tif (!qp) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n+\tif (!hrxq)\n+\t\tgoto error;\n+\thrxq->ind_table = ind_tbl;\n+\thrxq->qp = qp;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\thrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);\n+\tif (!hrxq->action) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+#endif\n+\thrxq->rss_key_len = rss_key_len;\n+\thrxq->hash_fields = hash_fields;\n+\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n+\trte_atomic32_inc(&hrxq->refcnt);\n+\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n+\t\t     hrxq, next);\n+\treturn hrxq_idx;\n+error:\n+\terr = rte_errno; /* Save rte_errno before cleanup. */\n+\tmlx5_ind_table_obj_release(dev, ind_tbl);\n+\tif (qp)\n+\t\tclaim_zero(mlx5_glue->destroy_qp(qp));\n+\tif (hrxq)\n+\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\trte_errno = err; /* Restore rte_errno. */\n+\treturn 0;\n+}\n+\n+/**\n+ * Destroy a Verbs queue pair.\n+ *\n+ * @param hrxq\n+ *   Hash Rx queue to release its qp.\n+ */\n+static void\n+mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)\n+{\n+\tclaim_zero(mlx5_glue->destroy_qp(hrxq->qp));\n+}\n+\n struct mlx5_obj_ops ibv_obj_ops = {\n \t.rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,\n \t.rxq_obj_new = mlx5_rxq_ibv_obj_new,\n@@ -525,4 +675,6 @@ struct mlx5_obj_ops ibv_obj_ops = {\n \t.rxq_obj_release = mlx5_rxq_ibv_obj_release,\n \t.ind_table_obj_new = mlx5_ibv_ind_table_obj_new,\n \t.ind_table_obj_destroy = mlx5_ibv_ind_table_obj_destroy,\n+\t.hrxq_new = mlx5_ibv_hrxq_new,\n+\t.hrxq_destroy = mlx5_ibv_qp_destroy,\n };\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c151e64..9fc4639 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -723,6 +723,24 @@ struct mlx5_ind_table_obj {\n \tuint16_t queues[]; /**< Queue list. */\n };\n \n+/* Hash Rx queue. */\n+struct mlx5_hrxq {\n+\tILIST_ENTRY(uint32_t)next; /* Index to the next element. */\n+\trte_atomic32_t refcnt; /* Reference counter. */\n+\tstruct mlx5_ind_table_obj *ind_table; /* Indirection table. */\n+\tRTE_STD_C11\n+\tunion {\n+\t\tvoid *qp; /* Verbs queue pair. */\n+\t\tstruct mlx5_devx_obj *tir; /* DevX TIR object. */\n+\t};\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tvoid *action; /* DV QP action pointer. */\n+#endif\n+\tuint64_t hash_fields; /* Verbs Hash fields. */\n+\tuint32_t rss_key_len; /* Hash key length in bytes. */\n+\tuint8_t rss_key[]; /* Hash key. */\n+};\n+\n /* HW objects operations structure. */\n struct mlx5_obj_ops {\n \tint (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);\n@@ -734,6 +752,11 @@ struct mlx5_obj_ops {\n \t\t\t\t\t\t\tconst uint16_t *queues,\n \t\t\t\t\t\t\tuint32_t queues_n);\n \tvoid (*ind_table_obj_destroy)(struct mlx5_ind_table_obj *ind_tbl);\n+\tuint32_t (*hrxq_new)(struct rte_eth_dev *dev, const uint8_t *rss_key,\n+\t\t\t     uint32_t rss_key_len, uint64_t hash_fields,\n+\t\t\t     const uint16_t *queues, uint32_t queues_n,\n+\t\t\t     int tunnel __rte_unused);\n+\tvoid (*hrxq_destroy)(struct mlx5_hrxq *hrxq);\n };\n \n struct mlx5_priv {\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex aab5e50..b1b3037 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -694,6 +694,159 @@\n \tclaim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));\n }\n \n+/**\n+ * Create an Rx Hash queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param rss_key\n+ *   RSS key for the Rx hash queue.\n+ * @param rss_key_len\n+ *   RSS key length.\n+ * @param hash_fields\n+ *   Verbs protocol hash field to make the RSS on.\n+ * @param queues\n+ *   Queues entering in hash queue. In case of empty hash_fields only the\n+ *   first queue index will be taken for the indirection table.\n+ * @param queues_n\n+ *   Number of queues.\n+ * @param tunnel\n+ *   Tunnel type.\n+ *\n+ * @return\n+ *   The DevX object initialized index, 0 otherwise and rte_errno is set.\n+ */\n+static uint32_t\n+mlx5_devx_hrxq_new(struct rte_eth_dev *dev,\n+\t\t   const uint8_t *rss_key, uint32_t rss_key_len,\n+\t\t   uint64_t hash_fields,\n+\t\t   const uint16_t *queues, uint32_t queues_n,\n+\t\t   int tunnel __rte_unused)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hrxq *hrxq = NULL;\n+\tuint32_t hrxq_idx = 0;\n+\tstruct mlx5_ind_table_obj *ind_tbl;\n+\tstruct mlx5_devx_obj *tir = NULL;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_devx_tir_attr tir_attr;\n+\tint err;\n+\tuint32_t i;\n+\tbool lro = true;\n+\n+\tqueues_n = hash_fields ? queues_n : 1;\n+\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n+\tif (!ind_tbl)\n+\t\tind_tbl = priv->obj_ops->ind_table_obj_new(dev, queues,\n+\t\t\t\t\t\t\t   queues_n);\n+\tif (!ind_tbl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn 0;\n+\t}\n+\t/* Enable TIR LRO only if all the queues were configured for. */\n+\tfor (i = 0; i < queues_n; ++i) {\n+\t\tif (!(*priv->rxqs)[queues[i]]->lro) {\n+\t\t\tlro = false;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tmemset(&tir_attr, 0, sizeof(tir_attr));\n+\ttir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;\n+\ttir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;\n+\ttir_attr.tunneled_offload_en = !!tunnel;\n+\t/* If needed, translate hash_fields bitmap to PRM format. */\n+\tif (hash_fields) {\n+\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select = NULL;\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\t\trx_hash_field_select = hash_fields & IBV_RX_HASH_INNER ?\n+\t\t\t\t       &tir_attr.rx_hash_field_selector_inner :\n+\t\t\t\t       &tir_attr.rx_hash_field_selector_outer;\n+#else\n+\t\trx_hash_field_select = &tir_attr.rx_hash_field_selector_outer;\n+#endif\n+\t\t/* 1 bit: 0: IPv4, 1: IPv6. */\n+\t\trx_hash_field_select->l3_prot_type =\n+\t\t\t\t\t!!(hash_fields & MLX5_IPV6_IBV_RX_HASH);\n+\t\t/* 1 bit: 0: TCP, 1: UDP. */\n+\t\trx_hash_field_select->l4_prot_type =\n+\t\t\t\t\t !!(hash_fields & MLX5_UDP_IBV_RX_HASH);\n+\t\t/* Bitmask which sets which fields to use in RX Hash. */\n+\t\trx_hash_field_select->selected_fields =\n+\t\t\t((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<\n+\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |\n+\t\t\t(!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<\n+\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |\n+\t\t\t(!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<\n+\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |\n+\t\t\t(!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<\n+\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;\n+\t}\n+\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)\n+\t\ttir_attr.transport_domain = priv->sh->td->id;\n+\telse\n+\t\ttir_attr.transport_domain = priv->sh->tdn;\n+\tmemcpy(tir_attr.rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);\n+\ttir_attr.indirect_table = ind_tbl->rqt->id;\n+\tif (dev->data->dev_conf.lpbk_mode)\n+\t\ttir_attr.self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n+\tif (lro) {\n+\t\ttir_attr.lro_timeout_period_usecs = priv->config.lro.timeout;\n+\t\ttir_attr.lro_max_msg_sz = priv->max_lro_msg_size;\n+\t\ttir_attr.lro_enable_mask = MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |\n+\t\t\t\t\t   MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;\n+\t}\n+\ttir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n+\tif (!tir) {\n+\t\tDRV_LOG(ERR, \"Port %u cannot create DevX TIR.\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n+\tif (!hrxq)\n+\t\tgoto error;\n+\thrxq->ind_table = ind_tbl;\n+\thrxq->tir = tir;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\thrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir\n+\t\t\t\t\t\t\t       (hrxq->tir->obj);\n+\tif (!hrxq->action) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+#endif\n+\thrxq->rss_key_len = rss_key_len;\n+\thrxq->hash_fields = hash_fields;\n+\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n+\trte_atomic32_inc(&hrxq->refcnt);\n+\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n+\t\t     hrxq, next);\n+\treturn hrxq_idx;\n+error:\n+\terr = rte_errno; /* Save rte_errno before cleanup. */\n+\tmlx5_ind_table_obj_release(dev, ind_tbl);\n+\tif (tir)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(tir));\n+\tif (hrxq)\n+\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\trte_errno = err; /* Restore rte_errno. */\n+\treturn 0;\n+}\n+\n+/**\n+ * Destroy a DevX TIR object.\n+ *\n+ * @param hrxq\n+ *   Hash Rx queue to release its tir.\n+ */\n+static void\n+mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)\n+{\n+\tclaim_zero(mlx5_devx_cmd_destroy(hrxq->tir));\n+}\n+\n struct mlx5_obj_ops devx_obj_ops = {\n \t.rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,\n \t.rxq_obj_new = mlx5_rxq_devx_obj_new,\n@@ -702,4 +855,6 @@ struct mlx5_obj_ops devx_obj_ops = {\n \t.rxq_obj_release = mlx5_rxq_devx_obj_release,\n \t.ind_table_obj_new = mlx5_devx_ind_table_obj_new,\n \t.ind_table_obj_destroy = mlx5_devx_ind_table_obj_destroy,\n+\t.hrxq_new = mlx5_devx_hrxq_new,\n+\t.hrxq_destroy = mlx5_devx_tir_destroy,\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 58358ce..fa41486 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -8949,14 +8949,14 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t\t rss_desc->queue,\n \t\t\t\t\t\t rss_desc->queue_num);\n \t\t\tif (!hrxq_idx) {\n-\t\t\t\thrxq_idx = mlx5_hrxq_new\n+\t\t\t\thrxq_idx = priv->obj_ops->hrxq_new\n \t\t\t\t\t\t(dev, rss_desc->key,\n-\t\t\t\t\t\tMLX5_RSS_HASH_KEY_LEN,\n-\t\t\t\t\t\tdev_flow->hash_fields,\n-\t\t\t\t\t\trss_desc->queue,\n-\t\t\t\t\t\trss_desc->queue_num,\n-\t\t\t\t\t\t!!(dh->layers &\n-\t\t\t\t\t\tMLX5_FLOW_LAYER_TUNNEL));\n+\t\t\t\t\t\t MLX5_RSS_HASH_KEY_LEN,\n+\t\t\t\t\t\t dev_flow->hash_fields,\n+\t\t\t\t\t\t rss_desc->queue,\n+\t\t\t\t\t\t rss_desc->queue_num,\n+\t\t\t\t\t\t !!(dh->layers &\n+\t\t\t\t\t\t MLX5_FLOW_LAYER_TUNNEL));\n \t\t\t}\n \t\t\thrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],\n \t\t\t\t\t      hrxq_idx);\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex 80c549a..f8edae1 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -1986,13 +1986,14 @@\n \t\t\t\t\t\t rss_desc->queue,\n \t\t\t\t\t\t rss_desc->queue_num);\n \t\t\tif (!hrxq_idx)\n-\t\t\t\thrxq_idx = mlx5_hrxq_new(dev, rss_desc->key,\n-\t\t\t\t\t\tMLX5_RSS_HASH_KEY_LEN,\n-\t\t\t\t\t\tdev_flow->hash_fields,\n-\t\t\t\t\t\trss_desc->queue,\n-\t\t\t\t\t\trss_desc->queue_num,\n-\t\t\t\t\t\t!!(handle->layers &\n-\t\t\t\t\t\tMLX5_FLOW_LAYER_TUNNEL));\n+\t\t\t\thrxq_idx = priv->obj_ops->hrxq_new\n+\t\t\t\t\t\t(dev, rss_desc->key,\n+\t\t\t\t\t\t MLX5_RSS_HASH_KEY_LEN,\n+\t\t\t\t\t\t dev_flow->hash_fields,\n+\t\t\t\t\t\t rss_desc->queue,\n+\t\t\t\t\t\t rss_desc->queue_num,\n+\t\t\t\t\t\t !!(handle->layers &\n+\t\t\t\t\t\t MLX5_FLOW_LAYER_TUNNEL));\n \t\t\thrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],\n \t\t\t\t\t hrxq_idx);\n \t\t\tif (!hrxq) {\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex aa39892..d84dfe1 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -20,7 +20,6 @@\n #include <rte_eal_paging.h>\n \n #include <mlx5_glue.h>\n-#include <mlx5_devx_cmds.h>\n #include <mlx5_malloc.h>\n \n #include \"mlx5_defs.h\"\n@@ -28,7 +27,6 @@\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_utils.h\"\n #include \"mlx5_autoconf.h\"\n-#include \"mlx5_flow.h\"\n \n \n /* Default RSS hash key also used for ConnectX-3. */\n@@ -1721,7 +1719,7 @@ enum mlx5_rxq_type\n  * @return\n  *   An indirection table if found.\n  */\n-static struct mlx5_ind_table_obj *\n+struct mlx5_ind_table_obj *\n mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,\n \t\t       uint32_t queues_n)\n {\n@@ -1756,7 +1754,7 @@ enum mlx5_rxq_type\n  * @return\n  *   1 while a reference on it exists, 0 when freed.\n  */\n-static int\n+int\n mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n \t\t\t   struct mlx5_ind_table_obj *ind_tbl)\n {\n@@ -1801,238 +1799,6 @@ enum mlx5_rxq_type\n }\n \n /**\n- * Create an Rx Hash queue.\n- *\n- * @param dev\n- *   Pointer to Ethernet device.\n- * @param rss_key\n- *   RSS key for the Rx hash queue.\n- * @param rss_key_len\n- *   RSS key length.\n- * @param hash_fields\n- *   Verbs protocol hash field to make the RSS on.\n- * @param queues\n- *   Queues entering in hash queue. In case of empty hash_fields only the\n- *   first queue index will be taken for the indirection table.\n- * @param queues_n\n- *   Number of queues.\n- * @param tunnel\n- *   Tunnel type.\n- *\n- * @return\n- *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.\n- */\n-uint32_t\n-mlx5_hrxq_new(struct rte_eth_dev *dev,\n-\t      const uint8_t *rss_key, uint32_t rss_key_len,\n-\t      uint64_t hash_fields,\n-\t      const uint16_t *queues, uint32_t queues_n,\n-\t      int tunnel __rte_unused)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_hrxq *hrxq = NULL;\n-\tuint32_t hrxq_idx = 0;\n-\tstruct ibv_qp *qp = NULL;\n-\tstruct mlx5_ind_table_obj *ind_tbl;\n-\tint err;\n-\tstruct mlx5_devx_obj *tir = NULL;\n-\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\n-\tqueues_n = hash_fields ? queues_n : 1;\n-\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n-\tif (!ind_tbl)\n-\t\tind_tbl = priv->obj_ops->ind_table_obj_new(dev, queues,\n-\t\t\t\t\t\t\t   queues_n);\n-\tif (!ind_tbl) {\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n-\tif (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {\n-#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n-\t\tstruct mlx5dv_qp_init_attr qp_init_attr;\n-\n-\t\tmemset(&qp_init_attr, 0, sizeof(qp_init_attr));\n-\t\tif (tunnel) {\n-\t\t\tqp_init_attr.comp_mask =\n-\t\t\t\tMLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n-\t\t\tqp_init_attr.create_flags =\n-\t\t\t\tMLX5DV_QP_CREATE_TUNNEL_OFFLOADS;\n-\t\t}\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\t\tif (dev->data->dev_conf.lpbk_mode) {\n-\t\t\t/*\n-\t\t\t * Allow packet sent from NIC loop back\n-\t\t\t * w/o source MAC check.\n-\t\t\t */\n-\t\t\tqp_init_attr.comp_mask |=\n-\t\t\t\tMLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n-\t\t\tqp_init_attr.create_flags |=\n-\t\t\t\tMLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;\n-\t\t}\n-#endif\n-\t\tqp = mlx5_glue->dv_create_qp\n-\t\t\t(priv->sh->ctx,\n-\t\t\t &(struct ibv_qp_init_attr_ex){\n-\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n-\t\t\t\t.comp_mask =\n-\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n-\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n-\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n-\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n-\t\t\t\t\t.rx_hash_function =\n-\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n-\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n-\t\t\t\t\t.rx_hash_key =\n-\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n-\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n-\t\t\t\t},\n-\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n-\t\t\t\t.pd = priv->sh->pd,\n-\t\t\t  },\n-\t\t\t  &qp_init_attr);\n-#else\n-\t\tqp = mlx5_glue->create_qp_ex\n-\t\t\t(priv->sh->ctx,\n-\t\t\t &(struct ibv_qp_init_attr_ex){\n-\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n-\t\t\t\t.comp_mask =\n-\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n-\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n-\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n-\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n-\t\t\t\t\t.rx_hash_function =\n-\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n-\t\t\t\t\t.rx_hash_key_len = rss_key_len,\n-\t\t\t\t\t.rx_hash_key =\n-\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n-\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n-\t\t\t\t},\n-\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n-\t\t\t\t.pd = priv->sh->pd,\n-\t\t\t });\n-#endif\n-\t\tif (!qp) {\n-\t\t\trte_errno = errno;\n-\t\t\tgoto error;\n-\t\t}\n-\t} else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */\n-\t\tstruct mlx5_devx_tir_attr tir_attr;\n-\t\tuint32_t i;\n-\t\tuint32_t lro = 1;\n-\n-\t\t/* Enable TIR LRO only if all the queues were configured for. */\n-\t\tfor (i = 0; i < queues_n; ++i) {\n-\t\t\tif (!(*priv->rxqs)[queues[i]]->lro) {\n-\t\t\t\tlro = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t\tmemset(&tir_attr, 0, sizeof(tir_attr));\n-\t\ttir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;\n-\t\ttir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;\n-\t\ttir_attr.tunneled_offload_en = !!tunnel;\n-\t\t/* If needed, translate hash_fields bitmap to PRM format. */\n-\t\tif (hash_fields) {\n-#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n-\t\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n-\t\t\t\t\thash_fields & IBV_RX_HASH_INNER ?\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_inner :\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_outer;\n-#else\n-\t\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_outer;\n-#endif\n-\t\t\t/* 1 bit: 0: IPv4, 1: IPv6. */\n-\t\t\trx_hash_field_select->l3_prot_type =\n-\t\t\t\t!!(hash_fields & MLX5_IPV6_IBV_RX_HASH);\n-\t\t\t/* 1 bit: 0: TCP, 1: UDP. */\n-\t\t\trx_hash_field_select->l4_prot_type =\n-\t\t\t\t!!(hash_fields & MLX5_UDP_IBV_RX_HASH);\n-\t\t\t/* Bitmask which sets which fields to use in RX Hash. */\n-\t\t\trx_hash_field_select->selected_fields =\n-\t\t\t((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |\n-\t\t\t(!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |\n-\t\t\t(!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |\n-\t\t\t(!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;\n-\t\t}\n-\t\tif (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)\n-\t\t\ttir_attr.transport_domain = priv->sh->td->id;\n-\t\telse\n-\t\t\ttir_attr.transport_domain = priv->sh->tdn;\n-\t\tmemcpy(tir_attr.rx_hash_toeplitz_key, rss_key,\n-\t\t       MLX5_RSS_HASH_KEY_LEN);\n-\t\ttir_attr.indirect_table = ind_tbl->rqt->id;\n-\t\tif (dev->data->dev_conf.lpbk_mode)\n-\t\t\ttir_attr.self_lb_block =\n-\t\t\t\t\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n-\t\tif (lro) {\n-\t\t\ttir_attr.lro_timeout_period_usecs =\n-\t\t\t\t\tpriv->config.lro.timeout;\n-\t\t\ttir_attr.lro_max_msg_sz = priv->max_lro_msg_size;\n-\t\t\ttir_attr.lro_enable_mask =\n-\t\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |\n-\t\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;\n-\t\t}\n-\t\ttir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n-\t\tif (!tir) {\n-\t\t\tDRV_LOG(ERR, \"port %u cannot create DevX TIR\",\n-\t\t\t\tdev->data->port_id);\n-\t\t\trte_errno = errno;\n-\t\t\tgoto error;\n-\t\t}\n-\t}\n-\thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n-\tif (!hrxq)\n-\t\tgoto error;\n-\thrxq->ind_table = ind_tbl;\n-\tif (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {\n-\t\thrxq->qp = qp;\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\t\thrxq->action =\n-\t\t\tmlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);\n-\t\tif (!hrxq->action) {\n-\t\t\trte_errno = errno;\n-\t\t\tgoto error;\n-\t\t}\n-#endif\n-\t} else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */\n-\t\thrxq->tir = tir;\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\t\thrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir\n-\t\t\t\t\t\t\t(hrxq->tir->obj);\n-\t\tif (!hrxq->action) {\n-\t\t\trte_errno = errno;\n-\t\t\tgoto error;\n-\t\t}\n-#endif\n-\t}\n-\thrxq->rss_key_len = rss_key_len;\n-\thrxq->hash_fields = hash_fields;\n-\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n-\trte_atomic32_inc(&hrxq->refcnt);\n-\tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n-\t\t     hrxq, next);\n-\treturn hrxq_idx;\n-error:\n-\terr = rte_errno; /* Save rte_errno before cleanup. */\n-\tmlx5_ind_table_obj_release(dev, ind_tbl);\n-\tif (qp)\n-\t\tclaim_zero(mlx5_glue->destroy_qp(qp));\n-\telse if (tir)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(tir));\n-\tif (hrxq)\n-\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n-\trte_errno = err; /* Restore rte_errno. */\n-\treturn 0;\n-}\n-\n-/**\n  * Get an Rx Hash queue.\n  *\n  * @param dev\n@@ -2106,10 +1872,7 @@ enum mlx5_rxq_type\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t\tmlx5_glue->destroy_flow_action(hrxq->action);\n #endif\n-\t\tif (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)\n-\t\t\tclaim_zero(mlx5_glue->destroy_qp(hrxq->qp));\n-\t\telse /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */\n-\t\t\tclaim_zero(mlx5_devx_cmd_destroy(hrxq->tir));\n+\t\tpriv->obj_ops->hrxq_destroy(hrxq);\n \t\tmlx5_ind_table_obj_release(dev, hrxq->ind_table);\n \t\tILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,\n \t\t\t     hrxq_idx, hrxq, next);\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 7878c81..14a3535 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -186,24 +186,6 @@ struct mlx5_rxq_ctrl {\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n };\n \n-/* Hash Rx queue. */\n-struct mlx5_hrxq {\n-\tILIST_ENTRY(uint32_t)next; /* Index to the next element. */\n-\trte_atomic32_t refcnt; /* Reference counter. */\n-\tstruct mlx5_ind_table_obj *ind_table; /* Indirection table. */\n-\tRTE_STD_C11\n-\tunion {\n-\t\tvoid *qp; /* Verbs queue pair. */\n-\t\tstruct mlx5_devx_obj *tir; /* DevX TIR object. */\n-\t};\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tvoid *action; /* DV QP action pointer. */\n-#endif\n-\tuint64_t hash_fields; /* Verbs Hash fields. */\n-\tuint32_t rss_key_len; /* Hash key length in bytes. */\n-\tuint8_t rss_key[]; /* Hash key. */\n-};\n-\n /* TX queue send local data. */\n __extension__\n struct mlx5_txq_local {\n@@ -383,11 +365,11 @@ struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new\n int mlx5_rxq_verify(struct rte_eth_dev *dev);\n int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);\n int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);\n-uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,\n-\t\t       const uint8_t *rss_key, uint32_t rss_key_len,\n-\t\t       uint64_t hash_fields,\n-\t\t       const uint16_t *queues, uint32_t queues_n,\n-\t\t       int tunnel __rte_unused);\n+struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,\n+\t\t\t\t\t\t  const uint16_t *queues,\n+\t\t\t\t\t\t  uint32_t queues_n);\n+int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n+\t\t\t       struct mlx5_ind_table_obj *ind_tbl);\n uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,\n \t\t       const uint8_t *rss_key, uint32_t rss_key_len,\n \t\t       uint64_t hash_fields,\n",
    "prefixes": [
        "v1",
        "13/18"
    ]
}