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GET /api/patches/76391/?format=api
{ "id": 76391, "url": "http://patches.dpdk.org/api/patches/76391/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-9-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599128029-2092-9-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-9-git-send-email-michaelba@nvidia.com", "date": "2020-09-03T10:13:39", "name": "[v1,08/18] net/mlx5: rearrange the creation of RQ and CQ resources", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7a7a0ce851863c2b156ccdff567aaf2f3e439974", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-9-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 11924, "url": "http://patches.dpdk.org/api/series/11924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924", "date": "2020-09-03T10:13:31", "name": "mlx5 Rx DevX/Verbs separation", "version": 1, "mbox": "http://patches.dpdk.org/series/11924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76391/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76391/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8C6A8A04DB;\n\tThu, 3 Sep 2020 12:16:03 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C62FF1C132;\n\tThu, 3 Sep 2020 12:14:55 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 0746C1C128\n for <dev@dpdk.org>; Thu, 3 Sep 2020 12:14:54 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:14:49 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP96031645;\n Thu, 3 Sep 2020 13:14:49 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 3 Sep 2020 10:13:39 +0000", "Message-Id": "<1599128029-2092-9-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 08/18] net/mlx5: rearrange the creation of RQ\n\tand CQ resources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rearrangement of RQ and CQ resource handling for DevX Rx queue:\n1. Rename the allocation function so that it is understood that it\nallocates all resources and not just the CQ or RQ.\n2. Move the allocation and release of the doorbell into creation and\nrelease functions.\n3. Reduce the number of arguments that the creation functions receive.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_devx.c | 156 ++++++++++++++++++++++++-------------------\n drivers/net/mlx5/mlx5_rxtx.h | 4 +-\n 2 files changed, 89 insertions(+), 71 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 5b1cf14..5a3ac49 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -22,13 +22,37 @@\n #include \"mlx5_utils.h\"\n #include \"mlx5_devx.h\"\n \n+\n+/**\n+ * Calculate the number of CQEs in CQ for the Rx queue.\n+ *\n+ * @param rxq_data\n+ * Pointer to receive queue structure.\n+ *\n+ * @return\n+ * Number of CQEs in CQ.\n+ */\n+static unsigned int\n+mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data)\n+{\n+\tunsigned int cqe_n;\n+\tunsigned int wqe_n = 1 << rxq_data->elts_n;\n+\n+\tif (mlx5_rxq_mprq_enabled(rxq_data))\n+\t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n+\telse\n+\t\tcqe_n = wqe_n - 1;\n+\treturn cqe_n;\n+}\n+\n /**\n * Modify RQ vlan stripping offload\n *\n * @param rxq_obj\n * Rx queue object.\n *\n- * @return 0 on success, non-0 otherwise\n+ * @return\n+ * 0 on success, non-0 otherwise\n */\n static int\n mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)\n@@ -52,6 +76,8 @@\n static void\n rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n+\tstruct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->rq_dbrec_page;\n+\n \tif (rxq_ctrl->rxq.wqes) {\n \t\tmlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);\n \t\trxq_ctrl->rxq.wqes = NULL;\n@@ -60,6 +86,12 @@\n \t\tmlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);\n \t\trxq_ctrl->wq_umem = NULL;\n \t}\n+\tif (dbr_page) {\n+\t\tclaim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,\n+\t\t\t\t\t mlx5_os_get_umem_id(dbr_page->umem),\n+\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n+\t\trxq_ctrl->rq_dbrec_page = NULL;\n+\t}\n }\n \n /**\n@@ -71,6 +103,8 @@\n static void\n rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n+\tstruct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->cq_dbrec_page;\n+\n \tif (rxq_ctrl->rxq.cqes) {\n \t\trte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);\n \t\trxq_ctrl->rxq.cqes = NULL;\n@@ -79,6 +113,12 @@\n \t\tmlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);\n \t\trxq_ctrl->cq_umem = NULL;\n \t}\n+\tif (dbr_page) {\n+\t\tclaim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,\n+\t\t\t\t\t mlx5_os_get_umem_id(dbr_page->umem),\n+\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n+\t\trxq_ctrl->cq_dbrec_page = NULL;\n+\t}\n }\n \n /**\n@@ -108,8 +148,6 @@\n static void\n mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)\n {\n-\tstruct mlx5_priv *priv = rxq_obj->rxq_ctrl->priv;\n-\n \tMLX5_ASSERT(rxq_obj);\n \tMLX5_ASSERT(rxq_obj->rq);\n \tif (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN) {\n@@ -118,12 +156,6 @@\n \t\tMLX5_ASSERT(rxq_obj->devx_cq);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n-\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t rxq_obj->rxq_ctrl->rq_dbr_umem_id,\n-\t\t\t\t\t rxq_obj->rxq_ctrl->rq_dbr_offset));\n-\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t rxq_obj->rxq_ctrl->cq_dbr_umem_id,\n-\t\t\t\t\t rxq_obj->rxq_ctrl->cq_dbr_offset));\n \t\tif (rxq_obj->devx_channel)\n \t\t\tmlx5_glue->devx_destroy_event_channel\n \t\t\t\t\t\t\t(rxq_obj->devx_channel);\n@@ -208,7 +240,8 @@\n \t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n \twq_attr->pd = priv->sh->pdn;\n \twq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;\n-\twq_attr->dbr_umem_id = rxq_ctrl->rq_dbr_umem_id;\n+\twq_attr->dbr_umem_id =\n+\t\t\tmlx5_os_get_umem_id(rxq_ctrl->rq_dbrec_page->umem);\n \twq_attr->dbr_umem_valid = 1;\n \twq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);\n \twq_attr->wq_umem_valid = 1;\n@@ -221,14 +254,12 @@\n * Pointer to Ethernet device.\n * @param idx\n * Queue index in DPDK Rx queue array.\n- * @param cqn\n- * CQ number to use with this RQ.\n *\n * @return\n- * The DevX object initialized, NULL otherwise and rte_errno is set.\n+ * The DevX RQ object initialized, NULL otherwise and rte_errno is set.\n */\n static struct mlx5_devx_obj *\n-mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)\n+rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n@@ -236,6 +267,9 @@\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct mlx5_devx_create_rq_attr rq_attr = { 0 };\n \tuint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);\n+\tuint32_t cqn = rxq_ctrl->obj->devx_cq->id;\n+\tstruct mlx5_devx_dbr_page *dbr_page;\n+\tint64_t dbr_offset;\n \tuint32_t wq_size = 0;\n \tuint32_t wqe_size = 0;\n \tuint32_t log_wqe_size = 0;\n@@ -284,15 +318,27 @@\n \trxq_data->wqes = buf;\n \trxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,\n \t\t\t\t\t\t buf, wq_size, 0);\n-\tif (!rxq_ctrl->wq_umem) {\n-\t\tmlx5_free(buf);\n-\t\treturn NULL;\n+\tif (!rxq_ctrl->wq_umem)\n+\t\tgoto error;\n+\t/* Allocate RQ door-bell. */\n+\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);\n+\tif (dbr_offset < 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate RQ door-bell.\");\n+\t\tgoto error;\n \t}\n+\trxq_ctrl->rq_dbr_offset = dbr_offset;\n+\trxq_ctrl->rq_dbrec_page = dbr_page;\n+\trxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t (uintptr_t)rxq_ctrl->rq_dbr_offset);\n+\t/* Create RQ using DevX API. */\n \tmlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);\n \trq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);\n \tif (!rq)\n-\t\trxq_release_devx_rq_resources(rxq_ctrl);\n+\t\tgoto error;\n \treturn rq;\n+error:\n+\trxq_release_devx_rq_resources(rxq_ctrl);\n+\treturn NULL;\n }\n \n /**\n@@ -300,19 +346,14 @@\n *\n * @param dev\n * Pointer to Ethernet device.\n- * @param cqe_n\n- * Number of CQEs in CQ.\n * @param idx\n * Queue index in DPDK Rx queue array.\n- * @param rxq_obj\n- * Pointer to Rx queue object data.\n *\n * @return\n- * The DevX object initialized, NULL otherwise and rte_errno is set.\n+ * The DevX CQ object initialized, NULL otherwise and rte_errno is set.\n */\n static struct mlx5_devx_obj *\n-mlx5_devx_cq_new(struct rte_eth_dev *dev, unsigned int cqe_n, uint16_t idx,\n-\t\t struct mlx5_rxq_obj *rxq_obj)\n+rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_devx_obj *cq_obj = 0;\n \tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n@@ -322,6 +363,9 @@\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tsize_t page_size = rte_mem_page_size();\n \tuint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);\n+\tunsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);\n+\tstruct mlx5_devx_dbr_page *dbr_page;\n+\tint64_t dbr_offset;\n \tuint32_t eqn = 0;\n \tvoid *buf = NULL;\n \tuint16_t event_nums[1] = {0};\n@@ -386,6 +430,19 @@\n \t\tDRV_LOG(ERR, \"Failed to register umem for CQ.\");\n \t\tgoto error;\n \t}\n+\t/* Allocate CQ door-bell. */\n+\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);\n+\tif (dbr_offset < 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n+\t\tgoto error;\n+\t}\n+\trxq_ctrl->cq_dbr_offset = dbr_offset;\n+\trxq_ctrl->cq_dbrec_page = dbr_page;\n+\trxq_data->cq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t (uintptr_t)rxq_ctrl->cq_dbr_offset);\n+\trxq_data->cq_uar =\n+\t\t\tmlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);\n+\t/* Create CQ using DevX API. */\n \tcq_attr.uar_page_id =\n \t\t\tmlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);\n \tcq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);\n@@ -393,16 +450,16 @@\n \tcq_attr.log_cq_size = log_cqe_n;\n \tcq_attr.log_page_size = rte_log2_u32(page_size);\n \tcq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;\n-\tcq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;\n+\tcq_attr.db_umem_id = mlx5_os_get_umem_id(dbr_page->umem);\n \tcq_attr.db_umem_valid = 1;\n \tcq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);\n \tif (!cq_obj)\n \t\tgoto error;\n \trxq_data->cqe_n = log_cqe_n;\n \trxq_data->cqn = cq_obj->id;\n-\tif (rxq_obj->devx_channel) {\n+\tif (rxq_ctrl->obj->devx_channel) {\n \t\tret = mlx5_glue->devx_subscribe_devx_event\n-\t\t\t\t\t\t(rxq_obj->devx_channel,\n+\t\t\t\t\t\t(rxq_ctrl->obj->devx_channel,\n \t\t\t\t\t\t cq_obj->obj,\n \t\t\t\t\t\t sizeof(event_nums),\n \t\t\t\t\t\t event_nums,\n@@ -501,13 +558,8 @@\n \tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\tunsigned int cqe_n;\n-\tunsigned int wqe_n = 1 << rxq_data->elts_n;\n \tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n \tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n-\tstruct mlx5_devx_dbr_page *cq_dbr_page = NULL;\n-\tstruct mlx5_devx_dbr_page *rq_dbr_page = NULL;\n-\tint64_t dbr_offset;\n \tint ret = 0;\n \n \tMLX5_ASSERT(rxq_data);\n@@ -531,40 +583,14 @@\n \t\t}\n \t\ttmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);\n \t}\n-\tif (mlx5_rxq_mprq_enabled(rxq_data))\n-\t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n-\telse\n-\t\tcqe_n = wqe_n - 1;\n-\t/* Allocate CQ door-bell. */\n-\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &cq_dbr_page);\n-\tif (dbr_offset < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\trxq_ctrl->cq_dbr_offset = dbr_offset;\n-\trxq_ctrl->cq_dbr_umem_id = mlx5_os_get_umem_id(cq_dbr_page->umem);\n-\trxq_data->cq_db = (uint32_t *)((uintptr_t)cq_dbr_page->dbrs +\n-\t\t\t\t (uintptr_t)rxq_ctrl->cq_dbr_offset);\n-\trxq_data->cq_uar =\n-\t\t\tmlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);\n \t/* Create CQ using DevX API. */\n-\ttmpl->devx_cq = mlx5_devx_cq_new(dev, cqe_n, idx, tmpl);\n+\ttmpl->devx_cq = rxq_create_devx_cq_resources(dev, idx);\n \tif (!tmpl->devx_cq) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n-\t/* Allocate RQ door-bell. */\n-\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &rq_dbr_page);\n-\tif (dbr_offset < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate RQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\trxq_ctrl->rq_dbr_offset = dbr_offset;\n-\trxq_ctrl->rq_dbr_umem_id = mlx5_os_get_umem_id(rq_dbr_page->umem);\n-\trxq_data->rq_db = (uint32_t *)((uintptr_t)rq_dbr_page->dbrs +\n-\t\t\t\t (uintptr_t)rxq_ctrl->rq_dbr_offset);\n \t/* Create RQ using DevX API. */\n-\ttmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);\n+\ttmpl->rq = rxq_create_devx_rq_resources(dev, idx);\n \tif (!tmpl->rq) {\n \t\tDRV_LOG(ERR, \"Port %u Rx queue %u RQ creation failure.\",\n \t\t\tdev->data->port_id, idx);\n@@ -591,14 +617,6 @@\n \t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));\n \tif (tmpl->devx_channel)\n \t\tmlx5_glue->devx_destroy_event_channel(tmpl->devx_channel);\n-\tif (rq_dbr_page)\n-\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n-\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n-\tif (cq_dbr_page)\n-\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n-\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n \trxq_release_devx_rq_resources(rxq_ctrl);\n \trxq_release_devx_cq_resources(rxq_ctrl);\n \trte_errno = ret; /* Restore rte_errno. */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex d4a6c50..6d135dd 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -175,10 +175,10 @@ struct mlx5_rxq_ctrl {\n \tuint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */\n \tuint32_t wqn; /* WQ number. */\n \tuint16_t dump_file_n; /* Number of dump files. */\n-\tuint32_t rq_dbr_umem_id;\n+\tstruct mlx5_devx_dbr_page *rq_dbrec_page;\n \tuint64_t rq_dbr_offset;\n \t/* Storing RQ door-bell information, needed when freeing door-bell. */\n-\tuint32_t cq_dbr_umem_id;\n+\tstruct mlx5_devx_dbr_page *cq_dbrec_page;\n \tuint64_t cq_dbr_offset;\n \t/* Storing CQ door-bell information, needed when freeing door-bell. */\n \tvoid *wq_umem; /* WQ buffer registration info. */\n", "prefixes": [ "v1", "08/18" ] }