Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/76390/?format=api
{ "id": 76390, "url": "http://patches.dpdk.org/api/patches/76390/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-8-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599128029-2092-8-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-8-git-send-email-michaelba@nvidia.com", "date": "2020-09-03T10:13:38", "name": "[v1,07/18] net/mlx5: share Rx control code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7526f08d3eb7f4029d2cfe832c253a4bb6005b5d", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-8-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 11924, "url": "http://patches.dpdk.org/api/series/11924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924", "date": "2020-09-03T10:13:31", "name": "mlx5 Rx DevX/Verbs separation", "version": 1, "mbox": "http://patches.dpdk.org/series/11924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76390/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76390/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F691A04DB;\n\tThu, 3 Sep 2020 12:15:51 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8B9151C12C;\n\tThu, 3 Sep 2020 12:14:51 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id EC3FB1C125\n for <dev@dpdk.org>; Thu, 3 Sep 2020 12:14:49 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:14:46 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP95031645;\n Thu, 3 Sep 2020 13:14:46 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 3 Sep 2020 10:13:38 +0000", "Message-Id": "<1599128029-2092-8-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 07/18] net/mlx5: share Rx control code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Move Rx object similar resources allocations and debug logs from DevX\nand Verbs modules to a shared location.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_verbs.c | 50 +++++++-----------------\n drivers/net/mlx5/mlx5.h | 3 +-\n drivers/net/mlx5/mlx5_devx.c | 77 ++++++++++---------------------------\n drivers/net/mlx5/mlx5_rxq.c | 8 +++-\n drivers/net/mlx5/mlx5_rxtx.h | 1 -\n drivers/net/mlx5/mlx5_trigger.c | 30 +++++++++++++--\n 6 files changed, 68 insertions(+), 101 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 3af09db..16e5900 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -269,9 +269,9 @@\n * Queue index in DPDK Rx queue array.\n *\n * @return\n- * The Verbs object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_rxq_obj *\n+static int\n mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -281,24 +281,16 @@\n \tstruct ibv_wq_attr mod;\n \tunsigned int cqe_n;\n \tunsigned int wqe_n = 1 << rxq_data->elts_n;\n-\tstruct mlx5_rxq_obj *tmpl = NULL;\n+\tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n \tstruct mlx5dv_cq cq_info;\n \tstruct mlx5dv_rwq rwq;\n \tint ret = 0;\n \tstruct mlx5dv_obj obj;\n \n \tMLX5_ASSERT(rxq_data);\n-\tMLX5_ASSERT(!rxq_ctrl->obj);\n+\tMLX5_ASSERT(tmpl);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;\n \tpriv->verbs_alloc_ctx.obj = rxq_ctrl;\n-\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n-\t\t\t rxq_ctrl->socket);\n-\tif (!tmpl) {\n-\t\tDRV_LOG(ERR, \"port %u Rx queue %u cannot allocate resources\",\n-\t\t\tdev->data->port_id, rxq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n \ttmpl->type = MLX5_RXQ_OBJ_TYPE_IBV;\n \ttmpl->rxq_ctrl = rxq_ctrl;\n \tif (rxq_ctrl->irq) {\n@@ -316,10 +308,6 @@\n \t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n \telse\n \t\tcqe_n = wqe_n - 1;\n-\tDRV_LOG(DEBUG, \"port %u device_attr.max_qp_wr is %d\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_qp_wr);\n-\tDRV_LOG(DEBUG, \"port %u device_attr.max_sge is %d\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n \t/* Create CQ using Verbs API. */\n \ttmpl->ibv_cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);\n \tif (!tmpl->ibv_cq) {\n@@ -382,28 +370,21 @@\n \trxq_data->cq_arm_sn = 0;\n \tmlx5_rxq_initialize(rxq_data);\n \trxq_data->cq_ci = 0;\n-\tDRV_LOG(DEBUG, \"port %u rxq %u updated with %p\", dev->data->port_id,\n-\t\tidx, (void *)&tmpl);\n-\tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n \trxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;\n-\treturn tmpl;\n+\treturn 0;\n error:\n-\tif (tmpl) {\n-\t\tret = rte_errno; /* Save rte_errno before cleanup. */\n-\t\tif (tmpl->wq)\n-\t\t\tclaim_zero(mlx5_glue->destroy_wq(tmpl->wq));\n-\t\tif (tmpl->ibv_cq)\n-\t\t\tclaim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));\n-\t\tif (tmpl->ibv_channel)\n-\t\t\tclaim_zero(mlx5_glue->destroy_comp_channel\n-\t\t\t\t\t\t\t(tmpl->ibv_channel));\n-\t\tmlx5_free(tmpl);\n-\t\trte_errno = ret; /* Restore rte_errno. */\n-\t}\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (tmpl->wq)\n+\t\tclaim_zero(mlx5_glue->destroy_wq(tmpl->wq));\n+\tif (tmpl->ibv_cq)\n+\t\tclaim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));\n+\tif (tmpl->ibv_channel)\n+\t\tclaim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));\n+\trte_errno = ret; /* Restore rte_errno. */\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n-\treturn NULL;\n+\treturn -rte_errno;\n }\n \n /**\n@@ -418,14 +399,11 @@\n \tMLX5_ASSERT(rxq_obj);\n \tMLX5_ASSERT(rxq_obj->wq);\n \tMLX5_ASSERT(rxq_obj->ibv_cq);\n-\trxq_free_elts(rxq_obj->rxq_ctrl);\n \tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n \tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));\n \tif (rxq_obj->ibv_channel)\n \t\tclaim_zero(mlx5_glue->destroy_comp_channel\n \t\t\t\t\t\t\t(rxq_obj->ibv_channel));\n-\tLIST_REMOVE(rxq_obj, next);\n-\tmlx5_free(rxq_obj);\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f0e2929..5131a47 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -707,8 +707,7 @@ struct mlx5_rxq_obj {\n /* HW objects operations structure. */\n struct mlx5_obj_ops {\n \tint (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);\n-\tstruct mlx5_rxq_obj *(*rxq_obj_new)(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint16_t idx);\n+\tint (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);\n \tint (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);\n \tvoid (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);\n };\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 39e2ad5..5b1cf14 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -116,7 +116,6 @@\n \t\tmlx5_rxq_obj_hairpin_release(rxq_obj);\n \t} else {\n \t\tMLX5_ASSERT(rxq_obj->devx_cq);\n-\t\trxq_free_elts(rxq_obj->rxq_ctrl);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n \t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n@@ -131,8 +130,6 @@\n \t\trxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);\n \t\trxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);\n \t}\n-\tLIST_REMOVE(rxq_obj, next);\n-\tmlx5_free(rxq_obj);\n }\n \n /**\n@@ -435,9 +432,9 @@\n * Queue index in DPDK Rx queue array.\n *\n * @return\n- * The hairpin DevX object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_rxq_obj *\n+static int\n mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -445,19 +442,11 @@\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct mlx5_devx_create_rq_attr attr = { 0 };\n-\tstruct mlx5_rxq_obj *tmpl = NULL;\n+\tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n \tuint32_t max_wq_data;\n \n \tMLX5_ASSERT(rxq_data);\n-\tMLX5_ASSERT(!rxq_ctrl->obj);\n-\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n-\t\t\t rxq_ctrl->socket);\n-\tif (!tmpl) {\n-\t\tDRV_LOG(ERR, \"port %u Rx queue %u cannot allocate resources\",\n-\t\t\tdev->data->port_id, rxq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\treturn NULL;\n-\t}\n+\tMLX5_ASSERT(tmpl);\n \ttmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;\n \ttmpl->rxq_ctrl = rxq_ctrl;\n \tattr.hairpin = 1;\n@@ -468,9 +457,8 @@\n \t\t\tDRV_LOG(ERR, \"Total data size %u power of 2 is \"\n \t\t\t\t\"too large for hairpin.\",\n \t\t\t\tpriv->config.log_hp_size);\n-\t\t\tmlx5_free(tmpl);\n \t\t\trte_errno = ERANGE;\n-\t\t\treturn NULL;\n+\t\t\treturn -rte_errno;\n \t\t}\n \t\tattr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n \t} else {\n@@ -488,15 +476,11 @@\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u Rx hairpin queue %u can't create rq object.\",\n \t\t\tdev->data->port_id, idx);\n-\t\tmlx5_free(tmpl);\n \t\trte_errno = errno;\n-\t\treturn NULL;\n+\t\treturn -rte_errno;\n \t}\n-\tDRV_LOG(DEBUG, \"port %u rxq %u updated with %p\", dev->data->port_id,\n-\t\tidx, (void *)&tmpl);\n-\tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;\n-\treturn tmpl;\n+\treturn 0;\n }\n \n /**\n@@ -508,9 +492,9 @@\n * Queue index in DPDK Rx queue array.\n *\n * @return\n- * The DevX object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_rxq_obj *\n+static int\n mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -519,7 +503,7 @@\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tunsigned int cqe_n;\n \tunsigned int wqe_n = 1 << rxq_data->elts_n;\n-\tstruct mlx5_rxq_obj *tmpl = NULL;\n+\tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n \tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n \tstruct mlx5_devx_dbr_page *cq_dbr_page = NULL;\n \tstruct mlx5_devx_dbr_page *rq_dbr_page = NULL;\n@@ -527,17 +511,9 @@\n \tint ret = 0;\n \n \tMLX5_ASSERT(rxq_data);\n-\tMLX5_ASSERT(!rxq_ctrl->obj);\n+\tMLX5_ASSERT(tmpl);\n \tif (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)\n \t\treturn mlx5_rxq_obj_hairpin_new(dev, idx);\n-\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n-\t\t\t rxq_ctrl->socket);\n-\tif (!tmpl) {\n-\t\tDRV_LOG(ERR, \"port %u Rx queue %u cannot allocate resources\",\n-\t\t\tdev->data->port_id, rxq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n \ttmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_RQ;\n \ttmpl->rxq_ctrl = rxq_ctrl;\n \tif (rxq_ctrl->irq) {\n@@ -559,10 +535,6 @@\n \t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n \telse\n \t\tcqe_n = wqe_n - 1;\n-\tDRV_LOG(DEBUG, \"port %u device_attr.max_qp_wr is %d\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_qp_wr);\n-\tDRV_LOG(DEBUG, \"port %u device_attr.max_sge is %d\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n \t/* Allocate CQ door-bell. */\n \tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &cq_dbr_page);\n \tif (dbr_offset < 0) {\n@@ -608,25 +580,17 @@\n \trxq_data->cq_arm_sn = 0;\n \tmlx5_rxq_initialize(rxq_data);\n \trxq_data->cq_ci = 0;\n-\tDRV_LOG(DEBUG, \"port %u rxq %u updated with %p\", dev->data->port_id,\n-\t\tidx, (void *)&tmpl);\n-\tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n \trxq_ctrl->wqn = tmpl->rq->id;\n-\treturn tmpl;\n+\treturn 0;\n error:\n-\tif (tmpl) {\n-\t\tret = rte_errno; /* Save rte_errno before cleanup. */\n-\t\tif (tmpl->rq)\n-\t\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->rq));\n-\t\tif (tmpl->devx_cq)\n-\t\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));\n-\t\tif (tmpl->devx_channel)\n-\t\t\tmlx5_glue->devx_destroy_event_channel\n-\t\t\t\t\t\t\t(tmpl->devx_channel);\n-\t\tmlx5_free(tmpl);\n-\t\trte_errno = ret; /* Restore rte_errno. */\n-\t}\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (tmpl->rq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->rq));\n+\tif (tmpl->devx_cq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));\n+\tif (tmpl->devx_channel)\n+\t\tmlx5_glue->devx_destroy_event_channel(tmpl->devx_channel);\n \tif (rq_dbr_page)\n \t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n \t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n@@ -637,7 +601,8 @@\n \t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n \trxq_release_devx_rq_resources(rxq_ctrl);\n \trxq_release_devx_cq_resources(rxq_ctrl);\n-\treturn NULL;\n+\trte_errno = ret; /* Restore rte_errno. */\n+\treturn -rte_errno;\n }\n \n struct mlx5_obj_ops devx_obj_ops = {\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 46d5f6c..00ef230 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -347,7 +347,7 @@\n * @param rxq_ctrl\n * Pointer to RX queue structure.\n */\n-void\n+static void\n rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n \tif (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))\n@@ -1651,10 +1651,14 @@ struct mlx5_rxq_ctrl *\n \t\treturn 1;\n \tif (rxq_ctrl->obj) {\n \t\tpriv->obj_ops->rxq_obj_release(rxq_ctrl->obj);\n+\t\tLIST_REMOVE(rxq_ctrl->obj, next);\n+\t\tmlx5_free(rxq_ctrl->obj);\n \t\trxq_ctrl->obj = NULL;\n \t}\n-\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n+\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {\n \t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n+\t\trxq_free_elts(rxq_ctrl);\n+\t}\n \tLIST_REMOVE(rxq_ctrl, next);\n \tmlx5_free(rxq_ctrl);\n \t(*priv->rxqs)[idx] = NULL;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 4baf5b9..d4a6c50 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -400,7 +400,6 @@ struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new\n int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_rxq_verify(struct rte_eth_dev *dev);\n int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);\n-void rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl);\n int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);\n uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,\n \t\t const uint8_t *rss_key, uint32_t rss_key_len,\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 6376719..43eff93 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -10,6 +10,8 @@\n #include <rte_interrupts.h>\n #include <rte_alarm.h>\n \n+#include <mlx5_malloc.h>\n+\n #include \"mlx5.h\"\n #include \"mlx5_mr.h\"\n #include \"mlx5_rxtx.h\"\n@@ -115,6 +117,10 @@\n \t\t/* Should not release Rx queues but return immediately. */\n \t\treturn -rte_errno;\n \t}\n+\tDRV_LOG(DEBUG, \"Port %u device_attr.max_qp_wr is %d.\",\n+\t\tdev->data->port_id, priv->sh->device_attr.max_qp_wr);\n+\tDRV_LOG(DEBUG, \"Port %u device_attr.max_sge is %d.\",\n+\t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);\n \t\tstruct rte_mempool *mp;\n@@ -125,17 +131,33 @@\n \t\t\t/* Pre-register Rx mempool. */\n \t\t\tmp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?\n \t\t\t rxq_ctrl->rxq.mprq_mp : rxq_ctrl->rxq.mp;\n-\t\t\tDRV_LOG(DEBUG, \"port %u Rx queue %u registering mp %s\"\n-\t\t\t\t\" having %u chunks\", dev->data->port_id,\n+\t\t\tDRV_LOG(DEBUG, \"Port %u Rx queue %u registering mp %s\"\n+\t\t\t\t\" having %u chunks.\", dev->data->port_id,\n \t\t\t\trxq_ctrl->rxq.idx, mp->name, mp->nb_mem_chunks);\n \t\t\tmlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl, mp);\n \t\t\tret = rxq_alloc_elts(rxq_ctrl);\n \t\t\tif (ret)\n \t\t\t\tgoto error;\n \t\t}\n-\t\trxq_ctrl->obj = priv->obj_ops->rxq_obj_new(dev, i);\n-\t\tif (!rxq_ctrl->obj)\n+\t\tMLX5_ASSERT(!rxq_ctrl->obj);\n+\t\trxq_ctrl->obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n+\t\t\t\t\t sizeof(*rxq_ctrl->obj), 0,\n+\t\t\t\t\t rxq_ctrl->socket);\n+\t\tif (!rxq_ctrl->obj) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Port %u Rx queue %u can't allocate resources.\",\n+\t\t\t\tdev->data->port_id, (*priv->rxqs)[i]->idx);\n+\t\t\trte_errno = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tret = priv->obj_ops->rxq_obj_new(dev, i);\n+\t\tif (ret) {\n+\t\t\tmlx5_free(rxq_ctrl->obj);\n \t\t\tgoto error;\n+\t\t}\n+\t\tDRV_LOG(DEBUG, \"Port %u rxq %u updated with %p.\",\n+\t\t\tdev->data->port_id, i, (void *)&rxq_ctrl->obj);\n+\t\tLIST_INSERT_HEAD(&priv->rxqsobj, rxq_ctrl->obj, next);\n \t}\n \treturn 0;\n error:\n", "prefixes": [ "v1", "07/18" ] }