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GET /api/patches/76387/?format=api
{ "id": 76387, "url": "http://patches.dpdk.org/api/patches/76387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-4-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599128029-2092-4-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-4-git-send-email-michaelba@nvidia.com", "date": "2020-09-03T10:13:34", "name": "[v1,03/18] net/mlx5: fix types differentiation in Rxq create", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "83945abeded2292357ebe43669406402176571e5", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-4-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 11924, "url": "http://patches.dpdk.org/api/series/11924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924", "date": "2020-09-03T10:13:31", "name": "mlx5 Rx DevX/Verbs separation", "version": 1, "mbox": "http://patches.dpdk.org/series/11924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76387/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76387/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2AA7CA04DB;\n\tThu, 3 Sep 2020 12:15:07 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2F1D81C10E;\n\tThu, 3 Sep 2020 12:14:42 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id DF9BC1C0D9\n for <dev@dpdk.org>; Thu, 3 Sep 2020 12:14:39 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:14:35 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP91031645;\n Thu, 3 Sep 2020 13:14:35 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, stable@dpdk.org", "Date": "Thu, 3 Sep 2020 10:13:34 +0000", "Message-Id": "<1599128029-2092-4-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v1 03/18] net/mlx5: fix types differentiation in\n\tRxq create", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rx HW objects can be created by both Verbs and DevX operations.\nThe management of the 2 types of operations are done directly in the\nmain flow of the object’s creations.\n\nSome arrangements and validations were wrongly done to the irrelevant\ntype:\n\n1. LRO related validations were done for Verbs type where LRO is not\nsupported at all.\n2. Verbs allocation arrangements were done for DevX operations where it\nis not needed.\n3. Doorbell destroy was considered for Verbs types where it is\nirrelevant.\n\nAdjust the aforementioned points only for the relevant types.\n\nFixes: e79c9be91515 (\"net/mlx5: support Rx hairpin queues\")\nFixes: 08d1838f645a (\"net/mlx5: implement CQ for Rx using DevX API\")\nFixes: 17ed314c6c0b (\"net/mlx5: allow LRO per Rx queue\")\nFixes: dc9ceff73c99 (\"net/mlx5: create advanced RxQ via DevX\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 78 +++++++++++++++++++++++---------------------\n drivers/net/mlx5/mlx5_rxtx.h | 2 --\n 2 files changed, 41 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 2e6cbd4..776c7f6 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -927,13 +927,16 @@\n static int\n mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)\n {\n+\tstruct mlx5_priv *priv = rxq_obj->rxq_ctrl->priv;\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl = rxq_obj->rxq_ctrl;\n+\n \tMLX5_ASSERT(rxq_obj);\n \tif (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {\n \t\tswitch (rxq_obj->type) {\n \t\tcase MLX5_RXQ_OBJ_TYPE_IBV:\n \t\t\tMLX5_ASSERT(rxq_obj->wq);\n \t\t\tMLX5_ASSERT(rxq_obj->ibv_cq);\n-\t\t\trxq_free_elts(rxq_obj->rxq_ctrl);\n+\t\t\trxq_free_elts(rxq_ctrl);\n \t\t\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n \t\t\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));\n \t\t\tif (rxq_obj->ibv_channel)\n@@ -943,14 +946,20 @@\n \t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_RQ:\n \t\t\tMLX5_ASSERT(rxq_obj->rq);\n \t\t\tMLX5_ASSERT(rxq_obj->devx_cq);\n-\t\t\trxq_free_elts(rxq_obj->rxq_ctrl);\n+\t\t\trxq_free_elts(rxq_ctrl);\n \t\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n+\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n+\t\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n+\t\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n+\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n+\t\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n+\t\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n \t\t\tif (rxq_obj->devx_channel)\n \t\t\t\tmlx5_glue->devx_destroy_event_channel\n \t\t\t\t\t\t\t(rxq_obj->devx_channel);\n-\t\t\trxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);\n-\t\t\trxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);\n+\t\t\trxq_release_devx_rq_resources(rxq_ctrl);\n+\t\t\trxq_release_devx_cq_resources(rxq_ctrl);\n \t\t\tbreak;\n \t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:\n \t\t\tMLX5_ASSERT(rxq_obj->rq);\n@@ -1264,8 +1273,7 @@\n \tcq_attr.mlx5 = (struct mlx5dv_cq_init_attr){\n \t\t.comp_mask = 0,\n \t};\n-\tif (priv->config.cqe_comp && !rxq_data->hw_timestamp &&\n-\t !rxq_data->lro) {\n+\tif (priv->config.cqe_comp && !rxq_data->hw_timestamp) {\n \t\tcq_attr.mlx5.comp_mask |=\n \t\t\t\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n@@ -1287,10 +1295,6 @@\n \t\t\t\"port %u Rx CQE compression is disabled for HW\"\n \t\t\t\" timestamp\",\n \t\t\tdev->data->port_id);\n-\t} else if (priv->config.cqe_comp && rxq_data->lro) {\n-\t\tDRV_LOG(DEBUG,\n-\t\t\t\"port %u Rx CQE compression is disabled for LRO\",\n-\t\t\tdev->data->port_id);\n \t}\n #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n \tif (priv->config.cqe_pad) {\n@@ -1628,7 +1632,7 @@\n \tcq_attr.log_page_size = rte_log2_u32(page_size);\n \tcq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;\n \tcq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;\n-\tcq_attr.db_umem_valid = rxq_ctrl->cq_dbr_umem_id_valid;\n+\tcq_attr.db_umem_valid = 1;\n \tcq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);\n \tif (!cq_obj)\n \t\tgoto error;\n@@ -1684,8 +1688,7 @@\n \ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n \t\t\t rxq_ctrl->socket);\n \tif (!tmpl) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"port %u Rx queue %u cannot allocate verbs resources\",\n+\t\tDRV_LOG(ERR, \"port %u Rx queue %u cannot allocate resources\",\n \t\t\tdev->data->port_id, rxq_data->idx);\n \t\trte_errno = ENOMEM;\n \t\treturn NULL;\n@@ -1728,7 +1731,6 @@\n \t\tidx, (void *)&tmpl);\n \trte_atomic32_inc(&tmpl->refcnt);\n \tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n-\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;\n \treturn tmpl;\n }\n@@ -1758,6 +1760,8 @@ struct mlx5_rxq_obj *\n \tunsigned int cqe_n;\n \tunsigned int wqe_n = 1 << rxq_data->elts_n;\n \tstruct mlx5_rxq_obj *tmpl = NULL;\n+\tstruct mlx5_devx_dbr_page *cq_dbr_page = NULL;\n+\tstruct mlx5_devx_dbr_page *rq_dbr_page = NULL;\n \tstruct mlx5dv_cq cq_info;\n \tstruct mlx5dv_rwq rwq;\n \tint ret = 0;\n@@ -1767,13 +1771,10 @@ struct mlx5_rxq_obj *\n \tMLX5_ASSERT(!rxq_ctrl->obj);\n \tif (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)\n \t\treturn mlx5_rxq_obj_hairpin_new(dev, idx);\n-\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;\n-\tpriv->verbs_alloc_ctx.obj = rxq_ctrl;\n \ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n \t\t\t rxq_ctrl->socket);\n \tif (!tmpl) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"port %u Rx queue %u cannot allocate resources\",\n+\t\tDRV_LOG(ERR, \"port %u Rx queue %u cannot allocate resources\",\n \t\t\tdev->data->port_id, rxq_data->idx);\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n@@ -1820,6 +1821,8 @@ struct mlx5_rxq_obj *\n \tDRV_LOG(DEBUG, \"port %u device_attr.max_sge is %d\",\n \t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n \tif (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {\n+\t\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;\n+\t\tpriv->verbs_alloc_ctx.obj = rxq_ctrl;\n \t\t/* Create CQ using Verbs API. */\n \t\ttmpl->ibv_cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n,\n \t\t\t\t\t tmpl);\n@@ -1882,23 +1885,23 @@ struct mlx5_rxq_obj *\n \t\t}\n \t\trxq_data->wqes = rwq.buf;\n \t\trxq_data->rq_db = rwq.dbrec;\n+\t\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \t} else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {\n \t\tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n-\t\tstruct mlx5_devx_dbr_page *dbr_page;\n \t\tint64_t dbr_offset;\n \n \t\t/* Allocate CQ door-bell. */\n \t\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,\n-\t\t\t\t\t &dbr_page);\n+\t\t\t\t\t &cq_dbr_page);\n \t\tif (dbr_offset < 0) {\n \t\t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n \t\t\tgoto error;\n \t\t}\n \t\trxq_ctrl->cq_dbr_offset = dbr_offset;\n-\t\trxq_ctrl->cq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);\n-\t\trxq_ctrl->cq_dbr_umem_id_valid = 1;\n+\t\trxq_ctrl->cq_dbr_umem_id =\n+\t\t\t\t\tmlx5_os_get_umem_id(cq_dbr_page->umem);\n \t\trxq_data->cq_db =\n-\t\t\t(uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t(uint32_t *)((uintptr_t)cq_dbr_page->dbrs +\n \t\t\t\t (uintptr_t)rxq_ctrl->cq_dbr_offset);\n \t\trxq_data->cq_uar =\n \t\t\tmlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);\n@@ -1910,16 +1913,16 @@ struct mlx5_rxq_obj *\n \t\t}\n \t\t/* Allocate RQ door-bell. */\n \t\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,\n-\t\t\t\t\t &dbr_page);\n+\t\t\t\t\t &rq_dbr_page);\n \t\tif (dbr_offset < 0) {\n \t\t\tDRV_LOG(ERR, \"Failed to allocate RQ door-bell.\");\n \t\t\tgoto error;\n \t\t}\n \t\trxq_ctrl->rq_dbr_offset = dbr_offset;\n-\t\trxq_ctrl->rq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);\n-\t\trxq_ctrl->rq_dbr_umem_id_valid = 1;\n+\t\trxq_ctrl->rq_dbr_umem_id =\n+\t\t\t\t\tmlx5_os_get_umem_id(rq_dbr_page->umem);\n \t\trxq_data->rq_db =\n-\t\t\t(uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t(uint32_t *)((uintptr_t)rq_dbr_page->dbrs +\n \t\t\t\t (uintptr_t)rxq_ctrl->rq_dbr_offset);\n \t\t/* Create RQ using DevX API. */\n \t\ttmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);\n@@ -1943,7 +1946,6 @@ struct mlx5_rxq_obj *\n \t\tidx, (void *)&tmpl);\n \trte_atomic32_inc(&tmpl->refcnt);\n \tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n-\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n \treturn tmpl;\n error:\n@@ -1957,6 +1959,7 @@ struct mlx5_rxq_obj *\n \t\t\tif (tmpl->ibv_channel)\n \t\t\t\tclaim_zero(mlx5_glue->destroy_comp_channel\n \t\t\t\t\t\t\t(tmpl->ibv_channel));\n+\t\t\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \t\t} else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {\n \t\t\tif (tmpl->rq)\n \t\t\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->rq));\n@@ -1966,6 +1969,16 @@ struct mlx5_rxq_obj *\n \t\t\tif (tmpl->devx_channel)\n \t\t\t\tmlx5_glue->devx_destroy_event_channel\n \t\t\t\t\t\t\t(tmpl->devx_channel);\n+\t\t\tif (rq_dbr_page)\n+\t\t\t\tclaim_zero(mlx5_release_dbr\n+\t\t\t\t\t\t (&priv->dbrpgs,\n+\t\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n+\t\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n+\t\t\tif (cq_dbr_page)\n+\t\t\t\tclaim_zero(mlx5_release_dbr\n+\t\t\t\t\t\t (&priv->dbrpgs,\n+\t\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n+\t\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n \t\t}\n \t\tmlx5_free(tmpl);\n \t\trte_errno = ret; /* Restore rte_errno. */\n@@ -1974,7 +1987,6 @@ struct mlx5_rxq_obj *\n \t\trxq_release_devx_rq_resources(rxq_ctrl);\n \t\trxq_release_devx_cq_resources(rxq_ctrl);\n \t}\n-\tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \treturn NULL;\n }\n \n@@ -2570,14 +2582,6 @@ struct mlx5_rxq_ctrl *\n \tif (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))\n \t\trxq_ctrl->obj = NULL;\n \tif (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {\n-\t\tif (rxq_ctrl->rq_dbr_umem_id_valid)\n-\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n-\t\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n-\t\tif (rxq_ctrl->cq_dbr_umem_id_valid)\n-\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n-\t\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n \t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n \t\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n \t\tLIST_REMOVE(rxq_ctrl, next);\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex f3fe2e1..a161d4e 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -200,8 +200,6 @@ struct mlx5_rxq_ctrl {\n \tenum mlx5_rxq_type type; /* Rxq type. */\n \tunsigned int socket; /* CPU socket ID for allocations. */\n \tunsigned int irq:1; /* Whether IRQ is enabled. */\n-\tunsigned int rq_dbr_umem_id_valid:1;\n-\tunsigned int cq_dbr_umem_id_valid:1;\n \tuint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */\n \tuint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */\n \tuint32_t wqn; /* WQ number. */\n", "prefixes": [ "v1", "03/18" ] }