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GET /api/patches/76386/?format=api
{ "id": 76386, "url": "http://patches.dpdk.org/api/patches/76386/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-5-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599128029-2092-5-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599128029-2092-5-git-send-email-michaelba@nvidia.com", "date": "2020-09-03T10:13:35", "name": "[v1,04/18] net/mlx5: mitigate Rx queue reference counters", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "99b2847b682ef28a2fb51861bc11413576fbcaf7", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599128029-2092-5-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 11924, "url": "http://patches.dpdk.org/api/series/11924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11924", "date": "2020-09-03T10:13:31", "name": "mlx5 Rx DevX/Verbs separation", "version": 1, "mbox": "http://patches.dpdk.org/series/11924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76386/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76386/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2F9FCA04DB;\n\tThu, 3 Sep 2020 12:14:56 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E5E511C0CF;\n\tThu, 3 Sep 2020 12:14:40 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id DC2731C0CF\n for <dev@dpdk.org>; Thu, 3 Sep 2020 12:14:39 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 3 Sep 2020 13:14:38 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 083AEP92031645;\n Thu, 3 Sep 2020 13:14:38 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 3 Sep 2020 10:13:35 +0000", "Message-Id": "<1599128029-2092-5-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "References": "<1599128029-2092-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 04/18] net/mlx5: mitigate Rx queue reference\n\tcounters", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The Rx queue structures manage 2 different reference counter per queue:\nrxq_ctrl reference counter and rxq_obj reference counter.\n\nThere is no real need to use two different counters, it just complicates\nthe release functions.\nRemove the rxq_obj counter and use only the rxq_ctrl counter.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 208 ++++++++++++++++---------------------------\n drivers/net/mlx5/mlx5_rxtx.h | 1 -\n 2 files changed, 79 insertions(+), 130 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 776c7f6..506c4d3 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -832,34 +832,6 @@\n }\n \n /**\n- * Get an Rx queue Verbs/DevX object.\n- *\n- * @param dev\n- * Pointer to Ethernet device.\n- * @param idx\n- * Queue index in DPDK Rx queue array\n- *\n- * @return\n- * The Verbs/DevX object if it exists.\n- */\n-static struct mlx5_rxq_obj *\n-mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n-\n-\tif (idx >= priv->rxqs_n)\n-\t\treturn NULL;\n-\tif (!rxq_data)\n-\t\treturn NULL;\n-\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\tif (rxq_ctrl->obj)\n-\t\trte_atomic32_inc(&rxq_ctrl->obj->refcnt);\n-\treturn rxq_ctrl->obj;\n-}\n-\n-/**\n * Release the resources allocated for an RQ DevX object.\n *\n * @param rxq_ctrl\n@@ -920,57 +892,50 @@\n *\n * @param rxq_obj\n * Verbs/DevX Rx queue object.\n- *\n- * @return\n- * 1 while a reference on it exists, 0 when freed.\n */\n-static int\n+static void\n mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)\n {\n \tstruct mlx5_priv *priv = rxq_obj->rxq_ctrl->priv;\n \tstruct mlx5_rxq_ctrl *rxq_ctrl = rxq_obj->rxq_ctrl;\n \n \tMLX5_ASSERT(rxq_obj);\n-\tif (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {\n-\t\tswitch (rxq_obj->type) {\n-\t\tcase MLX5_RXQ_OBJ_TYPE_IBV:\n-\t\t\tMLX5_ASSERT(rxq_obj->wq);\n-\t\t\tMLX5_ASSERT(rxq_obj->ibv_cq);\n-\t\t\trxq_free_elts(rxq_ctrl);\n-\t\t\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n-\t\t\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));\n-\t\t\tif (rxq_obj->ibv_channel)\n-\t\t\t\tclaim_zero(mlx5_glue->destroy_comp_channel\n-\t\t\t\t\t (rxq_obj->ibv_channel));\n-\t\t\tbreak;\n-\t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_RQ:\n-\t\t\tMLX5_ASSERT(rxq_obj->rq);\n-\t\t\tMLX5_ASSERT(rxq_obj->devx_cq);\n-\t\t\trxq_free_elts(rxq_ctrl);\n-\t\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n-\t\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n-\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n-\t\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n-\t\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n-\t\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n-\t\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n-\t\t\tif (rxq_obj->devx_channel)\n-\t\t\t\tmlx5_glue->devx_destroy_event_channel\n+\tswitch (rxq_obj->type) {\n+\tcase MLX5_RXQ_OBJ_TYPE_IBV:\n+\t\tMLX5_ASSERT(rxq_obj->wq);\n+\t\tMLX5_ASSERT(rxq_obj->ibv_cq);\n+\t\trxq_free_elts(rxq_ctrl);\n+\t\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n+\t\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));\n+\t\tif (rxq_obj->ibv_channel)\n+\t\t\tclaim_zero(mlx5_glue->destroy_comp_channel\n+\t\t\t\t\t\t\t(rxq_obj->ibv_channel));\n+\t\tbreak;\n+\tcase MLX5_RXQ_OBJ_TYPE_DEVX_RQ:\n+\t\tMLX5_ASSERT(rxq_obj->rq);\n+\t\tMLX5_ASSERT(rxq_obj->devx_cq);\n+\t\trxq_free_elts(rxq_ctrl);\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n+\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n+\t\t\t\t\t rxq_ctrl->rq_dbr_umem_id,\n+\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n+\t\tclaim_zero(mlx5_release_dbr(&priv->dbrpgs,\n+\t\t\t\t\t rxq_ctrl->cq_dbr_umem_id,\n+\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n+\t\tif (rxq_obj->devx_channel)\n+\t\t\tmlx5_glue->devx_destroy_event_channel\n \t\t\t\t\t\t\t(rxq_obj->devx_channel);\n-\t\t\trxq_release_devx_rq_resources(rxq_ctrl);\n-\t\t\trxq_release_devx_cq_resources(rxq_ctrl);\n-\t\t\tbreak;\n-\t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:\n-\t\t\tMLX5_ASSERT(rxq_obj->rq);\n-\t\t\trxq_obj_hairpin_release(rxq_obj);\n-\t\t\tbreak;\n-\t\t}\n-\t\tLIST_REMOVE(rxq_obj, next);\n-\t\tmlx5_free(rxq_obj);\n-\t\treturn 0;\n+\t\trxq_release_devx_rq_resources(rxq_ctrl);\n+\t\trxq_release_devx_cq_resources(rxq_ctrl);\n+\t\tbreak;\n+\tcase MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:\n+\t\tMLX5_ASSERT(rxq_obj->rq);\n+\t\trxq_obj_hairpin_release(rxq_obj);\n+\t\tbreak;\n \t}\n-\treturn 1;\n+\tLIST_REMOVE(rxq_obj, next);\n+\tmlx5_free(rxq_obj);\n }\n \n /**\n@@ -1009,7 +974,8 @@\n \tintr_handle->type = RTE_INTR_HANDLE_EXT;\n \tfor (i = 0; i != n; ++i) {\n \t\t/* This rxq obj must not be released in this function. */\n-\t\tstruct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);\n+\t\tstruct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;\n \t\tint rc;\n \n \t\t/* Skip queues that cannot request interrupts. */\n@@ -1019,6 +985,9 @@\n \t\t\tintr_handle->intr_vec[i] =\n \t\t\t\tRTE_INTR_VEC_RXTX_OFFSET +\n \t\t\t\tRTE_MAX_RXTX_INTR_VEC_ID;\n+\t\t\t/* Decrease the rxq_ctrl's refcnt */\n+\t\t\tif (rxq_ctrl)\n+\t\t\t\tmlx5_rxq_release(dev, i);\n \t\t\tcontinue;\n \t\t}\n \t\tif (count >= RTE_MAX_RXTX_INTR_VEC_ID) {\n@@ -1073,9 +1042,6 @@\n \tif (!intr_handle->intr_vec)\n \t\tgoto free;\n \tfor (i = 0; i != n; ++i) {\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n-\t\tstruct mlx5_rxq_data *rxq_data;\n-\n \t\tif (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +\n \t\t RTE_MAX_RXTX_INTR_VEC_ID)\n \t\t\tcontinue;\n@@ -1083,10 +1049,7 @@\n \t\t * Need to access directly the queue to release the reference\n \t\t * kept in mlx5_rx_intr_vec_enable().\n \t\t */\n-\t\trxq_data = (*priv->rxqs)[i];\n-\t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\t\tif (rxq_ctrl->obj)\n-\t\t\tmlx5_rxq_obj_release(rxq_ctrl->obj);\n+\t\tmlx5_rxq_release(dev, i);\n \t}\n free:\n \trte_intr_free_epoll_fd(intr_handle);\n@@ -1135,28 +1098,23 @@\n int\n mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq_data;\n \tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \n-\trxq_data = (*priv->rxqs)[rx_queue_id];\n-\tif (!rxq_data) {\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n-\t}\n-\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\trxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);\n+\tif (!rxq_ctrl)\n+\t\tgoto error;\n \tif (rxq_ctrl->irq) {\n-\t\tstruct mlx5_rxq_obj *rxq_obj;\n-\n-\t\trxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);\n-\t\tif (!rxq_obj) {\n-\t\t\trte_errno = EINVAL;\n-\t\t\treturn -rte_errno;\n+\t\tif (!rxq_ctrl->obj) {\n+\t\t\tmlx5_rxq_release(dev, rx_queue_id);\n+\t\t\tgoto error;\n \t\t}\n-\t\tmlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);\n-\t\tmlx5_rxq_obj_release(rxq_obj);\n+\t\tmlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);\n \t}\n+\tmlx5_rxq_release(dev, rx_queue_id);\n \treturn 0;\n+error:\n+\trte_errno = EINVAL;\n+\treturn -rte_errno;\n }\n \n /**\n@@ -1173,32 +1131,29 @@\n int\n mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq_data;\n \tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \tstruct mlx5_rxq_obj *rxq_obj = NULL;\n \tstruct ibv_cq *ev_cq;\n \tvoid *ev_ctx;\n-\tint ret;\n+\tint ret = 0;\n \n-\trxq_data = (*priv->rxqs)[rx_queue_id];\n-\tif (!rxq_data) {\n+\trxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);\n+\tif (!rxq_ctrl) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\tif (!rxq_ctrl->irq)\n+\tif (!rxq_ctrl->irq) {\n+\t\tmlx5_rxq_release(dev, rx_queue_id);\n \t\treturn 0;\n-\trxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);\n-\tif (!rxq_obj) {\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n \t}\n+\trxq_obj = rxq_ctrl->obj;\n+\tif (!rxq_obj)\n+\t\tgoto error;\n \tif (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {\n \t\tret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel, &ev_cq,\n \t\t\t\t\t &ev_ctx);\n \t\tif (ret < 0 || ev_cq != rxq_obj->ibv_cq)\n-\t\t\tgoto exit;\n+\t\t\tgoto error;\n \t\tmlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);\n \t} else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {\n #ifdef HAVE_IBV_DEVX_EVENT\n@@ -1213,13 +1168,13 @@\n \t\t\t\t sizeof(out.buf));\n \t\tif (ret < 0 || out.event_resp.cookie !=\n \t\t\t\t(uint64_t)(uintptr_t)rxq_obj->devx_cq)\n-\t\t\tgoto exit;\n+\t\t\tgoto error;\n #endif /* HAVE_IBV_DEVX_EVENT */\n \t}\n-\trxq_data->cq_arm_sn++;\n-\tmlx5_rxq_obj_release(rxq_obj);\n+\trxq_ctrl->rxq.cq_arm_sn++;\n+\tmlx5_rxq_release(dev, rx_queue_id);\n \treturn 0;\n-exit:\n+error:\n \t/**\n \t * For ret < 0 save the errno (may be EAGAIN which means the get_event\n \t * function was called before receiving one).\n@@ -1229,8 +1184,7 @@\n \telse\n \t\trte_errno = EINVAL;\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n-\tif (rxq_obj)\n-\t\tmlx5_rxq_obj_release(rxq_obj);\n+\tmlx5_rxq_release(dev, rx_queue_id);\n \tif (ret != EAGAIN)\n \t\tDRV_LOG(WARNING, \"port %u unable to disable interrupt on Rx queue %d\",\n \t\t\tdev->data->port_id, rx_queue_id);\n@@ -1729,7 +1683,6 @@\n \t}\n \tDRV_LOG(DEBUG, \"port %u rxq %u updated with %p\", dev->data->port_id,\n \t\tidx, (void *)&tmpl);\n-\trte_atomic32_inc(&tmpl->refcnt);\n \tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;\n \treturn tmpl;\n@@ -1944,7 +1897,6 @@ struct mlx5_rxq_obj *\n \trxq_data->cq_ci = 0;\n \tDRV_LOG(DEBUG, \"port %u rxq %u updated with %p\", dev->data->port_id,\n \t\tidx, (void *)&tmpl);\n-\trte_atomic32_inc(&tmpl->refcnt);\n \tLIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n \treturn tmpl;\n@@ -2546,13 +2498,11 @@ struct mlx5_rxq_ctrl *\n mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n \tstruct mlx5_rxq_ctrl *rxq_ctrl = NULL;\n \n-\tif ((*priv->rxqs)[idx]) {\n-\t\trxq_ctrl = container_of((*priv->rxqs)[idx],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl,\n-\t\t\t\t\trxq);\n-\t\tmlx5_rxq_obj_get(dev, idx);\n+\tif (rxq_data) {\n+\t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \t\trte_atomic32_inc(&rxq_ctrl->refcnt);\n \t}\n \treturn rxq_ctrl;\n@@ -2578,18 +2528,18 @@ struct mlx5_rxq_ctrl *\n \tif (!(*priv->rxqs)[idx])\n \t\treturn 0;\n \trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\tMLX5_ASSERT(rxq_ctrl->priv);\n-\tif (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))\n+\tif (!rte_atomic32_dec_and_test(&rxq_ctrl->refcnt))\n+\t\treturn 1;\n+\tif (rxq_ctrl->obj) {\n+\t\tmlx5_rxq_obj_release(rxq_ctrl->obj);\n \t\trxq_ctrl->obj = NULL;\n-\tif (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {\n-\t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n-\t\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n-\t\tLIST_REMOVE(rxq_ctrl, next);\n-\t\tmlx5_free(rxq_ctrl);\n-\t\t(*priv->rxqs)[idx] = NULL;\n-\t\treturn 0;\n \t}\n-\treturn 1;\n+\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n+\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n+\tLIST_REMOVE(rxq_ctrl, next);\n+\tmlx5_free(rxq_ctrl);\n+\t(*priv->rxqs)[idx] = NULL;\n+\treturn 0;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex a161d4e..b092e43 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -171,7 +171,6 @@ enum mlx5_rxq_type {\n /* Verbs/DevX Rx queue elements. */\n struct mlx5_rxq_obj {\n \tLIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */\n-\trte_atomic32_t refcnt; /* Reference counter. */\n \tstruct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */\n \tenum mlx5_rxq_obj_type type;\n \tint fd; /* File descriptor for event channel */\n", "prefixes": [ "v1", "04/18" ] }