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GET /api/patches/76270/?format=api
{ "id": 76270, "url": "http://patches.dpdk.org/api/patches/76270/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/714d4c5376dd16f4e35712153f26899369331a64.1598979347.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<714d4c5376dd16f4e35712153f26899369331a64.1598979347.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/714d4c5376dd16f4e35712153f26899369331a64.1598979347.git.rahul.lakkireddy@chelsio.com", "date": "2020-09-01T17:16:25", "name": "[1/2] net/cxgbe: fix queue DMA ring leaks during port close", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "37702e4edc9d8c1cc91417936dc0182ca2c07dc5", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/714d4c5376dd16f4e35712153f26899369331a64.1598979347.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [ { "id": 11881, "url": "http://patches.dpdk.org/api/series/11881/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11881", "date": "2020-09-01T17:16:24", "name": "net/cxgbe: release port resources during port close", "version": 1, "mbox": "http://patches.dpdk.org/series/11881/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76270/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76270/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBEA3A04AC;\n\tTue, 1 Sep 2020 19:30:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9200E1C0BC;\n\tTue, 1 Sep 2020 19:30:51 +0200 (CEST)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n by dpdk.org (Postfix) with ESMTP id CE6811C0B9;\n Tue, 1 Sep 2020 19:30:49 +0200 (CEST)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id 081HUlex013784;\n Tue, 1 Sep 2020 10:30:47 -0700" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "kaara.satwik@chelsio.com, stable@dpdk.org", "Date": "Tue, 1 Sep 2020 22:46:25 +0530", "Message-Id": "\n <714d4c5376dd16f4e35712153f26899369331a64.1598979347.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1598979347.git.rahul.lakkireddy@chelsio.com>", "<cover.1598979347.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1598979347.git.rahul.lakkireddy@chelsio.com>", "<cover.1598979347.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 1/2] net/cxgbe: fix queue DMA ring leaks during\n\tport close", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Free up the DMA memzones properly for all the port's queues during\nport close. So, rework DMA ring allocation/free logic to use\nrte_eth_dma_zone_reserve()/rte_eth_dma_zone_free() helper functions\nfor allocating/freeing the memzones.\n\nThe firmware event queue doesn't have an associated freelist queue.\nSo, remove check that tries to give memzone name for a non-existent\nfreelist queue.\n\nAlso, add a missing free for the control queue mempools.\n\nFixes: 0462d115441d (\"cxgbe: add device related operations\")\nCc: stable@dpdk.org\n\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n drivers/net/cxgbe/base/adapter.h | 1 +\n drivers/net/cxgbe/cxgbe_ethdev.c | 7 +-\n drivers/net/cxgbe/sge.c | 144 +++++++++++++++----------------\n 3 files changed, 70 insertions(+), 82 deletions(-)", "diff": "diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h\nindex 62de35c7c..3e74177f2 100644\n--- a/drivers/net/cxgbe/base/adapter.h\n+++ b/drivers/net/cxgbe/base/adapter.h\n@@ -825,6 +825,7 @@ int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);\n int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);\n void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);\n void t4_sge_eth_clear_queues(struct port_info *pi);\n+void t4_sge_eth_release_queues(struct port_info *pi);\n int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n \t\t\t unsigned int cnt);\n int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,\ndiff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c\nindex 7c6016d5c..913af2df7 100644\n--- a/drivers/net/cxgbe/cxgbe_ethdev.c\n+++ b/drivers/net/cxgbe/cxgbe_ethdev.c\n@@ -326,12 +326,7 @@ void cxgbe_dev_close(struct rte_eth_dev *eth_dev)\n \t\treturn;\n \n \tcxgbe_down(pi);\n-\n-\t/*\n-\t * We clear queues only if both tx and rx path of the port\n-\t * have been disabled\n-\t */\n-\tt4_sge_eth_clear_queues(pi);\n+\tt4_sge_eth_release_queues(pi);\n }\n \n /* Start the device.\ndiff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c\nindex aba85a209..34e48574a 100644\n--- a/drivers/net/cxgbe/sge.c\n+++ b/drivers/net/cxgbe/sge.c\n@@ -1423,14 +1423,16 @@ int t4_mgmt_tx(struct sge_ctrl_txq *q, struct rte_mbuf *mbuf)\n \n /**\n * alloc_ring - allocate resources for an SGE descriptor ring\n- * @dev: the PCI device's core device\n+ * @dev: the port associated with the queue\n+ * @z_name: memzone's name\n+ * @queue_id: queue index\n+ * @socket_id: preferred socket id for memory allocations\n * @nelem: the number of descriptors\n * @elem_size: the size of each descriptor\n+ * @stat_size: extra space in HW ring for status information\n * @sw_size: the size of the SW state associated with each ring element\n * @phys: the physical address of the allocated ring\n * @metadata: address of the array holding the SW state for the ring\n- * @stat_size: extra space in HW ring for status information\n- * @node: preferred node for memory allocations\n *\n * Allocates resources for an SGE descriptor ring, such as Tx queues,\n * free buffer lists, or response queues. Each SGE ring requires\n@@ -1440,39 +1442,34 @@ int t4_mgmt_tx(struct sge_ctrl_txq *q, struct rte_mbuf *mbuf)\n * of the function), the bus address of the HW ring, and the address\n * of the SW ring.\n */\n-static void *alloc_ring(size_t nelem, size_t elem_size,\n-\t\t\tsize_t sw_size, dma_addr_t *phys, void *metadata,\n-\t\t\tsize_t stat_size, __rte_unused uint16_t queue_id,\n-\t\t\tint socket_id, const char *z_name,\n-\t\t\tconst char *z_name_sw)\n+static void *alloc_ring(struct rte_eth_dev *dev, const char *z_name,\n+\t\t\tuint16_t queue_id, int socket_id, size_t nelem,\n+\t\t\tsize_t elem_size, size_t stat_size, size_t sw_size,\n+\t\t\tdma_addr_t *phys, void *metadata)\n {\n \tsize_t len = CXGBE_MAX_RING_DESC_SIZE * elem_size + stat_size;\n+\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n \tconst struct rte_memzone *tz;\n \tvoid *s = NULL;\n \n+\tsnprintf(z_name_sw, sizeof(z_name_sw), \"eth_p%d_q%d_%s_sw_ring\",\n+\t\t dev->data->port_id, queue_id, z_name);\n+\n \tdev_debug(adapter, \"%s: nelem = %zu; elem_size = %zu; sw_size = %zu; \"\n \t\t \"stat_size = %zu; queue_id = %u; socket_id = %d; z_name = %s;\"\n \t\t \" z_name_sw = %s\\n\", __func__, nelem, elem_size, sw_size,\n \t\t stat_size, queue_id, socket_id, z_name, z_name_sw);\n \n-\ttz = rte_memzone_lookup(z_name);\n-\tif (tz) {\n-\t\tdev_debug(adapter, \"%s: tz exists...returning existing..\\n\",\n-\t\t\t __func__);\n-\t\tgoto alloc_sw_ring;\n-\t}\n-\n \t/*\n \t * Allocate TX/RX ring hardware descriptors. A memzone large enough to\n \t * handle the maximum ring size is allocated in order to allow for\n \t * resizing in later calls to the queue setup function.\n \t */\n-\ttz = rte_memzone_reserve_aligned(z_name, len, socket_id,\n-\t\t\tRTE_MEMZONE_IOVA_CONTIG, 4096);\n+\ttz = rte_eth_dma_zone_reserve(dev, z_name, queue_id, len, 4096,\n+\t\t\t\t socket_id);\n \tif (!tz)\n \t\treturn NULL;\n \n-alloc_sw_ring:\n \tmemset(tz->addr, 0, len);\n \tif (sw_size) {\n \t\ts = rte_zmalloc_socket(z_name_sw, nelem * sw_size,\n@@ -1788,21 +1785,15 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,\n \tstruct fw_iq_cmd c;\n \tstruct sge *s = &adap->sge;\n \tstruct port_info *pi = eth_dev->data->dev_private;\n-\tchar z_name[RTE_MEMZONE_NAMESIZE];\n-\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n \tunsigned int nb_refill;\n \tu8 pciechan;\n \n \t/* Size needs to be multiple of 16, including status entry. */\n \tiq->size = cxgbe_roundup(iq->size, 16);\n \n-\tsnprintf(z_name, sizeof(z_name), \"eth_p%d_q%d_%s\",\n-\t\t\teth_dev->data->port_id, queue_id,\n-\t\t\tfwevtq ? \"fwq_ring\" : \"rx_ring\");\n-\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n-\n-\tiq->desc = alloc_ring(iq->size, iq->iqe_len, 0, &iq->phys_addr, NULL, 0,\n-\t\t\t queue_id, socket_id, z_name, z_name_sw);\n+\tiq->desc = alloc_ring(eth_dev, fwevtq ? \"fwq_ring\" : \"rx_ring\",\n+\t\t\t queue_id, socket_id, iq->size, iq->iqe_len,\n+\t\t\t 0, 0, &iq->phys_addr, NULL);\n \tif (!iq->desc)\n \t\treturn -ENOMEM;\n \n@@ -1860,18 +1851,14 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,\n \t\t\tfl->size = s->fl_starve_thres - 1 + 2 * 8;\n \t\tfl->size = cxgbe_roundup(fl->size, 8);\n \n-\t\tsnprintf(z_name, sizeof(z_name), \"eth_p%d_q%d_%s\",\n-\t\t\t\teth_dev->data->port_id, queue_id,\n-\t\t\t\tfwevtq ? \"fwq_ring\" : \"fl_ring\");\n-\t\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n-\n-\t\tfl->desc = alloc_ring(fl->size, sizeof(__be64),\n+\t\tfl->desc = alloc_ring(eth_dev, \"fl_ring\", queue_id, socket_id,\n+\t\t\t\t fl->size, sizeof(__be64), s->stat_len,\n \t\t\t\t sizeof(struct rx_sw_desc),\n-\t\t\t\t &fl->addr, &fl->sdesc, s->stat_len,\n-\t\t\t\t queue_id, socket_id, z_name, z_name_sw);\n-\n-\t\tif (!fl->desc)\n-\t\t\tgoto fl_nomem;\n+\t\t\t\t &fl->addr, &fl->sdesc);\n+\t\tif (!fl->desc) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto err;\n+\t\t}\n \n \t\tflsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);\n \t\tc.iqns_to_fl0congen |=\n@@ -1991,8 +1978,6 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,\n refill_fl_err:\n \tt4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,\n \t\t iq->cntxt_id, fl->cntxt_id, 0xffff);\n-fl_nomem:\n-\tret = -ENOMEM;\n err:\n \tiq->cntxt_id = 0;\n \tiq->abs_id = 0;\n@@ -2058,21 +2043,15 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,\n \tstruct fw_eq_eth_cmd c;\n \tstruct sge *s = &adap->sge;\n \tstruct port_info *pi = eth_dev->data->dev_private;\n-\tchar z_name[RTE_MEMZONE_NAMESIZE];\n-\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n \tu8 pciechan;\n \n \t/* Add status entries */\n \tnentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);\n \n-\tsnprintf(z_name, sizeof(z_name), \"eth_p%d_q%d_%s\",\n-\t\t\teth_dev->data->port_id, queue_id, \"tx_ring\");\n-\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n-\n-\ttxq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),\n-\t\t\t\t sizeof(struct tx_sw_desc), &txq->q.phys_addr,\n-\t\t\t\t &txq->q.sdesc, s->stat_len, queue_id,\n-\t\t\t\t socket_id, z_name, z_name_sw);\n+\ttxq->q.desc = alloc_ring(eth_dev, \"tx_ring\", queue_id, socket_id,\n+\t\t\t\t txq->q.size, sizeof(struct tx_desc),\n+\t\t\t\t s->stat_len, sizeof(struct tx_sw_desc),\n+\t\t\t\t &txq->q.phys_addr, &txq->q.sdesc);\n \tif (!txq->q.desc)\n \t\treturn -ENOMEM;\n \n@@ -2137,20 +2116,13 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,\n \tstruct fw_eq_ctrl_cmd c;\n \tstruct sge *s = &adap->sge;\n \tstruct port_info *pi = eth_dev->data->dev_private;\n-\tchar z_name[RTE_MEMZONE_NAMESIZE];\n-\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n \n \t/* Add status entries */\n \tnentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);\n \n-\tsnprintf(z_name, sizeof(z_name), \"eth_p%d_q%d_%s\",\n-\t\t\teth_dev->data->port_id, queue_id, \"ctrl_tx_ring\");\n-\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n-\n-\ttxq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),\n-\t\t\t\t 0, &txq->q.phys_addr,\n-\t\t\t\t NULL, 0, queue_id,\n-\t\t\t\t socket_id, z_name, z_name_sw);\n+\ttxq->q.desc = alloc_ring(eth_dev, \"ctrl_tx_ring\", queue_id,\n+\t\t\t\t socket_id, txq->q.size, sizeof(struct tx_desc),\n+\t\t\t\t 0, 0, &txq->q.phys_addr, NULL);\n \tif (!txq->q.desc)\n \t\treturn -ENOMEM;\n \n@@ -2262,6 +2234,36 @@ void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq)\n \t}\n }\n \n+void t4_sge_eth_release_queues(struct port_info *pi)\n+{\n+\tstruct adapter *adap = pi->adapter;\n+\tstruct sge_eth_rxq *rxq;\n+\tstruct sge_eth_txq *txq;\n+\tunsigned int i;\n+\n+\trxq = &adap->sge.ethrxq[pi->first_qset];\n+\t/* clean up Ethernet Tx/Rx queues */\n+\tfor (i = 0; i < pi->n_rx_qsets; i++, rxq++) {\n+\t\t/* Free only the queues allocated */\n+\t\tif (rxq->rspq.desc) {\n+\t\t\tt4_sge_eth_rxq_release(adap, rxq);\n+\t\t\trte_eth_dma_zone_free(rxq->rspq.eth_dev, \"fl_ring\", i);\n+\t\t\trte_eth_dma_zone_free(rxq->rspq.eth_dev, \"rx_ring\", i);\n+\t\t\trxq->rspq.eth_dev = NULL;\n+\t\t}\n+\t}\n+\n+\ttxq = &adap->sge.ethtxq[pi->first_qset];\n+\tfor (i = 0; i < pi->n_tx_qsets; i++, txq++) {\n+\t\t/* Free only the queues allocated */\n+\t\tif (txq->q.desc) {\n+\t\t\tt4_sge_eth_txq_release(adap, txq);\n+\t\t\trte_eth_dma_zone_free(txq->eth_dev, \"tx_ring\", i);\n+\t\t\ttxq->eth_dev = NULL;\n+\t\t}\n+\t}\n+}\n+\n void t4_sge_tx_monitor_start(struct adapter *adap)\n {\n \trte_eal_alarm_set(50, tx_timer_cb, (void *)adap);\n@@ -2281,21 +2283,6 @@ void t4_sge_tx_monitor_stop(struct adapter *adap)\n void t4_free_sge_resources(struct adapter *adap)\n {\n \tunsigned int i;\n-\tstruct sge_eth_rxq *rxq = &adap->sge.ethrxq[0];\n-\tstruct sge_eth_txq *txq = &adap->sge.ethtxq[0];\n-\n-\t/* clean up Ethernet Tx/Rx queues */\n-\tfor (i = 0; i < adap->sge.max_ethqsets; i++, rxq++, txq++) {\n-\t\t/* Free only the queues allocated */\n-\t\tif (rxq->rspq.desc) {\n-\t\t\tt4_sge_eth_rxq_release(adap, rxq);\n-\t\t\trxq->rspq.eth_dev = NULL;\n-\t\t}\n-\t\tif (txq->q.desc) {\n-\t\t\tt4_sge_eth_txq_release(adap, txq);\n-\t\t\ttxq->eth_dev = NULL;\n-\t\t}\n-\t}\n \n \t/* clean up control Tx queues */\n \tfor (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {\n@@ -2305,12 +2292,17 @@ void t4_free_sge_resources(struct adapter *adap)\n \t\t\treclaim_completed_tx_imm(&cq->q);\n \t\t\tt4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0,\n \t\t\t\t\tcq->q.cntxt_id);\n+\t\t\trte_eth_dma_zone_free(adap->eth_dev, \"ctrl_tx_ring\", i);\n+\t\t\trte_mempool_free(cq->mb_pool);\n \t\t\tfree_txq(&cq->q);\n \t\t}\n \t}\n \n-\tif (adap->sge.fw_evtq.desc)\n+\t/* clean up firmware event queue */\n+\tif (adap->sge.fw_evtq.desc) {\n \t\tfree_rspq_fl(adap, &adap->sge.fw_evtq, NULL);\n+\t\trte_eth_dma_zone_free(adap->eth_dev, \"fwq_ring\", 0);\n+\t}\n }\n \n /**\n", "prefixes": [ "1/2" ] }