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GET /api/patches/76017/?format=api
{ "id": 76017, "url": "http://patches.dpdk.org/api/patches/76017/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200826151445.51500-23-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200826151445.51500-23-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200826151445.51500-23-cristian.dumitrescu@intel.com", "date": "2020-08-26T15:14:27", "name": "[22/40] pipeline: introduce shr instruction", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "126c618a52c03da15411e653fd0da52e99f9bc73", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200826151445.51500-23-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 11806, "url": "http://patches.dpdk.org/api/series/11806/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11806", "date": "2020-08-26T15:14:05", "name": "Pipeline alignment with the P4 language", "version": 1, "mbox": "http://patches.dpdk.org/series/11806/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76017/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76017/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9B475A04B1;\n\tWed, 26 Aug 2020 17:19:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9615A1C1B2;\n\tWed, 26 Aug 2020 17:15:36 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 6A4DC1C002\n for <dev@dpdk.org>; Wed, 26 Aug 2020 17:15:10 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Aug 2020 08:15:09 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by orsmga004.jf.intel.com with ESMTP; 26 Aug 2020 08:15:09 -0700" ], "IronPort-SDR": [ "\n Tt0MSxsDuTja69wSK63tYtmhwtWuvkBRyYdxOUc6gwZqJ5yFPuhKqmPxSphckLBpREWK5+d4F7\n nx14CIhOBouQ==", "\n svStI7RL9dnuaBN7Vcx/1wgWdvPPwM3kBlJwdSSpTPePdY21T3JGe/sVT6f9rp6KEWYZ7pz/Km\n BOuWKHdMOUMw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9725\"; a=\"153879569\"", "E=Sophos;i=\"5.76,356,1592895600\"; d=\"scan'208\";a=\"153879569\"", "E=Sophos;i=\"5.76,356,1592895600\"; d=\"scan'208\";a=\"444081389\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Wed, 26 Aug 2020 16:14:27 +0100", "Message-Id": "<20200826151445.51500-23-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200826151445.51500-1-cristian.dumitrescu@intel.com>", "References": "<20200826151445.51500-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH 22/40] pipeline: introduce shr instruction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The shr (i.e. shift right) instruction source can be header field (H),\nmeta-data field (M), extern object (E) or function (F) mailbox field,\ntable entry action data field (T) or immediate value (I). The\ndestination is HMEF.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_swx_pipeline.c | 168 +++++++++++++++++++++++++\n 1 file changed, 168 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex c22bc007c..0c0490eef 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -338,6 +338,17 @@ enum instruction_type {\n \tINSTR_ALU_SHL_HH, /* dst = H, src = H */\n \tINSTR_ALU_SHL_MI, /* dst = MEF, src = I */\n \tINSTR_ALU_SHL_HI, /* dst = H, src = I */\n+\n+\t/* shr dst src\n+\t * dst >>= src\n+\t * dst = HMEF, src = HMEFTI\n+\t */\n+\tINSTR_ALU_SHR, /* dst = MEF, src = MEF */\n+\tINSTR_ALU_SHR_MH, /* dst = MEF, src = H */\n+\tINSTR_ALU_SHR_HM, /* dst = H, src = MEF */\n+\tINSTR_ALU_SHR_HH, /* dst = H, src = H */\n+\tINSTR_ALU_SHR_MI, /* dst = MEF, src = I */\n+\tINSTR_ALU_SHR_HI, /* dst = H, src = I */\n };\n \n struct instr_operand {\n@@ -3157,6 +3168,58 @@ instr_alu_shl_translate(struct rte_swx_pipeline *p,\n \treturn 0;\n }\n \n+static int\n+instr_alu_shr_translate(struct rte_swx_pipeline *p,\n+\t\t\tstruct action *action,\n+\t\t\tchar **tokens,\n+\t\t\tint n_tokens,\n+\t\t\tstruct instruction *instr,\n+\t\t\tstruct instruction_data *data __rte_unused)\n+{\n+\tchar *dst = tokens[1], *src = tokens[2];\n+\tstruct field *fdst, *fsrc;\n+\tuint32_t dst_struct_id, src_struct_id, src_val;\n+\n+\tCHECK(n_tokens == 3, EINVAL);\n+\n+\tfdst = struct_field_parse(p, NULL, dst, &dst_struct_id);\n+\tCHECK(fdst, EINVAL);\n+\n+\t/* SHR, SHR_HM, SHR_MH, SHR_HH. */\n+\tfsrc = struct_field_parse(p, action, src, &src_struct_id);\n+\tif (fsrc) {\n+\t\tinstr->type = INSTR_ALU_SHR;\n+\t\tif (dst[0] == 'h' && src[0] == 'm')\n+\t\t\tinstr->type = INSTR_ALU_SHR_HM;\n+\t\tif (dst[0] == 'm' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_SHR_MH;\n+\t\tif (dst[0] == 'h' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_SHR_HH;\n+\n+\t\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\t\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\t\tinstr->alu.dst.offset = fdst->offset / 8;\n+\t\tinstr->alu.src.struct_id = (uint8_t)src_struct_id;\n+\t\tinstr->alu.src.n_bits = fsrc->n_bits;\n+\t\tinstr->alu.src.offset = fsrc->offset / 8;\n+\t\treturn 0;\n+\t}\n+\n+\t/* SHR_MI, SHR_HI. */\n+\tsrc_val = strtoul(src, &src, 0);\n+\tCHECK(!src[0], EINVAL);\n+\n+\tinstr->type = INSTR_ALU_SHR_MI;\n+\tif (dst[0] == 'h')\n+\t\tinstr->type = INSTR_ALU_SHR_HI;\n+\n+\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\tinstr->alu.dst.offset = fdst->offset / 8;\n+\tinstr->alu.src_val = (uint32_t)src_val;\n+\treturn 0;\n+}\n+\n static int\n instr_alu_and_translate(struct rte_swx_pipeline *p,\n \t\t\tstruct action *action,\n@@ -3574,6 +3637,96 @@ instr_alu_shl_hi_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+static inline void\n+instr_alu_shr_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shr_mh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr (mh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MH(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shr_hm_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr (hm)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HM(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shr_hh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr (hh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HH(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shr_mi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr (mi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MI(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_shr_hi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] shr (hi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HI(t, ip, >>);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n static inline void\n instr_alu_and_exec(struct rte_swx_pipeline *p)\n {\n@@ -4108,6 +4261,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t instr,\n \t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"shr\"))\n+\t\treturn instr_alu_shr_translate(p,\n+\t\t\t\t\t action,\n+\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t instr,\n+\t\t\t\t\t data);\n+\n \tCHECK(0, EINVAL);\n }\n \n@@ -4303,6 +4464,13 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_ALU_SHL_HH] = instr_alu_shl_hh_exec,\n \t[INSTR_ALU_SHL_MI] = instr_alu_shl_mi_exec,\n \t[INSTR_ALU_SHL_HI] = instr_alu_shl_hi_exec,\n+\n+\t[INSTR_ALU_SHR] = instr_alu_shr_exec,\n+\t[INSTR_ALU_SHR_MH] = instr_alu_shr_mh_exec,\n+\t[INSTR_ALU_SHR_HM] = instr_alu_shr_hm_exec,\n+\t[INSTR_ALU_SHR_HH] = instr_alu_shr_hh_exec,\n+\t[INSTR_ALU_SHR_MI] = instr_alu_shr_mi_exec,\n+\t[INSTR_ALU_SHR_HI] = instr_alu_shr_hi_exec,\n };\n \n static inline void\n", "prefixes": [ "22/40" ] }