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GET /api/patches/75654/?format=api
{ "id": 75654, "url": "http://patches.dpdk.org/api/patches/75654/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1597791894-37041-11-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1597791894-37041-11-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1597791894-37041-11-git-send-email-nicolas.chautru@intel.com", "date": "2020-08-18T23:04:53", "name": "[v2,10/11] baseband/acc100: add configure function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e02c0c147d3eea4481b3ac1b3e7416696ab65dac", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1597791894-37041-11-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 11695, "url": "http://patches.dpdk.org/api/series/11695/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11695", "date": "2020-08-18T23:04:43", "name": "bbdev PMD ACC100", "version": 2, "mbox": "http://patches.dpdk.org/series/11695/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/75654/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/75654/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DCC26A04AF;\n\tWed, 19 Aug 2020 01:08:40 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DC5711C12F;\n\tWed, 19 Aug 2020 01:07:01 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 96DC91C031\n for <dev@dpdk.org>; Wed, 19 Aug 2020 01:06:48 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Aug 2020 16:06:44 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga004.jf.intel.com with ESMTP; 18 Aug 2020 16:06:44 -0700" ], "IronPort-SDR": [ "\n Vv23j8j2t2n2jCh/b3ROvh6J/9G1l/S2oS/ICkk3aOqRvBWxL2p2DTjzDGyeG/WaSWMyXp5LVN\n MfaM4VcPMi6g==", "\n kSX5mM8Fxd0cPRRC3yylSp2IGY12AcCpE6ESAbMgY3UA8gZXqTUif5BIqspgxFTKSvQ0RJz/VH\n 3Ek5nKmaJnSQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9717\"; a=\"154281365\"", "E=Sophos;i=\"5.76,329,1592895600\"; d=\"scan'208\";a=\"154281365\"", "E=Sophos;i=\"5.76,329,1592895600\"; d=\"scan'208\";a=\"441400718\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Tue, 18 Aug 2020 16:04:53 -0700", "Message-Id": "<1597791894-37041-11-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1597791894-37041-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1597791894-37041-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 10/11] baseband/acc100: add configure function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add configure function to configure the PF from within\nthe bbdev-test itself without external application\nconfiguration the device.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/test_bbdev_perf.c | 72 +++\n drivers/baseband/acc100/Makefile | 3 +\n drivers/baseband/acc100/meson.build | 2 +\n drivers/baseband/acc100/rte_acc100_cfg.h | 17 +\n drivers/baseband/acc100/rte_acc100_pmd.c | 505 +++++++++++++++++++++\n .../acc100/rte_pmd_bbdev_acc100_version.map | 7 +\n 6 files changed, 606 insertions(+)", "diff": "diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex 45c0d62..32f23ff 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -52,6 +52,18 @@\n #define FLR_5G_TIMEOUT 610\n #endif\n \n+#ifdef RTE_LIBRTE_PMD_BBDEV_ACC100\n+#include <rte_acc100_cfg.h>\n+#define ACC100PF_DRIVER_NAME (\"intel_acc100_pf\")\n+#define ACC100VF_DRIVER_NAME (\"intel_acc100_vf\")\n+#define ACC100_QMGR_NUM_AQS 16\n+#define ACC100_QMGR_NUM_QGS 2\n+#define ACC100_QMGR_AQ_DEPTH 5\n+#define ACC100_QMGR_INVALID_IDX -1\n+#define ACC100_QMGR_RR 1\n+#define ACC100_QOS_GBR 0\n+#endif\n+\n #define OPS_CACHE_SIZE 256U\n #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */\n \n@@ -653,6 +665,66 @@ typedef int (test_case_function)(struct active_device *ad,\n \t\t\t\tinfo->dev_name);\n \t}\n #endif\n+#ifdef RTE_LIBRTE_PMD_BBDEV_ACC100\n+\tif ((get_init_device() == true) &&\n+\t\t(!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {\n+\t\tstruct acc100_conf conf;\n+\t\tunsigned int i;\n+\n+\t\tprintf(\"Configure ACC100 FEC Driver %s with default values\\n\",\n+\t\t\t\tinfo->drv.driver_name);\n+\n+\t\t/* clear default configuration before initialization */\n+\t\tmemset(&conf, 0, sizeof(struct acc100_conf));\n+\n+\t\t/* Always set in PF mode for built-in configuration */\n+\t\tconf.pf_mode_en = true;\n+\t\tfor (i = 0; i < RTE_ACC100_NUM_VFS; ++i) {\n+\t\t\tconf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_dl_4g[i].round_robin_weight = ACC100_QMGR_RR;\n+\t\t\tconf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_ul_4g[i].round_robin_weight = ACC100_QMGR_RR;\n+\t\t\tconf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_dl_5g[i].round_robin_weight = ACC100_QMGR_RR;\n+\t\t\tconf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;\n+\t\t\tconf.arb_ul_5g[i].round_robin_weight = ACC100_QMGR_RR;\n+\t\t}\n+\n+\t\tconf.input_pos_llr_1_bit = true;\n+\t\tconf.output_pos_llr_1_bit = true;\n+\t\tconf.num_vf_bundles = 1; /**< Number of VF bundles to setup */\n+\n+\t\tconf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS;\n+\t\tconf.q_ul_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;\n+\t\tconf.q_ul_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;\n+\t\tconf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;\n+\t\tconf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS;\n+\t\tconf.q_dl_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;\n+\t\tconf.q_dl_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;\n+\t\tconf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;\n+\t\tconf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS;\n+\t\tconf.q_ul_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;\n+\t\tconf.q_ul_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;\n+\t\tconf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;\n+\t\tconf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS;\n+\t\tconf.q_dl_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;\n+\t\tconf.q_dl_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;\n+\t\tconf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;\n+\n+\t\t/* setup PF with configuration information */\n+\t\tret = acc100_configure(info->dev_name, &conf);\n+\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\"Failed to configure ACC100 PF for bbdev %s\",\n+\t\t\t\tinfo->dev_name);\n+\t\t/* Let's refresh this now this is configured */\n+\t}\n+\trte_bbdev_info_get(dev_id, info);\n+#endif\n+\n \tnb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);\n \tnb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES);\n \ndiff --git a/drivers/baseband/acc100/Makefile b/drivers/baseband/acc100/Makefile\nindex c79e487..37e73af 100644\n--- a/drivers/baseband/acc100/Makefile\n+++ b/drivers/baseband/acc100/Makefile\n@@ -22,4 +22,7 @@ LIBABIVER := 1\n # library source files\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_ACC100) += rte_acc100_pmd.c\n \n+# export include files\n+SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_ACC100)-include += rte_acc100_cfg.h\n+\n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/baseband/acc100/meson.build b/drivers/baseband/acc100/meson.build\nindex 8afafc2..7ac44dc 100644\n--- a/drivers/baseband/acc100/meson.build\n+++ b/drivers/baseband/acc100/meson.build\n@@ -4,3 +4,5 @@\n deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']\n \n sources = files('rte_acc100_pmd.c')\n+\n+install_headers('rte_acc100_cfg.h')\ndiff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h\nindex 73bbe36..7f523bc 100644\n--- a/drivers/baseband/acc100/rte_acc100_cfg.h\n+++ b/drivers/baseband/acc100/rte_acc100_cfg.h\n@@ -89,6 +89,23 @@ struct acc100_conf {\n \tstruct rte_arbitration_t arb_dl_5g[RTE_ACC100_NUM_VFS];\n };\n \n+/**\n+ * Configure a ACC100 device\n+ *\n+ * @param dev_name\n+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n+ * It can also be retrieved for a bbdev device from the dev_name field in the\n+ * rte_bbdev_info structure returned by rte_bbdev_info_get().\n+ * @param conf\n+ * Configuration to apply to ACC100 HW.\n+ *\n+ * @return\n+ * Zero on success, negative value on failure.\n+ */\n+__rte_experimental\n+int\n+acc100_configure(const char *dev_name, struct acc100_conf *conf);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c\nindex dc14079..43f664b 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.c\n@@ -85,6 +85,26 @@\n \n enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, NUM_ACC};\n \n+/* Return the accelerator enum for a Queue Group Index */\n+static inline int\n+accFromQgid(int qg_idx, const struct acc100_conf *acc100_conf)\n+{\n+\tint accQg[ACC100_NUM_QGRPS];\n+\tint NumQGroupsPerFn[NUM_ACC];\n+\tint acc, qgIdx, qgIndex = 0;\n+\tfor (qgIdx = 0; qgIdx < ACC100_NUM_QGRPS; qgIdx++)\n+\t\taccQg[qgIdx] = 0;\n+\tNumQGroupsPerFn[UL_4G] = acc100_conf->q_ul_4g.num_qgroups;\n+\tNumQGroupsPerFn[UL_5G] = acc100_conf->q_ul_5g.num_qgroups;\n+\tNumQGroupsPerFn[DL_4G] = acc100_conf->q_dl_4g.num_qgroups;\n+\tNumQGroupsPerFn[DL_5G] = acc100_conf->q_dl_5g.num_qgroups;\n+\tfor (acc = UL_4G; acc < NUM_ACC; acc++)\n+\t\tfor (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)\n+\t\t\taccQg[qgIndex++] = acc;\n+\tacc = accQg[qg_idx];\n+\treturn acc;\n+}\n+\n /* Return the queue topology for a Queue Group Index */\n static inline void\n qtopFromAcc(struct rte_q_topology_t **qtop, int acc_enum,\n@@ -113,6 +133,30 @@\n \t*qtop = p_qtop;\n }\n \n+/* Return the AQ depth for a Queue Group Index */\n+static inline int\n+aqDepth(int qg_idx, struct acc100_conf *acc100_conf)\n+{\n+\tstruct rte_q_topology_t *q_top = NULL;\n+\tint acc_enum = accFromQgid(qg_idx, acc100_conf);\n+\tqtopFromAcc(&q_top, acc_enum, acc100_conf);\n+\tif (unlikely(q_top == NULL))\n+\t\treturn 0;\n+\treturn q_top->aq_depth_log2;\n+}\n+\n+/* Return the AQ depth for a Queue Group Index */\n+static inline int\n+aqNum(int qg_idx, struct acc100_conf *acc100_conf)\n+{\n+\tstruct rte_q_topology_t *q_top = NULL;\n+\tint acc_enum = accFromQgid(qg_idx, acc100_conf);\n+\tqtopFromAcc(&q_top, acc_enum, acc100_conf);\n+\tif (unlikely(q_top == NULL))\n+\t\treturn 0;\n+\treturn q_top->num_aqs_per_groups;\n+}\n+\n static void\n initQTop(struct acc100_conf *acc100_conf)\n {\n@@ -4177,3 +4221,464 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n RTE_PMD_REGISTER_PCI_TABLE(ACC100PF_DRIVER_NAME, pci_id_acc100_pf_map);\n RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);\n RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);\n+\n+/*\n+ * Implementation to fix the power on status of some 5GUL engines\n+ * This requires DMA permission if ported outside DPDK\n+ */\n+static void\n+poweron_cleanup(struct rte_bbdev *bbdev, struct acc100_device *d,\n+\t\tstruct acc100_conf *conf)\n+{\n+\tint i, template_idx, qg_idx;\n+\tuint32_t address, status, payload;\n+\tprintf(\"Need to clear power-on 5GUL status in internal memory\\n\");\n+\t/* Reset LDPC Cores */\n+\tfor (i = 0; i < ACC100_ENGINES_MAX; i++)\n+\t\tacc100_reg_write(d, HWPfFecUl5gCntrlReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * i, ACC100_RESET_HI);\n+\tusleep(LONG_WAIT);\n+\tfor (i = 0; i < ACC100_ENGINES_MAX; i++)\n+\t\tacc100_reg_write(d, HWPfFecUl5gCntrlReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * i, ACC100_RESET_LO);\n+\tusleep(LONG_WAIT);\n+\t/* Prepare dummy workload */\n+\talloc_2x64mb_sw_rings_mem(bbdev, d, 0);\n+\t/* Set base addresses */\n+\tuint32_t phys_high = (uint32_t)(d->sw_rings_phys >> 32);\n+\tuint32_t phys_low = (uint32_t)(d->sw_rings_phys &\n+\t\t\t~(ACC100_SIZE_64MBYTE-1));\n+\tacc100_reg_write(d, HWPfDmaFec5GulDescBaseHiRegVf, phys_high);\n+\tacc100_reg_write(d, HWPfDmaFec5GulDescBaseLoRegVf, phys_low);\n+\n+\t/* Descriptor for a dummy 5GUL code block processing*/\n+\tunion acc100_dma_desc *desc = NULL;\n+\tdesc = d->sw_rings;\n+\tdesc->req.data_ptrs[0].address = d->sw_rings_phys +\n+\t\t\tACC100_DESC_FCW_OFFSET;\n+\tdesc->req.data_ptrs[0].blen = ACC100_FCW_LD_BLEN;\n+\tdesc->req.data_ptrs[0].blkid = ACC100_DMA_BLKID_FCW;\n+\tdesc->req.data_ptrs[0].last = 0;\n+\tdesc->req.data_ptrs[0].dma_ext = 0;\n+\tdesc->req.data_ptrs[1].address = d->sw_rings_phys + 512;\n+\tdesc->req.data_ptrs[1].blkid = ACC100_DMA_BLKID_IN;\n+\tdesc->req.data_ptrs[1].last = 1;\n+\tdesc->req.data_ptrs[1].dma_ext = 0;\n+\tdesc->req.data_ptrs[1].blen = 44;\n+\tdesc->req.data_ptrs[2].address = d->sw_rings_phys + 1024;\n+\tdesc->req.data_ptrs[2].blkid = ACC100_DMA_BLKID_OUT_ENC;\n+\tdesc->req.data_ptrs[2].last = 1;\n+\tdesc->req.data_ptrs[2].dma_ext = 0;\n+\tdesc->req.data_ptrs[2].blen = 5;\n+\t/* Dummy FCW */\n+\tdesc->req.fcw_ld.FCWversion = ACC100_FCW_VER;\n+\tdesc->req.fcw_ld.qm = 1;\n+\tdesc->req.fcw_ld.nfiller = 30;\n+\tdesc->req.fcw_ld.BG = 2 - 1;\n+\tdesc->req.fcw_ld.Zc = 7;\n+\tdesc->req.fcw_ld.ncb = 350;\n+\tdesc->req.fcw_ld.rm_e = 4;\n+\tdesc->req.fcw_ld.itmax = 10;\n+\tdesc->req.fcw_ld.gain_i = 1;\n+\tdesc->req.fcw_ld.gain_h = 1;\n+\n+\tint engines_to_restart[SIG_UL_5G_LAST + 1] = {0};\n+\tint num_failed_engine = 0;\n+\t/* Detect engines in undefined state */\n+\tfor (template_idx = SIG_UL_5G; template_idx <= SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\t/* Check engine power-on status */\n+\t\taddress = HwPfFecUl5gIbDebugReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc100_reg_read(d, address) >> 4) & 0xF;\n+\t\tif (status == 0) {\n+\t\t\tengines_to_restart[num_failed_engine] = template_idx;\n+\t\t\tnum_failed_engine++;\n+\t\t}\n+\t}\n+\n+\tint numQqsAcc = conf->q_ul_5g.num_qgroups;\n+\tint numQgs = conf->q_ul_5g.num_qgroups;\n+\tpayload = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tpayload |= (1 << qg_idx);\n+\t/* Force each engine which is in unspecified state */\n+\tfor (i = 0; i < num_failed_engine; i++) {\n+\t\tint failed_engine = engines_to_restart[i];\n+\t\tprintf(\"Force engine %d\\n\", failed_engine);\n+\t\tfor (template_idx = SIG_UL_5G; template_idx <= SIG_UL_5G_LAST;\n+\t\t\t\ttemplate_idx++) {\n+\t\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t\t+ BYTES_IN_WORD * template_idx;\n+\t\t\tif (template_idx == failed_engine)\n+\t\t\t\tacc100_reg_write(d, address, payload);\n+\t\t\telse\n+\t\t\t\tacc100_reg_write(d, address, 0);\n+\t\t}\n+\t\t/* Reset descriptor header */\n+\t\tdesc->req.word0 = ACC100_DMA_DESC_TYPE;\n+\t\tdesc->req.word1 = 0;\n+\t\tdesc->req.word2 = 0;\n+\t\tdesc->req.word3 = 0;\n+\t\tdesc->req.numCBs = 1;\n+\t\tdesc->req.m2dlen = 2;\n+\t\tdesc->req.d2mlen = 1;\n+\t\t/* Enqueue the code block for processing */\n+\t\tunion acc100_enqueue_reg_fmt enq_req;\n+\t\tenq_req.val = 0;\n+\t\tenq_req.addr_offset = ACC100_DESC_OFFSET;\n+\t\tenq_req.num_elem = 1;\n+\t\tenq_req.req_elem_addr = 0;\n+\t\trte_wmb();\n+\t\tacc100_reg_write(d, HWPfQmgrIngressAq + 0x100, enq_req.val);\n+\t\tusleep(LONG_WAIT * 100);\n+\t\tif (desc->req.word0 != 2)\n+\t\t\tprintf(\"DMA Response %#\"PRIx32\"\\n\", desc->req.word0);\n+\t}\n+\n+\t/* Reset LDPC Cores */\n+\tfor (i = 0; i < ACC100_ENGINES_MAX; i++)\n+\t\tacc100_reg_write(d, HWPfFecUl5gCntrlReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * i, ACC100_RESET_HI);\n+\tusleep(LONG_WAIT);\n+\tfor (i = 0; i < ACC100_ENGINES_MAX; i++)\n+\t\tacc100_reg_write(d, HWPfFecUl5gCntrlReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * i, ACC100_RESET_LO);\n+\tusleep(LONG_WAIT);\n+\tacc100_reg_write(d, HWPfHi5GHardResetReg, ACC100_RESET_HARD);\n+\tusleep(LONG_WAIT);\n+\tint numEngines = 0;\n+\t/* Check engine power-on status again */\n+\tfor (template_idx = SIG_UL_5G; template_idx <= SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HwPfFecUl5gIbDebugReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc100_reg_read(d, address) >> 4) & 0xF;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD * template_idx;\n+\t\tif (status == 1) {\n+\t\t\tacc100_reg_write(d, address, payload);\n+\t\t\tnumEngines++;\n+\t\t} else\n+\t\t\tacc100_reg_write(d, address, 0);\n+\t}\n+\tprintf(\"Number of 5GUL engines %d\\n\", numEngines);\n+\n+\tif (d->sw_rings_base != NULL)\n+\t\trte_free(d->sw_rings_base);\n+\tusleep(LONG_WAIT);\n+}\n+\n+/* Initial configuration of a ACC100 device prior to running configure() */\n+int\n+acc100_configure(const char *dev_name, struct acc100_conf *conf)\n+{\n+\trte_bbdev_log(INFO, \"acc100_configure\");\n+\tuint32_t payload, address, status;\n+\tint qg_idx, template_idx, vf_idx, acc, i;\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\n+\t/* Compile time checks */\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);\n+\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\tstruct acc100_device *d = bbdev->data->dev_private;\n+\n+\t/* Store configuration */\n+\trte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));\n+\n+\t/* PCIe Bridge configuration */\n+\tacc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);\n+\tfor (i = 1; i < 17; i++)\n+\t\tacc100_reg_write(d,\n+\t\t\t\tHwPfPcieGpexAxiAddrMappingWindowPexBaseHigh\n+\t\t\t\t+ i * 16, 0);\n+\n+\t/* PCIe Link Trainiing and Status State Machine */\n+\tacc100_reg_write(d, HwPfPcieGpexLtssmStateCntrl, 0xDFC00000);\n+\n+\t/* Prevent blocking AXI read on BRESP for AXI Write */\n+\taddress = HwPfPcieGpexAxiPioControl;\n+\tpayload = ACC100_CFG_PCI_AXI;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* 5GDL PLL phase shift */\n+\tacc100_reg_write(d, HWPfChaDl5gPllPhshft0, 0x1);\n+\n+\t/* Explicitly releasing AXI as this may be stopped after PF FLR/BME */\n+\taddress = HWPfDmaAxiControl;\n+\tpayload = 1;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* DDR Configuration */\n+\taddress = HWPfDdrBcTim6;\n+\tpayload = acc100_reg_read(d, address);\n+\tpayload &= 0xFFFFFFFB; /* Bit 2 */\n+#ifdef ACC100_DDR_ECC_ENABLE\n+\tpayload |= 0x4;\n+#endif\n+\tacc100_reg_write(d, address, payload);\n+\taddress = HWPfDdrPhyDqsCountNum;\n+#ifdef ACC100_DDR_ECC_ENABLE\n+\tpayload = 9;\n+#else\n+\tpayload = 8;\n+#endif\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Set default descriptor signature */\n+\taddress = HWPfDmaDescriptorSignatuture;\n+\tpayload = 0;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Enable the Error Detection in DMA */\n+\tpayload = ACC100_CFG_DMA_ERROR;\n+\taddress = HWPfDmaErrorDetectionEn;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* AXI Cache configuration */\n+\tpayload = ACC100_CFG_AXI_CACHE;\n+\taddress = HWPfDmaAxcacheReg;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Default DMA Configuration (Qmgr Enabled) */\n+\taddress = HWPfDmaConfig0Reg;\n+\tpayload = 0;\n+\tacc100_reg_write(d, address, payload);\n+\taddress = HWPfDmaQmanen;\n+\tpayload = 0;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Default RLIM/ALEN configuration */\n+\taddress = HWPfDmaConfig1Reg;\n+\tpayload = (1 << 31) + (23 << 8) + (1 << 6) + 7;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Configure DMA Qmanager addresses */\n+\taddress = HWPfDmaQmgrAddrReg;\n+\tpayload = HWPfQmgrEgressQueuesTemplate;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* ===== Qmgr Configuration ===== */\n+\t/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */\n+\tint totalQgs = conf->q_ul_4g.num_qgroups +\n+\t\t\tconf->q_ul_5g.num_qgroups +\n+\t\t\tconf->q_dl_4g.num_qgroups +\n+\t\t\tconf->q_dl_5g.num_qgroups;\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\taddress = HWPfQmgrDepthLog2Grp +\n+\t\tBYTES_IN_WORD * qg_idx;\n+\t\tpayload = aqDepth(qg_idx, conf);\n+\t\tacc100_reg_write(d, address, payload);\n+\t\taddress = HWPfQmgrTholdGrp +\n+\t\tBYTES_IN_WORD * qg_idx;\n+\t\tpayload = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\n+\t/* Template Priority in incremental order */\n+\tfor (template_idx = 0; template_idx < ACC100_NUM_TMPL;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg0Indx +\n+\t\tBYTES_IN_WORD * (template_idx % 8);\n+\t\tpayload = TMPL_PRI_0;\n+\t\tacc100_reg_write(d, address, payload);\n+\t\taddress = HWPfQmgrGrpTmplateReg1Indx +\n+\t\tBYTES_IN_WORD * (template_idx % 8);\n+\t\tpayload = TMPL_PRI_1;\n+\t\tacc100_reg_write(d, address, payload);\n+\t\taddress = HWPfQmgrGrpTmplateReg2indx +\n+\t\tBYTES_IN_WORD * (template_idx % 8);\n+\t\tpayload = TMPL_PRI_2;\n+\t\tacc100_reg_write(d, address, payload);\n+\t\taddress = HWPfQmgrGrpTmplateReg3Indx +\n+\t\tBYTES_IN_WORD * (template_idx % 8);\n+\t\tpayload = TMPL_PRI_3;\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\n+\taddress = HWPfQmgrGrpPriority;\n+\tpayload = ACC100_CFG_QMGR_HI_P;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Template Configuration */\n+\tfor (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {\n+\t\tpayload = 0;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD * template_idx;\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\t/* 4GUL */\n+\tint numQgs = conf->q_ul_4g.num_qgroups;\n+\tint numQqsAcc = 0;\n+\tpayload = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tpayload |= (1 << qg_idx);\n+\tfor (template_idx = SIG_UL_4G; template_idx <= SIG_UL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD*template_idx;\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\t/* 5GUL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_ul_5g.num_qgroups;\n+\tpayload = 0;\n+\tint numEngines = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tpayload |= (1 << qg_idx);\n+\tfor (template_idx = SIG_UL_5G; template_idx <= SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\t/* Check engine power-on status */\n+\t\taddress = HwPfFecUl5gIbDebugReg +\n+\t\t\t\tACC100_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc100_reg_read(d, address) >> 4) & 0xF;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD * template_idx;\n+\t\tif (status == 1) {\n+\t\t\tacc100_reg_write(d, address, payload);\n+\t\t\tnumEngines++;\n+\t\t} else\n+\t\t\tacc100_reg_write(d, address, 0);\n+\t\t#if RTE_ACC100_SINGLE_FEC == 1\n+\t\tpayload = 0;\n+\t\t#endif\n+\t}\n+\tprintf(\"Number of 5GUL engines %d\\n\", numEngines);\n+\t/* 4GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_4g.num_qgroups;\n+\tpayload = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tpayload |= (1 << qg_idx);\n+\tfor (template_idx = SIG_DL_4G; template_idx <= SIG_DL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD*template_idx;\n+\t\tacc100_reg_write(d, address, payload);\n+\t\t#if RTE_ACC100_SINGLE_FEC == 1\n+\t\t\tpayload = 0;\n+\t\t#endif\n+\t}\n+\t/* 5GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_5g.num_qgroups;\n+\tpayload = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tpayload |= (1 << qg_idx);\n+\tfor (template_idx = SIG_DL_5G; template_idx <= SIG_DL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ BYTES_IN_WORD*template_idx;\n+\t\tacc100_reg_write(d, address, payload);\n+\t\t#if RTE_ACC100_SINGLE_FEC == 1\n+\t\tpayload = 0;\n+\t\t#endif\n+\t}\n+\n+\t/* Queue Group Function mapping */\n+\tint qman_func_id[5] = {0, 2, 1, 3, 4};\n+\taddress = HWPfQmgrGrpFunction0;\n+\tpayload = 0;\n+\tfor (qg_idx = 0; qg_idx < 8; qg_idx++) {\n+\t\tacc = accFromQgid(qg_idx, conf);\n+\t\tpayload |= qman_func_id[acc]<<(qg_idx * 4);\n+\t}\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* Configuration of the Arbitration QGroup depth to 1 */\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\taddress = HWPfQmgrArbQDepthGrp +\n+\t\tBYTES_IN_WORD * qg_idx;\n+\t\tpayload = 0;\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\n+\t/* Enabling AQueues through the Queue hierarchy*/\n+\tfor (vf_idx = 0; vf_idx < ACC100_NUM_VFS; vf_idx++) {\n+\t\tfor (qg_idx = 0; qg_idx < ACC100_NUM_QGRPS; qg_idx++) {\n+\t\t\tpayload = 0;\n+\t\t\tif (vf_idx < conf->num_vf_bundles &&\n+\t\t\t\t\tqg_idx < totalQgs)\n+\t\t\t\tpayload = (1 << aqNum(qg_idx, conf)) - 1;\n+\t\t\taddress = HWPfQmgrAqEnableVf\n+\t\t\t\t\t+ vf_idx * BYTES_IN_WORD;\n+\t\t\tpayload += (qg_idx << 16);\n+\t\t\tacc100_reg_write(d, address, payload);\n+\t\t}\n+\t}\n+\n+\t/* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */\n+\tuint32_t aram_address = 0;\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\t\taddress = HWPfQmgrVfBaseAddr + vf_idx\n+\t\t\t\t\t* BYTES_IN_WORD + qg_idx\n+\t\t\t\t\t* BYTES_IN_WORD * 64;\n+\t\t\tpayload = aram_address;\n+\t\t\tacc100_reg_write(d, address, payload);\n+\t\t\t/* Offset ARAM Address for next memory bank\n+\t\t\t * - increment of 4B\n+\t\t\t */\n+\t\t\taram_address += aqNum(qg_idx, conf) *\n+\t\t\t\t\t(1 << aqDepth(qg_idx, conf));\n+\t\t}\n+\t}\n+\n+\tif (aram_address > WORDS_IN_ARAM_SIZE) {\n+\t\trte_bbdev_log(ERR, \"ARAM Configuration not fitting %d %d\\n\",\n+\t\t\t\taram_address, WORDS_IN_ARAM_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* ==== HI Configuration ==== */\n+\n+\t/* Prevent Block on Transmit Error */\n+\taddress = HWPfHiBlockTransmitOnErrorEn;\n+\tpayload = 0;\n+\tacc100_reg_write(d, address, payload);\n+\t/* Prevents to drop MSI */\n+\taddress = HWPfHiMsiDropEnableReg;\n+\tpayload = 0;\n+\tacc100_reg_write(d, address, payload);\n+\t/* Set the PF Mode register */\n+\taddress = HWPfHiPfMode;\n+\tpayload = (conf->pf_mode_en) ? 2 : 0;\n+\tacc100_reg_write(d, address, payload);\n+\t/* Enable Error Detection in HW */\n+\taddress = HWPfDmaErrorDetectionEn;\n+\tpayload = 0x3D7;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* QoS overflow init */\n+\tpayload = 1;\n+\taddress = HWPfQosmonAEvalOverflow0;\n+\tacc100_reg_write(d, address, payload);\n+\taddress = HWPfQosmonBEvalOverflow0;\n+\tacc100_reg_write(d, address, payload);\n+\n+\t/* HARQ DDR Configuration */\n+\tunsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */\n+\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\taddress = HWPfDmaVfDdrBaseRw + vf_idx\n+\t\t\t\t* 0x10;\n+\t\tpayload = ((vf_idx * (ddrSizeInMb / 64)) << 16) +\n+\t\t\t\t(ddrSizeInMb - 1);\n+\t\tacc100_reg_write(d, address, payload);\n+\t}\n+\tusleep(LONG_WAIT);\n+\n+\tif (numEngines < (SIG_UL_5G_LAST + 1))\n+\t\tpoweron_cleanup(bbdev, d, conf);\n+\n+\trte_bbdev_log_debug(\"PF Tip configuration complete for %s\", dev_name);\n+\treturn 0;\n+}\ndiff --git a/drivers/baseband/acc100/rte_pmd_bbdev_acc100_version.map b/drivers/baseband/acc100/rte_pmd_bbdev_acc100_version.map\nindex 4a76d1d..91c234d 100644\n--- a/drivers/baseband/acc100/rte_pmd_bbdev_acc100_version.map\n+++ b/drivers/baseband/acc100/rte_pmd_bbdev_acc100_version.map\n@@ -1,3 +1,10 @@\n DPDK_21 {\n \tlocal: *;\n };\n+\n+EXPERIMENTAL {\n+\tglobal:\n+\n+\tacc100_configure;\n+\n+};\n", "prefixes": [ "v2", "10/11" ] }