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GET /api/patches/75646/?format=api
{ "id": 75646, "url": "http://patches.dpdk.org/api/patches/75646/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1597791894-37041-4-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1597791894-37041-4-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1597791894-37041-4-git-send-email-nicolas.chautru@intel.com", "date": "2020-08-18T23:04:46", "name": "[v2,03/11] baseband/acc100: add info get function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f5d105da4a960a32830c7c8b84b28d742f291ef9", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1597791894-37041-4-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 11695, "url": "http://patches.dpdk.org/api/series/11695/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11695", "date": "2020-08-18T23:04:43", "name": "bbdev PMD ACC100", "version": 2, "mbox": "http://patches.dpdk.org/series/11695/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/75646/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/75646/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7F52EA04AF;\n\tWed, 19 Aug 2020 01:07:11 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6D3891C065;\n\tWed, 19 Aug 2020 01:06:50 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 48E52AAB7\n for <dev@dpdk.org>; Wed, 19 Aug 2020 01:06:46 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Aug 2020 16:06:44 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga004.jf.intel.com with ESMTP; 18 Aug 2020 16:06:43 -0700" ], "IronPort-SDR": [ "\n N95w75R/9YLqT6M+lV8HCka3yh/3KUmsSnHHQ7RsPGLEsPTgzjO2i/WPQNqUNWDsWQgSsQ6E64\n 2BBxc3YqLwxQ==", "\n miRpW+BMQxOUqWJ/XU8f3pGWaSxw+7RJqLtfokuwme1P5XeMpf4a5SKX3KOUH+LDMpy/na27Rx\n sWHj6jBtLHsA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9717\"; a=\"154281357\"", "E=Sophos;i=\"5.76,329,1592895600\"; d=\"scan'208\";a=\"154281357\"", "E=Sophos;i=\"5.76,329,1592895600\"; d=\"scan'208\";a=\"441400695\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Tue, 18 Aug 2020 16:04:46 -0700", "Message-Id": "<1597791894-37041-4-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1597791894-37041-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1597791894-37041-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 03/11] baseband/acc100: add info get function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add in the \"info_get\" function to the driver, to allow us to query the\ndevice.\nNo processing capability are available yet.\nLinking bbdev-test to support the PMD with null capability.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/Makefile | 3 +\n app/test-bbdev/meson.build | 3 +\n drivers/baseband/acc100/rte_acc100_cfg.h | 96 +++++++++++++\n drivers/baseband/acc100/rte_acc100_pmd.c | 225 +++++++++++++++++++++++++++++++\n drivers/baseband/acc100/rte_acc100_pmd.h | 3 +\n 5 files changed, 330 insertions(+)\n create mode 100644 drivers/baseband/acc100/rte_acc100_cfg.h", "diff": "diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile\nindex dc29557..dbc3437 100644\n--- a/app/test-bbdev/Makefile\n+++ b/app/test-bbdev/Makefile\n@@ -26,5 +26,8 @@ endif\n ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y)\n LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec\n endif\n+ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_ACC100),y)\n+LDLIBS += -lrte_pmd_bbdev_acc100\n+endif\n \n include $(RTE_SDK)/mk/rte.app.mk\ndiff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build\nindex 18ab6a8..fbd8ae3 100644\n--- a/app/test-bbdev/meson.build\n+++ b/app/test-bbdev/meson.build\n@@ -12,3 +12,6 @@ endif\n if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')\n \tdeps += ['pmd_bbdev_fpga_5gnr_fec']\n endif\n+if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_ACC100')\n+\tdeps += ['pmd_bbdev_acc100']\n+endif\n\\ No newline at end of file\ndiff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h\nnew file mode 100644\nindex 0000000..73bbe36\n--- /dev/null\n+++ b/drivers/baseband/acc100/rte_acc100_cfg.h\n@@ -0,0 +1,96 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_ACC100_CFG_H_\n+#define _RTE_ACC100_CFG_H_\n+\n+/**\n+ * @file rte_acc100_cfg.h\n+ *\n+ * Functions for configuring ACC100 HW, exposed directly to applications.\n+ * Configuration related to encoding/decoding is done through the\n+ * librte_bbdev library.\n+ *\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+/**< Number of Virtual Functions ACC100 supports */\n+#define RTE_ACC100_NUM_VFS 16\n+\n+/**\n+ * Definition of Queue Topology for ACC100 Configuration\n+ * Some level of details is abstracted out to expose a clean interface\n+ * given that comprehensive flexibility is not required\n+ */\n+struct rte_q_topology_t {\n+\t/** Number of QGroups in incremental order of priority */\n+\tuint16_t num_qgroups;\n+\t/**\n+\t * All QGroups have the same number of AQs here.\n+\t * Note : Could be made a 16-array if more flexibility is really\n+\t * required\n+\t */\n+\tuint16_t num_aqs_per_groups;\n+\t/**\n+\t * Depth of the AQs is the same of all QGroups here. Log2 Enum : 2^N\n+\t * Note : Could be made a 16-array if more flexibility is really\n+\t * required\n+\t */\n+\tuint16_t aq_depth_log2;\n+\t/**\n+\t * Index of the first Queue Group Index - assuming contiguity\n+\t * Initialized as -1\n+\t */\n+\tint8_t first_qgroup_index;\n+};\n+\n+/**\n+ * Definition of Arbitration related parameters for ACC100 Configuration\n+ */\n+struct rte_arbitration_t {\n+\t/** Default Weight for VF Fairness Arbitration */\n+\tuint16_t round_robin_weight;\n+\tuint32_t gbr_threshold1; /**< Guaranteed Bitrate Threshold 1 */\n+\tuint32_t gbr_threshold2; /**< Guaranteed Bitrate Threshold 2 */\n+};\n+\n+/**\n+ * Structure to pass ACC100 configuration.\n+ * Note: all VF Bundles will have the same configuration.\n+ */\n+struct acc100_conf {\n+\tbool pf_mode_en; /**< 1 if PF is used for dataplane, 0 for VFs */\n+\t/** 1 if input '1' bit is represented by a positive LLR value, 0 if '1'\n+\t * bit is represented by a negative value.\n+\t */\n+\tbool input_pos_llr_1_bit;\n+\t/** 1 if output '1' bit is represented by a positive value, 0 if '1'\n+\t * bit is represented by a negative value.\n+\t */\n+\tbool output_pos_llr_1_bit;\n+\tuint16_t num_vf_bundles; /**< Number of VF bundles to setup */\n+\t/** Queue topology for each operation type */\n+\tstruct rte_q_topology_t q_ul_4g;\n+\tstruct rte_q_topology_t q_dl_4g;\n+\tstruct rte_q_topology_t q_ul_5g;\n+\tstruct rte_q_topology_t q_dl_5g;\n+\t/** Arbitration configuration for each operation type */\n+\tstruct rte_arbitration_t arb_ul_4g[RTE_ACC100_NUM_VFS];\n+\tstruct rte_arbitration_t arb_dl_4g[RTE_ACC100_NUM_VFS];\n+\tstruct rte_arbitration_t arb_ul_5g[RTE_ACC100_NUM_VFS];\n+\tstruct rte_arbitration_t arb_dl_5g[RTE_ACC100_NUM_VFS];\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ACC100_CFG_H_ */\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c\nindex 1b4cd13..7807a30 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.c\n@@ -26,6 +26,184 @@\n RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, NOTICE);\n #endif\n \n+/* Read a register of a ACC100 device */\n+static inline uint32_t\n+acc100_reg_read(struct acc100_device *d, uint32_t offset)\n+{\n+\n+\tvoid *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);\n+\tuint32_t ret = *((volatile uint32_t *)(reg_addr));\n+\treturn rte_le_to_cpu_32(ret);\n+}\n+\n+/* Calculate the offset of the enqueue register */\n+static inline uint32_t\n+queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)\n+{\n+\tif (pf_device)\n+\t\treturn ((vf_id << 12) + (qgrp_id << 7) + (aq_id << 3) +\n+\t\t\t\tHWPfQmgrIngressAq);\n+\telse\n+\t\treturn ((qgrp_id << 7) + (aq_id << 3) +\n+\t\t\t\tHWVfQmgrIngressAq);\n+}\n+\n+enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, NUM_ACC};\n+\n+/* Return the queue topology for a Queue Group Index */\n+static inline void\n+qtopFromAcc(struct rte_q_topology_t **qtop, int acc_enum,\n+\t\tstruct acc100_conf *acc100_conf)\n+{\n+\tstruct rte_q_topology_t *p_qtop;\n+\tp_qtop = NULL;\n+\tswitch (acc_enum) {\n+\tcase UL_4G:\n+\t\tp_qtop = &(acc100_conf->q_ul_4g);\n+\t\tbreak;\n+\tcase UL_5G:\n+\t\tp_qtop = &(acc100_conf->q_ul_5g);\n+\t\tbreak;\n+\tcase DL_4G:\n+\t\tp_qtop = &(acc100_conf->q_dl_4g);\n+\t\tbreak;\n+\tcase DL_5G:\n+\t\tp_qtop = &(acc100_conf->q_dl_5g);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* NOTREACHED */\n+\t\trte_bbdev_log(ERR, \"Unexpected error evaluating qtopFromAcc\");\n+\t\tbreak;\n+\t}\n+\t*qtop = p_qtop;\n+}\n+\n+static void\n+initQTop(struct acc100_conf *acc100_conf)\n+{\n+\tacc100_conf->q_ul_4g.num_aqs_per_groups = 0;\n+\tacc100_conf->q_ul_4g.num_qgroups = 0;\n+\tacc100_conf->q_ul_4g.first_qgroup_index = -1;\n+\tacc100_conf->q_ul_5g.num_aqs_per_groups = 0;\n+\tacc100_conf->q_ul_5g.num_qgroups = 0;\n+\tacc100_conf->q_ul_5g.first_qgroup_index = -1;\n+\tacc100_conf->q_dl_4g.num_aqs_per_groups = 0;\n+\tacc100_conf->q_dl_4g.num_qgroups = 0;\n+\tacc100_conf->q_dl_4g.first_qgroup_index = -1;\n+\tacc100_conf->q_dl_5g.num_aqs_per_groups = 0;\n+\tacc100_conf->q_dl_5g.num_qgroups = 0;\n+\tacc100_conf->q_dl_5g.first_qgroup_index = -1;\n+}\n+\n+static inline void\n+updateQtop(uint8_t acc, uint8_t qg, struct acc100_conf *acc100_conf,\n+\t\tstruct acc100_device *d) {\n+\tuint32_t reg;\n+\tstruct rte_q_topology_t *q_top = NULL;\n+\tqtopFromAcc(&q_top, acc, acc100_conf);\n+\tif (unlikely(q_top == NULL))\n+\t\treturn;\n+\tuint16_t aq;\n+\tq_top->num_qgroups++;\n+\tif (q_top->first_qgroup_index == -1) {\n+\t\tq_top->first_qgroup_index = qg;\n+\t\t/* Can be optimized to assume all are enabled by default */\n+\t\treg = acc100_reg_read(d, queue_offset(d->pf_device,\n+\t\t\t\t0, qg, ACC100_NUM_AQS - 1));\n+\t\tif (reg & QUEUE_ENABLE) {\n+\t\t\tq_top->num_aqs_per_groups = ACC100_NUM_AQS;\n+\t\t\treturn;\n+\t\t}\n+\t\tq_top->num_aqs_per_groups = 0;\n+\t\tfor (aq = 0; aq < ACC100_NUM_AQS; aq++) {\n+\t\t\treg = acc100_reg_read(d, queue_offset(d->pf_device,\n+\t\t\t\t\t0, qg, aq));\n+\t\t\tif (reg & QUEUE_ENABLE)\n+\t\t\t\tq_top->num_aqs_per_groups++;\n+\t\t}\n+\t}\n+}\n+\n+/* Fetch configuration enabled for the PF/VF using MMIO Read (slow) */\n+static inline void\n+fetch_acc100_config(struct rte_bbdev *dev)\n+{\n+\tstruct acc100_device *d = dev->data->dev_private;\n+\tstruct acc100_conf *acc100_conf = &d->acc100_conf;\n+\tconst struct acc100_registry_addr *reg_addr;\n+\tuint8_t acc, qg;\n+\tuint32_t reg, reg_aq, reg_len0, reg_len1;\n+\tuint32_t reg_mode;\n+\n+\t/* No need to retrieve the configuration is already done */\n+\tif (d->configured)\n+\t\treturn;\n+\n+\t/* Choose correct registry addresses for the device type */\n+\tif (d->pf_device)\n+\t\treg_addr = &pf_reg_addr;\n+\telse\n+\t\treg_addr = &vf_reg_addr;\n+\n+\td->ddr_size = (1 + acc100_reg_read(d, reg_addr->ddr_range)) << 10;\n+\n+\t/* Single VF Bundle by VF */\n+\tacc100_conf->num_vf_bundles = 1;\n+\tinitQTop(acc100_conf);\n+\n+\tstruct rte_q_topology_t *q_top = NULL;\n+\tint qman_func_id[5] = {0, 2, 1, 3, 4};\n+\treg = acc100_reg_read(d, reg_addr->qman_group_func);\n+\tfor (qg = 0; qg < ACC100_NUM_QGRPS_PER_WORD; qg++) {\n+\t\treg_aq = acc100_reg_read(d,\n+\t\t\t\tqueue_offset(d->pf_device, 0, qg, 0));\n+\t\tif (reg_aq & QUEUE_ENABLE) {\n+\t\t\tacc = qman_func_id[(reg >> (qg * 4)) & 0x7];\n+\t\t\tupdateQtop(acc, qg, acc100_conf, d);\n+\t\t}\n+\t}\n+\n+\t/* Check the depth of the AQs*/\n+\treg_len0 = acc100_reg_read(d, reg_addr->depth_log0_offset);\n+\treg_len1 = acc100_reg_read(d, reg_addr->depth_log1_offset);\n+\tfor (acc = 0; acc < NUM_ACC; acc++) {\n+\t\tqtopFromAcc(&q_top, acc, acc100_conf);\n+\t\tif (q_top->first_qgroup_index < ACC100_NUM_QGRPS_PER_WORD)\n+\t\t\tq_top->aq_depth_log2 = (reg_len0 >>\n+\t\t\t\t\t(q_top->first_qgroup_index * 4))\n+\t\t\t\t\t& 0xF;\n+\t\telse\n+\t\t\tq_top->aq_depth_log2 = (reg_len1 >>\n+\t\t\t\t\t((q_top->first_qgroup_index -\n+\t\t\t\t\tACC100_NUM_QGRPS_PER_WORD) * 4))\n+\t\t\t\t\t& 0xF;\n+\t}\n+\n+\t/* Read PF mode */\n+\tif (d->pf_device) {\n+\t\treg_mode = acc100_reg_read(d, HWPfHiPfMode);\n+\t\tacc100_conf->pf_mode_en = (reg_mode == 2) ? 1 : 0;\n+\t}\n+\n+\trte_bbdev_log_debug(\n+\t\t\t\"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u AQ %u %u %u %u Len %u %u %u %u\\n\",\n+\t\t\t(d->pf_device) ? \"PF\" : \"VF\",\n+\t\t\t(acc100_conf->input_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n+\t\t\t(acc100_conf->output_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n+\t\t\tacc100_conf->q_ul_4g.num_qgroups,\n+\t\t\tacc100_conf->q_dl_4g.num_qgroups,\n+\t\t\tacc100_conf->q_ul_5g.num_qgroups,\n+\t\t\tacc100_conf->q_dl_5g.num_qgroups,\n+\t\t\tacc100_conf->q_ul_4g.num_aqs_per_groups,\n+\t\t\tacc100_conf->q_dl_4g.num_aqs_per_groups,\n+\t\t\tacc100_conf->q_ul_5g.num_aqs_per_groups,\n+\t\t\tacc100_conf->q_dl_5g.num_aqs_per_groups,\n+\t\t\tacc100_conf->q_ul_4g.aq_depth_log2,\n+\t\t\tacc100_conf->q_dl_4g.aq_depth_log2,\n+\t\t\tacc100_conf->q_ul_5g.aq_depth_log2,\n+\t\t\tacc100_conf->q_dl_5g.aq_depth_log2);\n+}\n+\n /* Free 64MB memory used for software rings */\n static int\n acc100_dev_close(struct rte_bbdev *dev __rte_unused)\n@@ -33,8 +211,55 @@\n \treturn 0;\n }\n \n+/* Get ACC100 device info */\n+static void\n+acc100_dev_info_get(struct rte_bbdev *dev,\n+\t\tstruct rte_bbdev_driver_info *dev_info)\n+{\n+\tstruct acc100_device *d = dev->data->dev_private;\n+\n+\tstatic const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n+\t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n+\t};\n+\n+\tstatic struct rte_bbdev_queue_conf default_queue_conf;\n+\tdefault_queue_conf.socket = dev->data->socket_id;\n+\tdefault_queue_conf.queue_size = MAX_QUEUE_DEPTH;\n+\n+\tdev_info->driver_name = dev->device->driver->name;\n+\n+\t/* Read and save the populated config from ACC100 registers */\n+\tfetch_acc100_config(dev);\n+\n+\t/* This isn't ideal because it reports the maximum number of queues but\n+\t * does not provide info on how many can be uplink/downlink or different\n+\t * priorities\n+\t */\n+\tdev_info->max_num_queues =\n+\t\t\td->acc100_conf.q_dl_5g.num_aqs_per_groups *\n+\t\t\td->acc100_conf.q_dl_5g.num_qgroups +\n+\t\t\td->acc100_conf.q_ul_5g.num_aqs_per_groups *\n+\t\t\td->acc100_conf.q_ul_5g.num_qgroups +\n+\t\t\td->acc100_conf.q_dl_4g.num_aqs_per_groups *\n+\t\t\td->acc100_conf.q_dl_4g.num_qgroups +\n+\t\t\td->acc100_conf.q_ul_4g.num_aqs_per_groups *\n+\t\t\td->acc100_conf.q_ul_4g.num_qgroups;\n+\tdev_info->queue_size_lim = MAX_QUEUE_DEPTH;\n+\tdev_info->hardware_accelerated = true;\n+\tdev_info->max_dl_queue_priority =\n+\t\t\td->acc100_conf.q_dl_4g.num_qgroups - 1;\n+\tdev_info->max_ul_queue_priority =\n+\t\t\td->acc100_conf.q_ul_4g.num_qgroups - 1;\n+\tdev_info->default_queue_conf = default_queue_conf;\n+\tdev_info->cpu_flag_reqs = NULL;\n+\tdev_info->min_alignment = 64;\n+\tdev_info->capabilities = bbdev_capabilities;\n+\tdev_info->harq_buffer_size = d->ddr_size;\n+}\n+\n static const struct rte_bbdev_ops acc100_bbdev_ops = {\n \t.close = acc100_dev_close,\n+\t.info_get = acc100_dev_info_get,\n };\n \n /* ACC100 PCI PF address map */\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h\nindex 139d3ee..3e2397c 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.h\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.h\n@@ -7,6 +7,7 @@\n \n #include \"acc100_pf_enum.h\"\n #include \"acc100_vf_enum.h\"\n+#include \"rte_acc100_cfg.h\"\n \n /* Helper macro for logging */\n #define rte_bbdev_log(level, fmt, ...) \\\n@@ -520,6 +521,8 @@ struct acc100_registry_addr {\n /* Private data structure for each ACC100 device */\n struct acc100_device {\n \tvoid *mmio_base; /**< Base address of MMIO registers (BAR0) */\n+\tuint32_t ddr_size; /* Size in kB */\n+\tstruct acc100_conf acc100_conf; /* ACC100 Initial configuration */\n \tbool pf_device; /**< True if this is a PF ACC100 device */\n \tbool configured; /**< True if this ACC100 device is configured */\n };\n", "prefixes": [ "v2", "03/11" ] }