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GET /api/patches/75059/?format=api
{ "id": 75059, "url": "http://patches.dpdk.org/api/patches/75059/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1596138614-17409-9-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1596138614-17409-9-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1596138614-17409-9-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-07-30T19:49:55", "name": "[08/27] event/dlb: add definitions shared with LKM or shared code", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3956f411ab2fb40b79ec6bc7ffbe991c8fc856c3", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1596138614-17409-9-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 11425, "url": "http://patches.dpdk.org/api/series/11425/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11425", "date": "2020-07-30T19:49:47", "name": "Add Intel DLM PMD to 20.11", "version": 1, "mbox": "http://patches.dpdk.org/series/11425/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/75059/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/75059/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 49C27A052B;\n\tThu, 30 Jul 2020 21:54:30 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A5BF41C0CA;\n\tThu, 30 Jul 2020 21:53:22 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id DB8C11C00D\n for <dev@dpdk.org>; Thu, 30 Jul 2020 21:53:10 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Jul 2020 12:53:10 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga005.jf.intel.com with ESMTP; 30 Jul 2020 12:53:09 -0700" ], "IronPort-SDR": [ "\n NqMRFCvk9RJWoRVY4wIePvcHAhAjIG5LT73RlL8J/M3sYwqZon7n3s6d0EDbW2zJlUKThzF8/E\n Jgv7RVDu9RKA==", "\n yoGBiMFSz7MK5/Ih4pQoEWyh2TAahiciTccjpuG5Ep/JBB7GSbz4fEpwW+5iheHlHzi1D2vkWH\n tBtCfv0LfqHQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9698\"; a=\"139672300\"", "E=Sophos;i=\"5.75,415,1589266800\"; d=\"scan'208\";a=\"139672300\"", "E=Sophos;i=\"5.75,415,1589266800\"; d=\"scan'208\";a=\"465378095\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "\"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "To": "jerinj@marvell.com", "Cc": "mattias.ronnblom@ericsson.com, dev@dpdk.org, gage.eads@intel.com,\n harry.van.haaren@intel.com,\n \"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "Date": "Thu, 30 Jul 2020 14:49:55 -0500", "Message-Id": "<1596138614-17409-9-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1596138614-17409-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<1593232671-5690-0-git-send-email-timothy.mcdaniel@intel.com>\n <1596138614-17409-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH 08/27] event/dlb: add definitions shared with LKM\n\tor shared code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>\n\nSigned-off-by: McDaniel, Timothy <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb/dlb_user.h | 1083 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 1083 insertions(+)\n create mode 100644 drivers/event/dlb/dlb_user.h", "diff": "diff --git a/drivers/event/dlb/dlb_user.h b/drivers/event/dlb/dlb_user.h\nnew file mode 100644\nindex 0000000..73b601b\n--- /dev/null\n+++ b/drivers/event/dlb/dlb_user.h\n@@ -0,0 +1,1083 @@\n+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB_USER_H\n+#define __DLB_USER_H\n+\n+#define DLB_MAX_NAME_LEN 64\n+\n+#include <linux/types.h>\n+\n+enum dlb_error {\n+\tDLB_ST_SUCCESS = 0,\n+\tDLB_ST_NAME_EXISTS,\n+\tDLB_ST_DOMAIN_UNAVAILABLE,\n+\tDLB_ST_LDB_PORTS_UNAVAILABLE,\n+\tDLB_ST_DIR_PORTS_UNAVAILABLE,\n+\tDLB_ST_LDB_QUEUES_UNAVAILABLE,\n+\tDLB_ST_LDB_CREDITS_UNAVAILABLE,\n+\tDLB_ST_DIR_CREDITS_UNAVAILABLE,\n+\tDLB_ST_LDB_CREDIT_POOLS_UNAVAILABLE,\n+\tDLB_ST_DIR_CREDIT_POOLS_UNAVAILABLE,\n+\tDLB_ST_SEQUENCE_NUMBERS_UNAVAILABLE,\n+\tDLB_ST_INVALID_DOMAIN_ID,\n+\tDLB_ST_INVALID_QID_INFLIGHT_ALLOCATION,\n+\tDLB_ST_ATOMIC_INFLIGHTS_UNAVAILABLE,\n+\tDLB_ST_HIST_LIST_ENTRIES_UNAVAILABLE,\n+\tDLB_ST_INVALID_LDB_CREDIT_POOL_ID,\n+\tDLB_ST_INVALID_DIR_CREDIT_POOL_ID,\n+\tDLB_ST_INVALID_POP_COUNT_VIRT_ADDR,\n+\tDLB_ST_INVALID_LDB_QUEUE_ID,\n+\tDLB_ST_INVALID_CQ_DEPTH,\n+\tDLB_ST_INVALID_CQ_VIRT_ADDR,\n+\tDLB_ST_INVALID_PORT_ID,\n+\tDLB_ST_INVALID_QID,\n+\tDLB_ST_INVALID_PRIORITY,\n+\tDLB_ST_NO_QID_SLOTS_AVAILABLE,\n+\tDLB_ST_QED_FREELIST_ENTRIES_UNAVAILABLE,\n+\tDLB_ST_DQED_FREELIST_ENTRIES_UNAVAILABLE,\n+\tDLB_ST_INVALID_DIR_QUEUE_ID,\n+\tDLB_ST_DIR_QUEUES_UNAVAILABLE,\n+\tDLB_ST_INVALID_LDB_CREDIT_LOW_WATERMARK,\n+\tDLB_ST_INVALID_LDB_CREDIT_QUANTUM,\n+\tDLB_ST_INVALID_DIR_CREDIT_LOW_WATERMARK,\n+\tDLB_ST_INVALID_DIR_CREDIT_QUANTUM,\n+\tDLB_ST_DOMAIN_NOT_CONFIGURED,\n+\tDLB_ST_PID_ALREADY_ATTACHED,\n+\tDLB_ST_PID_NOT_ATTACHED,\n+\tDLB_ST_INTERNAL_ERROR,\n+\tDLB_ST_DOMAIN_IN_USE,\n+\tDLB_ST_IOMMU_MAPPING_ERROR,\n+\tDLB_ST_FAIL_TO_PIN_MEMORY_PAGE,\n+\tDLB_ST_UNABLE_TO_PIN_POPCOUNT_PAGES,\n+\tDLB_ST_UNABLE_TO_PIN_CQ_PAGES,\n+\tDLB_ST_DISCONTIGUOUS_CQ_MEMORY,\n+\tDLB_ST_DISCONTIGUOUS_POP_COUNT_MEMORY,\n+\tDLB_ST_DOMAIN_STARTED,\n+\tDLB_ST_LARGE_POOL_NOT_SPECIFIED,\n+\tDLB_ST_SMALL_POOL_NOT_SPECIFIED,\n+\tDLB_ST_NEITHER_POOL_SPECIFIED,\n+\tDLB_ST_DOMAIN_NOT_STARTED,\n+\tDLB_ST_INVALID_MEASUREMENT_DURATION,\n+\tDLB_ST_INVALID_PERF_METRIC_GROUP_ID,\n+\tDLB_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES,\n+\tDLB_ST_DOMAIN_RESET_FAILED,\n+\tDLB_ST_MBOX_ERROR,\n+\tDLB_ST_INVALID_HIST_LIST_DEPTH,\n+\tDLB_ST_NO_MEMORY,\n+};\n+\n+static const char dlb_error_strings[][128] = {\n+\t\"DLB_ST_SUCCESS\",\n+\t\"DLB_ST_NAME_EXISTS\",\n+\t\"DLB_ST_DOMAIN_UNAVAILABLE\",\n+\t\"DLB_ST_LDB_PORTS_UNAVAILABLE\",\n+\t\"DLB_ST_DIR_PORTS_UNAVAILABLE\",\n+\t\"DLB_ST_LDB_QUEUES_UNAVAILABLE\",\n+\t\"DLB_ST_LDB_CREDITS_UNAVAILABLE\",\n+\t\"DLB_ST_DIR_CREDITS_UNAVAILABLE\",\n+\t\"DLB_ST_LDB_CREDIT_POOLS_UNAVAILABLE\",\n+\t\"DLB_ST_DIR_CREDIT_POOLS_UNAVAILABLE\",\n+\t\"DLB_ST_SEQUENCE_NUMBERS_UNAVAILABLE\",\n+\t\"DLB_ST_INVALID_DOMAIN_ID\",\n+\t\"DLB_ST_INVALID_QID_INFLIGHT_ALLOCATION\",\n+\t\"DLB_ST_ATOMIC_INFLIGHTS_UNAVAILABLE\",\n+\t\"DLB_ST_HIST_LIST_ENTRIES_UNAVAILABLE\",\n+\t\"DLB_ST_INVALID_LDB_CREDIT_POOL_ID\",\n+\t\"DLB_ST_INVALID_DIR_CREDIT_POOL_ID\",\n+\t\"DLB_ST_INVALID_POP_COUNT_VIRT_ADDR\",\n+\t\"DLB_ST_INVALID_LDB_QUEUE_ID\",\n+\t\"DLB_ST_INVALID_CQ_DEPTH\",\n+\t\"DLB_ST_INVALID_CQ_VIRT_ADDR\",\n+\t\"DLB_ST_INVALID_PORT_ID\",\n+\t\"DLB_ST_INVALID_QID\",\n+\t\"DLB_ST_INVALID_PRIORITY\",\n+\t\"DLB_ST_NO_QID_SLOTS_AVAILABLE\",\n+\t\"DLB_ST_QED_FREELIST_ENTRIES_UNAVAILABLE\",\n+\t\"DLB_ST_DQED_FREELIST_ENTRIES_UNAVAILABLE\",\n+\t\"DLB_ST_INVALID_DIR_QUEUE_ID\",\n+\t\"DLB_ST_DIR_QUEUES_UNAVAILABLE\",\n+\t\"DLB_ST_INVALID_LDB_CREDIT_LOW_WATERMARK\",\n+\t\"DLB_ST_INVALID_LDB_CREDIT_QUANTUM\",\n+\t\"DLB_ST_INVALID_DIR_CREDIT_LOW_WATERMARK\",\n+\t\"DLB_ST_INVALID_DIR_CREDIT_QUANTUM\",\n+\t\"DLB_ST_DOMAIN_NOT_CONFIGURED\",\n+\t\"DLB_ST_PID_ALREADY_ATTACHED\",\n+\t\"DLB_ST_PID_NOT_ATTACHED\",\n+\t\"DLB_ST_INTERNAL_ERROR\",\n+\t\"DLB_ST_DOMAIN_IN_USE\",\n+\t\"DLB_ST_IOMMU_MAPPING_ERROR\",\n+\t\"DLB_ST_FAIL_TO_PIN_MEMORY_PAGE\",\n+\t\"DLB_ST_UNABLE_TO_PIN_POPCOUNT_PAGES\",\n+\t\"DLB_ST_UNABLE_TO_PIN_CQ_PAGES\",\n+\t\"DLB_ST_DISCONTIGUOUS_CQ_MEMORY\",\n+\t\"DLB_ST_DISCONTIGUOUS_POP_COUNT_MEMORY\",\n+\t\"DLB_ST_DOMAIN_STARTED\",\n+\t\"DLB_ST_LARGE_POOL_NOT_SPECIFIED\",\n+\t\"DLB_ST_SMALL_POOL_NOT_SPECIFIED\",\n+\t\"DLB_ST_NEITHER_POOL_SPECIFIED\",\n+\t\"DLB_ST_DOMAIN_NOT_STARTED\",\n+\t\"DLB_ST_INVALID_MEASUREMENT_DURATION\",\n+\t\"DLB_ST_INVALID_PERF_METRIC_GROUP_ID\",\n+\t\"DLB_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES\",\n+\t\"DLB_ST_DOMAIN_RESET_FAILED\",\n+\t\"DLB_ST_MBOX_ERROR\",\n+\t\"DLB_ST_INVALID_HIST_LIST_DEPTH\",\n+\t\"DLB_ST_NO_MEMORY\",\n+};\n+\n+struct dlb_cmd_response {\n+\t__u32 status; /* Interpret using enum dlb_error */\n+\t__u32 id;\n+};\n+\n+/******************************/\n+/* 'dlb' device file commands */\n+/******************************/\n+\n+#define DLB_DEVICE_VERSION(x) (((x) >> 8) & 0xFF)\n+#define DLB_DEVICE_REVISION(x) ((x) & 0xFF)\n+\n+enum dlb_revisions {\n+\tDLB_REV_A0 = 0,\n+\tDLB_REV_A1 = 1,\n+\tDLB_REV_A2 = 2,\n+\tDLB_REV_A3 = 3,\n+\tDLB_REV_B0 = 4,\n+};\n+\n+/*\n+ * DLB_CMD_GET_DEVICE_VERSION: Query the DLB device version.\n+ *\n+ *\tThis ioctl interface is the same in all driver versions and is always\n+ *\tthe first ioctl.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id[7:0]: Device revision.\n+ *\tresponse.id[15:8]: Device version.\n+ */\n+\n+struct dlb_get_device_version_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+};\n+\n+#define DLB_VERSION_MAJOR_NUMBER 10\n+#define DLB_VERSION_MINOR_NUMBER 7\n+#define DLB_VERSION_REVISION_NUMBER 9\n+#define DLB_VERSION (DLB_VERSION_MAJOR_NUMBER << 24 | \\\n+\t\t DLB_VERSION_MINOR_NUMBER << 16 | \\\n+\t\t DLB_VERSION_REVISION_NUMBER)\n+\n+#define DLB_VERSION_GET_MAJOR_NUMBER(x) (((x) >> 24) & 0xFF)\n+#define DLB_VERSION_GET_MINOR_NUMBER(x) (((x) >> 16) & 0xFF)\n+#define DLB_VERSION_GET_REVISION_NUMBER(x) ((x) & 0xFFFF)\n+\n+static inline __u8 dlb_version_incompatible(__u32 version)\n+{\n+\t__u8 inc;\n+\n+\tinc = DLB_VERSION_GET_MAJOR_NUMBER(version) != DLB_VERSION_MAJOR_NUMBER;\n+\tinc |= (int)DLB_VERSION_GET_MINOR_NUMBER(version) <\n+\t\tDLB_VERSION_MINOR_NUMBER;\n+\n+\treturn inc;\n+}\n+\n+/*\n+ * DLB_CMD_GET_DRIVER_VERSION: Query the DLB driver version. The major number\n+ *\tis changed when there is an ABI-breaking change, the minor number is\n+ *\tchanged if the API is changed in a backwards-compatible way, and the\n+ *\trevision number is changed for fixes that don't affect the API.\n+ *\n+ *\tIf the kernel driver's API version major number and the header's\n+ *\tDLB_VERSION_MAJOR_NUMBER differ, the two are incompatible, or if the\n+ *\tmajor numbers match but the kernel driver's minor number is less than\n+ *\tthe header file's, they are incompatible. The DLB_VERSION_INCOMPATIBLE\n+ *\tmacro should be used to check for compatibility.\n+ *\n+ *\tThis ioctl interface is the same in all driver versions. Applications\n+ *\tshould check the driver version before performing any other ioctl\n+ *\toperations.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Driver API version. Use the DLB_VERSION_GET_MAJOR_NUMBER,\n+ *\t\tDLB_VERSION_GET_MINOR_NUMBER, and\n+ *\t\tDLB_VERSION_GET_REVISION_NUMBER macros to interpret the field.\n+ */\n+\n+struct dlb_get_driver_version_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+};\n+\n+/*\n+ * DLB_CMD_CREATE_SCHED_DOMAIN: Create a DLB scheduling domain and reserve the\n+ *\tresources (queues, ports, etc.) that it contains.\n+ *\n+ * Input parameters:\n+ * - num_ldb_queues: Number of load-balanced queues.\n+ * - num_ldb_ports: Number of load-balanced ports.\n+ * - num_dir_ports: Number of directed ports. A directed port has one directed\n+ *\tqueue, so no num_dir_queues argument is necessary.\n+ * - num_atomic_inflights: This specifies the amount of temporary atomic QE\n+ *\tstorage for the domain. This storage is divided among the domain's\n+ *\tload-balanced queues that are configured for atomic scheduling.\n+ * - num_hist_list_entries: Amount of history list storage. This is divided\n+ *\tamong the domain's CQs.\n+ * - num_ldb_credits: Amount of load-balanced QE storage (QED). QEs occupy this\n+ *\tspace until they are scheduled to a load-balanced CQ. One credit\n+ *\trepresents the storage for one QE.\n+ * - num_dir_credits: Amount of directed QE storage (DQED). QEs occupy this\n+ *\tspace until they are scheduled to a directed CQ. One credit represents\n+ *\tthe storage for one QE.\n+ * - num_ldb_credit_pools: Number of pools into which the load-balanced credits\n+ *\tare placed.\n+ * - num_dir_credit_pools: Number of pools into which the directed credits are\n+ *\tplaced.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: domain ID.\n+ */\n+struct dlb_create_sched_domain_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 num_ldb_queues;\n+\t__u32 num_ldb_ports;\n+\t__u32 num_dir_ports;\n+\t__u32 num_atomic_inflights;\n+\t__u32 num_hist_list_entries;\n+\t__u32 num_ldb_credits;\n+\t__u32 num_dir_credits;\n+\t__u32 num_ldb_credit_pools;\n+\t__u32 num_dir_credit_pools;\n+};\n+\n+/*\n+ * DLB_CMD_GET_NUM_RESOURCES: Return the number of available resources\n+ *\t(queues, ports, etc.) that this device owns.\n+ *\n+ * Output parameters:\n+ * - num_domains: Number of available scheduling domains.\n+ * - num_ldb_queues: Number of available load-balanced queues.\n+ * - num_ldb_ports: Number of available load-balanced ports.\n+ * - num_dir_ports: Number of available directed ports. There is one directed\n+ *\tqueue for every directed port.\n+ * - num_atomic_inflights: Amount of available temporary atomic QE storage.\n+ * - max_contiguous_atomic_inflights: When a domain is created, the temporary\n+ *\tatomic QE storage is allocated in a contiguous chunk. This return value\n+ *\tis the longest available contiguous range of atomic QE storage.\n+ * - num_hist_list_entries: Amount of history list storage.\n+ * - max_contiguous_hist_list_entries: History list storage is allocated in\n+ *\ta contiguous chunk, and this return value is the longest available\n+ *\tcontiguous range of history list entries.\n+ * - num_ldb_credits: Amount of available load-balanced QE storage.\n+ * - max_contiguous_ldb_credits: QED storage is allocated in a contiguous\n+ *\tchunk, and this return value is the longest available contiguous range\n+ *\tof load-balanced credit storage.\n+ * - num_dir_credits: Amount of available directed QE storage.\n+ * - max_contiguous_dir_credits: DQED storage is allocated in a contiguous\n+ *\tchunk, and this return value is the longest available contiguous range\n+ *\tof directed credit storage.\n+ * - num_ldb_credit_pools: Number of available load-balanced credit pools.\n+ * - num_dir_credit_pools: Number of available directed credit pools.\n+ * - padding0: Reserved for future use.\n+ */\n+struct dlb_get_num_resources_args {\n+\t/* Output parameters */\n+\t__u32 num_sched_domains;\n+\t__u32 num_ldb_queues;\n+\t__u32 num_ldb_ports;\n+\t__u32 num_dir_ports;\n+\t__u32 num_atomic_inflights;\n+\t__u32 max_contiguous_atomic_inflights;\n+\t__u32 num_hist_list_entries;\n+\t__u32 max_contiguous_hist_list_entries;\n+\t__u32 num_ldb_credits;\n+\t__u32 max_contiguous_ldb_credits;\n+\t__u32 num_dir_credits;\n+\t__u32 max_contiguous_dir_credits;\n+\t__u32 num_ldb_credit_pools;\n+\t__u32 num_dir_credit_pools;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_CMD_SET_SN_ALLOCATION: Configure a sequence number group\n+ *\n+ * Input parameters:\n+ * - group: Sequence number group ID.\n+ * - num: Number of sequence numbers per queue.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_set_sn_allocation_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 group;\n+\t__u32 num;\n+};\n+\n+/*\n+ * DLB_CMD_GET_SN_ALLOCATION: Get a sequence number group's configuration\n+ *\n+ * Input parameters:\n+ * - group: Sequence number group ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Specified group's number of sequence numbers per queue.\n+ */\n+struct dlb_get_sn_allocation_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 group;\n+\t__u32 padding0;\n+};\n+\n+enum dlb_cq_poll_modes {\n+\tDLB_CQ_POLL_MODE_STD,\n+\tDLB_CQ_POLL_MODE_SPARSE,\n+\n+\t/* NUM_DLB_CQ_POLL_MODE must be last */\n+\tNUM_DLB_CQ_POLL_MODE,\n+};\n+\n+/*\n+ * DLB_CMD_QUERY_CQ_POLL_MODE: Query the CQ poll mode the kernel driver is using\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: CQ poll mode (see enum dlb_cq_poll_modes).\n+ */\n+struct dlb_query_cq_poll_mode_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+};\n+\n+/*\n+ * DLB_CMD_GET_SN_OCCUPANCY: Get a sequence number group's occupancy\n+ *\n+ * Each sequence number group has one or more slots, depending on its\n+ * configuration. I.e.:\n+ * - If configured for 1024 sequence numbers per queue, the group has 1 slot\n+ * - If configured for 512 sequence numbers per queue, the group has 2 slots\n+ * ...\n+ * - If configured for 32 sequence numbers per queue, the group has 32 slots\n+ *\n+ * This ioctl returns the group's number of in-use slots. If its occupancy is\n+ * 0, the group's sequence number allocation can be reconfigured.\n+ *\n+ * Input parameters:\n+ * - group: Sequence number group ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Specified group's number of used slots.\n+ */\n+struct dlb_get_sn_occupancy_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 group;\n+\t__u32 padding0;\n+};\n+\n+enum dlb_user_interface_commands {\n+\tDLB_CMD_GET_DEVICE_VERSION,\n+\tDLB_CMD_CREATE_SCHED_DOMAIN,\n+\tDLB_CMD_GET_NUM_RESOURCES,\n+\tDLB_CMD_GET_DRIVER_VERSION,\n+\tDLB_CMD_SAMPLE_PERF_COUNTERS,\n+\tDLB_CMD_SET_SN_ALLOCATION,\n+\tDLB_CMD_GET_SN_ALLOCATION,\n+\tDLB_CMD_MEASURE_SCHED_COUNTS,\n+\tDLB_CMD_QUERY_CQ_POLL_MODE,\n+\tDLB_CMD_GET_SN_OCCUPANCY,\n+\n+\t/* NUM_DLB_CMD must be last */\n+\tNUM_DLB_CMD,\n+};\n+\n+/*******************************/\n+/* 'domain' device file alerts */\n+/*******************************/\n+\n+/* Scheduling domain device files can be read to receive domain-specific\n+ * notifications, for alerts such as hardware errors.\n+ *\n+ * Each alert is encoded in a 16B message. The first 8B contains the alert ID,\n+ * and the second 8B is optional and contains additional information.\n+ * Applications should cast read data to a struct dlb_domain_alert, and\n+ * interpret the struct's alert_id according to dlb_domain_alert_id. The read\n+ * length must be 16B, or the function will return -EINVAL.\n+ *\n+ * Reads are destructive, and in the case of multiple file descriptors for the\n+ * same domain device file, an alert will be read by only one of the file\n+ * descriptors.\n+ *\n+ * The driver stores alerts in a fixed-size alert ring until they are read. If\n+ * the alert ring fills completely, subsequent alerts will be dropped. It is\n+ * recommended that DLB applications dedicate a thread to perform blocking\n+ * reads on the device file.\n+ */\n+enum dlb_domain_alert_id {\n+\t/* A destination domain queue that this domain connected to has\n+\t * unregistered, and can no longer be sent to. The aux alert data\n+\t * contains the queue ID.\n+\t */\n+\tDLB_DOMAIN_ALERT_REMOTE_QUEUE_UNREGISTER,\n+\t/* A producer port in this domain attempted to send a QE without a\n+\t * credit. aux_alert_data[7:0] contains the port ID, and\n+\t * aux_alert_data[15:8] contains a flag indicating whether the port is\n+\t * load-balanced (1) or directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_PP_OUT_OF_CREDITS,\n+\t/* Software issued an illegal enqueue for a port in this domain. An\n+\t * illegal enqueue could be:\n+\t * - Illegal (excess) completion\n+\t * - Illegal fragment\n+\t * - Illegal enqueue command\n+\t * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]\n+\t * contains a flag indicating whether the port is load-balanced (1) or\n+\t * directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_PP_ILLEGAL_ENQ,\n+\t/* Software issued excess CQ token pops for a port in this domain.\n+\t * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]\n+\t * contains a flag indicating whether the port is load-balanced (1) or\n+\t * directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_PP_EXCESS_TOKEN_POPS,\n+\t/* A enqueue contained either an invalid command encoding or a REL,\n+\t * REL_T, RLS, FWD, FWD_T, FRAG, or FRAG_T from a directed port.\n+\t *\n+\t * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]\n+\t * contains a flag indicating whether the port is load-balanced (1) or\n+\t * directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_ILLEGAL_HCW,\n+\t/* The QID must be valid and less than 128.\n+\t *\n+\t * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]\n+\t * contains a flag indicating whether the port is load-balanced (1) or\n+\t * directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_ILLEGAL_QID,\n+\t/* An enqueue went to a disabled QID.\n+\t *\n+\t * aux_alert_data[7:0] contains the port ID, and aux_alert_data[15:8]\n+\t * contains a flag indicating whether the port is load-balanced (1) or\n+\t * directed (0).\n+\t */\n+\tDLB_DOMAIN_ALERT_DISABLED_QID,\n+\t/* The device containing this domain was reset. All applications using\n+\t * the device need to exit for the driver to complete the reset\n+\t * procedure.\n+\t *\n+\t * aux_alert_data doesn't contain any information for this alert.\n+\t */\n+\tDLB_DOMAIN_ALERT_DEVICE_RESET,\n+\t/* User-space has enqueued an alert.\n+\t *\n+\t * aux_alert_data contains user-provided data.\n+\t */\n+\tDLB_DOMAIN_ALERT_USER,\n+\n+\t/* Number of DLB domain alerts */\n+\tNUM_DLB_DOMAIN_ALERTS\n+};\n+\n+static const char dlb_domain_alert_strings[][128] = {\n+\t\"DLB_DOMAIN_ALERT_REMOTE_QUEUE_UNREGISTER\",\n+\t\"DLB_DOMAIN_ALERT_PP_OUT_OF_CREDITS\",\n+\t\"DLB_DOMAIN_ALERT_PP_ILLEGAL_ENQ\",\n+\t\"DLB_DOMAIN_ALERT_PP_EXCESS_TOKEN_POPS\",\n+\t\"DLB_DOMAIN_ALERT_ILLEGAL_HCW\",\n+\t\"DLB_DOMAIN_ALERT_ILLEGAL_QID\",\n+\t\"DLB_DOMAIN_ALERT_DISABLED_QID\",\n+\t\"DLB_DOMAIN_ALERT_DEVICE_RESET\",\n+\t\"DLB_DOMAIN_ALERT_USER\",\n+};\n+\n+struct dlb_domain_alert {\n+\t__u64 alert_id;\n+\t__u64 aux_alert_data;\n+};\n+\n+/*********************************/\n+/* 'domain' device file commands */\n+/*********************************/\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_LDB_POOL: Configure a load-balanced credit pool.\n+ * Input parameters:\n+ * - num_ldb_credits: Number of load-balanced credits (QED space) for this\n+ *\tpool.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: pool ID.\n+ */\n+struct dlb_create_ldb_pool_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 num_ldb_credits;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_DIR_POOL: Configure a directed credit pool.\n+ * Input parameters:\n+ * - num_dir_credits: Number of directed credits (DQED space) for this pool.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Pool ID.\n+ */\n+struct dlb_create_dir_pool_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 num_dir_credits;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_LDB_QUEUE: Configure a load-balanced queue.\n+ * Input parameters:\n+ * - num_atomic_inflights: This specifies the amount of temporary atomic QE\n+ *\tstorage for this queue. If zero, the queue will not support atomic\n+ *\tscheduling.\n+ * - num_sequence_numbers: This specifies the number of sequence numbers used\n+ *\tby this queue. If zero, the queue will not support ordered scheduling.\n+ *\tIf non-zero, the queue will not support unordered scheduling.\n+ * - num_qid_inflights: The maximum number of QEs that can be inflight\n+ *\t(scheduled to a CQ but not completed) at any time. If\n+ *\tnum_sequence_numbers is non-zero, num_qid_inflights must be set equal\n+ *\tto num_sequence_numbers.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Queue ID.\n+ */\n+struct dlb_create_ldb_queue_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 num_sequence_numbers;\n+\t__u32 num_qid_inflights;\n+\t__u32 num_atomic_inflights;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_DIR_QUEUE: Configure a directed queue.\n+ * Input parameters:\n+ * - port_id: Port ID. If the corresponding directed port is already created,\n+ *\tspecify its ID here. Else this argument must be 0xFFFFFFFF to indicate\n+ *\tthat the queue is being created before the port.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Queue ID.\n+ */\n+struct dlb_create_dir_queue_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__s32 port_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_LDB_PORT: Configure a load-balanced port.\n+ * Input parameters:\n+ * - ldb_credit_pool_id: Load-balanced credit pool this port will belong to.\n+ * - dir_credit_pool_id: Directed credit pool this port will belong to.\n+ * - ldb_credit_high_watermark: Number of load-balanced credits from the pool\n+ *\tthat this port will own.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_high_watermark: Number of directed credits from the pool that\n+ *\tthis port will own.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any directed queues,\n+ *\tthis argument is ignored and the port is given no directed credits.\n+ * - ldb_credit_low_watermark: Load-balanced credit low watermark. When the\n+ *\tport's credits reach this watermark, they become eligible to be\n+ *\trefilled by the DLB as credits until the high watermark\n+ *\t(num_ldb_credits) is reached.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_low_watermark: Directed credit low watermark. When the port's\n+ *\tcredits reach this watermark, they become eligible to be refilled by\n+ *\tthe DLB as credits until the high watermark (num_dir_credits) is\n+ *\treached.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any directed queues,\n+ *\tthis argument is ignored and the port is given no directed credits.\n+ * - ldb_credit_quantum: Number of load-balanced credits for the DLB to refill\n+ *\tper refill operation.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_quantum: Number of directed credits for the DLB to refill per\n+ *\trefill operation.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any directed queues,\n+ *\tthis argument is ignored and the port is given no directed credits.\n+ * - padding0: Reserved for future use.\n+ * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and\n+ *\t1024, inclusive.\n+ * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that\n+ *\tthe CQ interrupt won't fire until there are N or more outstanding CQ\n+ *\ttokens.\n+ * - cq_history_list_size: Number of history list entries. This must be greater\n+ *\tthan or equal to cq_depth.\n+ * - padding1: Reserved for future use.\n+ * - padding2: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: port ID.\n+ */\n+struct dlb_create_ldb_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 ldb_credit_pool_id;\n+\t__u32 dir_credit_pool_id;\n+\t__u16 ldb_credit_high_watermark;\n+\t__u16 ldb_credit_low_watermark;\n+\t__u16 ldb_credit_quantum;\n+\t__u16 dir_credit_high_watermark;\n+\t__u16 dir_credit_low_watermark;\n+\t__u16 dir_credit_quantum;\n+\t__u16 padding0;\n+\t__u16 cq_depth;\n+\t__u16 cq_depth_threshold;\n+\t__u16 cq_history_list_size;\n+\t__u32 padding1;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_CREATE_DIR_PORT: Configure a directed port.\n+ * Input parameters:\n+ * - ldb_credit_pool_id: Load-balanced credit pool this port will belong to.\n+ * - dir_credit_pool_id: Directed credit pool this port will belong to.\n+ * - ldb_credit_high_watermark: Number of load-balanced credits from the pool\n+ *\tthat this port will own.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_high_watermark: Number of directed credits from the pool that\n+ *\tthis port will own.\n+ * - ldb_credit_low_watermark: Load-balanced credit low watermark. When the\n+ *\tport's credits reach this watermark, they become eligible to be\n+ *\trefilled by the DLB as credits until the high watermark\n+ *\t(num_ldb_credits) is reached.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_low_watermark: Directed credit low watermark. When the port's\n+ *\tcredits reach this watermark, they become eligible to be refilled by\n+ *\tthe DLB as credits until the high watermark (num_dir_credits) is\n+ *\treached.\n+ * - ldb_credit_quantum: Number of load-balanced credits for the DLB to refill\n+ *\tper refill operation.\n+ *\n+ *\tIf this port's scheduling domain doesn't have any load-balanced queues,\n+ *\tthis argument is ignored and the port is given no load-balanced\n+ *\tcredits.\n+ * - dir_credit_quantum: Number of directed credits for the DLB to refill per\n+ *\trefill operation.\n+ * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and\n+ *\t1024, inclusive.\n+ * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that\n+ *\tthe CQ interrupt won't fire until there are N or more outstanding CQ\n+ *\ttokens.\n+ * - qid: Queue ID. If the corresponding directed queue is already created,\n+ *\tspecify its ID here. Else this argument must be 0xFFFFFFFF to indicate\n+ *\tthat the port is being created before the queue.\n+ * - padding1: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: Port ID.\n+ */\n+struct dlb_create_dir_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 ldb_credit_pool_id;\n+\t__u32 dir_credit_pool_id;\n+\t__u16 ldb_credit_high_watermark;\n+\t__u16 ldb_credit_low_watermark;\n+\t__u16 ldb_credit_quantum;\n+\t__u16 dir_credit_high_watermark;\n+\t__u16 dir_credit_low_watermark;\n+\t__u16 dir_credit_quantum;\n+\t__u16 cq_depth;\n+\t__u16 cq_depth_threshold;\n+\t__s32 queue_id;\n+\t__u32 padding1;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_START_DOMAIN: Mark the end of the domain configuration. This\n+ *\tmust be called before passing QEs into the device, and no configuration\n+ *\tioctls can be issued once the domain has started. Sending QEs into the\n+ *\tdevice before calling this ioctl will result in undefined behavior.\n+ * Input parameters:\n+ * - (None)\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_start_domain_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_MAP_QID: Map a load-balanced queue to a load-balanced port.\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ * - qid: Load-balanced queue ID.\n+ * - priority: Queue->port service priority.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_map_qid_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 qid;\n+\t__u32 priority;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_UNMAP_QID: Unmap a load-balanced queue to a load-balanced\n+ *\tport.\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ * - qid: Load-balanced queue ID.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_unmap_qid_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 qid;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_ENABLE_LDB_PORT: Enable scheduling to a load-balanced port.\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_enable_ldb_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_ENABLE_DIR_PORT: Enable scheduling to a directed port.\n+ * Input parameters:\n+ * - port_id: Directed port ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_enable_dir_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_DISABLE_LDB_PORT: Disable scheduling to a load-balanced port.\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_disable_ldb_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_DISABLE_DIR_PORT: Disable scheduling to a directed port.\n+ * Input parameters:\n+ * - port_id: Directed port ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_disable_dir_port_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_BLOCK_ON_CQ_INTERRUPT: Block on a CQ interrupt until a QE\n+ *\tarrives for the specified port. If a QE is already present, the ioctl\n+ *\twill immediately return.\n+ *\n+ *\tNote: Only one thread can block on a CQ's interrupt at a time. Doing\n+ *\totherwise can result in hung threads.\n+ *\n+ * Input parameters:\n+ * - port_id: Port ID.\n+ * - is_ldb: True if the port is load-balanced, false otherwise.\n+ * - arm: Tell the driver to arm the interrupt.\n+ * - cq_gen: Current CQ generation bit.\n+ * - padding0: Reserved for future use.\n+ * - cq_va: VA of the CQ entry where the next QE will be placed.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_block_on_cq_interrupt_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u8 is_ldb;\n+\t__u8 arm;\n+\t__u8 cq_gen;\n+\t__u8 padding0;\n+\t__u64 cq_va;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_ENQUEUE_DOMAIN_ALERT: Enqueue a domain alert that will be\n+ *\tread by one reader thread.\n+ *\n+ * Input parameters:\n+ * - aux_alert_data: user-defined auxiliary data.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ */\n+struct dlb_enqueue_domain_alert_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u64 aux_alert_data;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_GET_LDB_QUEUE_DEPTH: Get a load-balanced queue's depth.\n+ * Input parameters:\n+ * - queue_id: The load-balanced queue ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: queue depth.\n+ */\n+struct dlb_get_ldb_queue_depth_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 queue_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_GET_DIR_QUEUE_DEPTH: Get a directed queue's depth.\n+ * Input parameters:\n+ * - queue_id: The directed queue ID.\n+ * - padding0: Reserved for future use.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: queue depth.\n+ */\n+struct dlb_get_dir_queue_depth_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 queue_id;\n+\t__u32 padding0;\n+};\n+\n+/*\n+ * DLB_DOMAIN_CMD_PENDING_PORT_UNMAPS: Get number of queue unmap operations in\n+ *\tprogress for a load-balanced port.\n+ *\n+ *\tNote: This is a snapshot; the number of unmap operations in progress\n+ *\tis subject to change at any time.\n+ *\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ *\n+ * Output parameters:\n+ * - response: pointer to a struct dlb_cmd_response.\n+ *\tresponse.status: Detailed error code. In certain cases, such as if the\n+ *\t\tresponse pointer is invalid, the driver won't set status.\n+ *\tresponse.id: number of unmaps in progress.\n+ */\n+struct dlb_pending_port_unmaps_args {\n+\t/* Output parameters */\n+\t__u64 response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u32 padding0;\n+};\n+\n+enum dlb_domain_user_interface_commands {\n+\tDLB_DOMAIN_CMD_CREATE_LDB_POOL,\n+\tDLB_DOMAIN_CMD_CREATE_DIR_POOL,\n+\tDLB_DOMAIN_CMD_CREATE_LDB_QUEUE,\n+\tDLB_DOMAIN_CMD_CREATE_DIR_QUEUE,\n+\tDLB_DOMAIN_CMD_CREATE_LDB_PORT,\n+\tDLB_DOMAIN_CMD_CREATE_DIR_PORT,\n+\tDLB_DOMAIN_CMD_START_DOMAIN,\n+\tDLB_DOMAIN_CMD_MAP_QID,\n+\tDLB_DOMAIN_CMD_UNMAP_QID,\n+\tDLB_DOMAIN_CMD_ENABLE_LDB_PORT,\n+\tDLB_DOMAIN_CMD_ENABLE_DIR_PORT,\n+\tDLB_DOMAIN_CMD_DISABLE_LDB_PORT,\n+\tDLB_DOMAIN_CMD_DISABLE_DIR_PORT,\n+\tDLB_DOMAIN_CMD_BLOCK_ON_CQ_INTERRUPT,\n+\tDLB_DOMAIN_CMD_ENQUEUE_DOMAIN_ALERT,\n+\tDLB_DOMAIN_CMD_GET_LDB_QUEUE_DEPTH,\n+\tDLB_DOMAIN_CMD_GET_DIR_QUEUE_DEPTH,\n+\tDLB_DOMAIN_CMD_PENDING_PORT_UNMAPS,\n+\n+\t/* NUM_DLB_DOMAIN_CMD must be last */\n+\tNUM_DLB_DOMAIN_CMD,\n+};\n+\n+/*\n+ * Base addresses for memory mapping the consumer queue (CQ) and popcount (PC)\n+ * memory space, and producer port (PP) MMIO space. The CQ, PC, and PP\n+ * addresses are per-port. Every address is page-separated (e.g. LDB PP 0 is at\n+ * 0x2100000 and LDB PP 1 is at 0x2101000).\n+ */\n+#define DLB_LDB_CQ_BASE 0x3000000\n+#define DLB_LDB_CQ_MAX_SIZE 65536\n+#define DLB_LDB_CQ_OFFS(id) (DLB_LDB_CQ_BASE + (id) * DLB_LDB_CQ_MAX_SIZE)\n+\n+#define DLB_DIR_CQ_BASE 0x3800000\n+#define DLB_DIR_CQ_MAX_SIZE 65536\n+#define DLB_DIR_CQ_OFFS(id) (DLB_DIR_CQ_BASE + (id) * DLB_DIR_CQ_MAX_SIZE)\n+\n+#define DLB_LDB_PC_BASE 0x2300000\n+#define DLB_LDB_PC_MAX_SIZE 4096\n+#define DLB_LDB_PC_OFFS(id) (DLB_LDB_PC_BASE + (id) * DLB_LDB_PC_MAX_SIZE)\n+\n+#define DLB_DIR_PC_BASE 0x2200000\n+#define DLB_DIR_PC_MAX_SIZE 4096\n+#define DLB_DIR_PC_OFFS(id) (DLB_DIR_PC_BASE + (id) * DLB_DIR_PC_MAX_SIZE)\n+\n+#define DLB_LDB_PP_BASE 0x2100000\n+#define DLB_LDB_PP_MAX_SIZE 4096\n+#define DLB_LDB_PP_OFFS(id) (DLB_LDB_PP_BASE + (id) * DLB_LDB_PP_MAX_SIZE)\n+\n+#define DLB_DIR_PP_BASE 0x2000000\n+#define DLB_DIR_PP_MAX_SIZE 4096\n+#define DLB_DIR_PP_OFFS(id) (DLB_DIR_PP_BASE + (id) * DLB_DIR_PP_MAX_SIZE)\n+\n+#endif /* __DLB_USER_H */\n", "prefixes": [ "08/27" ] }