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GET /api/patches/74880/?format=api
{ "id": 74880, "url": "http://patches.dpdk.org/api/patches/74880/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-3-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200727220341.29084-3-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200727220341.29084-3-manishc@marvell.com", "date": "2020-07-27T22:03:37", "name": "[v4,2/6] net/qede: define PCI config space specific osals", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4b60b7b34ee9f78456afcdc434080f56018a17bb", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-3-manishc@marvell.com/mbox/", "series": [ { "id": 11335, "url": "http://patches.dpdk.org/api/series/11335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11335", "date": "2020-07-27T22:03:35", "name": "qede: SR-IOV PF driver support", "version": 4, "mbox": "http://patches.dpdk.org/series/11335/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74880/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E4384A052B;\n\tTue, 28 Jul 2020 00:05:00 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C8A031BFE8;\n\tTue, 28 Jul 2020 00:05:00 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 426192C6E\n for <dev@dpdk.org>; Tue, 28 Jul 2020 00:04:59 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06RLjKcY002370; Mon, 27 Jul 2020 15:04:58 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0a-0016f401.pphosted.com with ESMTP id 32gj3qs8q7-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 27 Jul 2020 15:04:58 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 27 Jul 2020 15:04:57 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 27 Jul 2020 15:04:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 27 Jul 2020 15:04:56 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id 4BF473F703F;\n Mon, 27 Jul 2020 15:04:56 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06RM4umg029138;\n Mon, 27 Jul 2020 15:04:56 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06RM4uI6029137;\n Mon, 27 Jul 2020 15:04:56 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=nUDzt2F80IlizjB0fwk9oxUYp+FldBD3y86PSW2SiHs=;\n b=FzqOUVgfLndqCjF3KNMrSyOGQb9gs/UbQhpbUlGuuhFTpGb23vKKIKSFHBQfT6Y5oYWn\n zdEQu+e6C/lTYwy3e3s90o+bOeCjGV68H4uqTpm7rWxQbZJBwIgyC+1Pv4y5+dhyboVX\n BOijT/LT4fcDoHCA+q0i+Vfqpwhd81PsurirB57DleVx6mKHz+t8oCtOzJxVV3G1J+1S\n qtSK+Le3h/FJI1mZLbdxPTyaHoz0pyKoWTDtUtTsToFNO4PjqfUCDfr3M5ujRj/Rqbtr\n uPZ0xG9bhjmw/s7L5Zmo46b/xgCChzqb2n6R4iHxZG53MVBW2Vko93rhRN2SvF5OUj6q hg==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <rosen.xu@intel.com>,\n <tianfei.zhang@intel.com>, <heinrich.kuhn@netronome.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>", "Date": "Mon, 27 Jul 2020 15:03:37 -0700", "Message-ID": "<20200727220341.29084-3-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200727220341.29084-1-manishc@marvell.com>", "References": "<20200727220341.29084-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-27_15:2020-07-27,\n 2020-07-27 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 2/6] net/qede: define PCI config space\n\tspecific osals", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch defines various PCI config space access APIs\nin order to read and find IOV specific PCI capabilities.\n\nWith these definitions implemented, it enables the base\ndriver to do SR-IOV specific initialization and HW specific\nconfiguration required from PF-PMD driver instance.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n drivers/net/qede/base/bcm_osal.h | 14 +++++++++-----\n drivers/net/qede/base/ecore.h | 3 +++\n drivers/net/qede/base/ecore_dev.c | 6 +++---\n drivers/net/qede/base/ecore_sriov.c | 28 +++++++++++++++-------------\n drivers/net/qede/base/meson.build | 2 +-\n drivers/net/qede/qede_main.c | 1 +\n lib/librte_pci/rte_pci.h | 23 +++++++++++++++++++++--\n 7 files changed, 53 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 5d4df5907..5f55cc2ee 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -21,6 +21,7 @@\n #include <rte_ether.h>\n #include <rte_io.h>\n #include <rte_version.h>\n+#include <rte_bus_pci.h>\n \n /* Forward declaration */\n struct ecore_dev;\n@@ -286,11 +287,14 @@ typedef struct osal_list_t {\n \tOSAL_LIST_PUSH_HEAD(new_entry, list)\n \n /* PCI config space */\n-\n-#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing\n-#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing\n-#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing\n-#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0\n+#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 1, address)\n+#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 2, address)\n+#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 4, address)\n+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \\\n+\trte_pci_find_next_ext_capability((dev)->pci_dev, cap)\n #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0\n #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing\n #define OSAL_BAR_SIZE(dev, bar_id) 0\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex 63bd7466a..750e99a8f 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -937,6 +937,9 @@ struct ecore_dev {\n \tstruct ecore_dbg_feature\tdbg_features[DBG_FEATURE_NUM];\n \tstruct ecore_dbg_params\t\tdbg_params;\n \tosal_mutex_t\t\t\tdbg_lock;\n+\n+\t/* DPDK specific ecore field */\n+\tstruct rte_pci_device\t\t*pci_dev;\n };\n \n enum ecore_hsi_def_type {\ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 35a8394de..e895dee40 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -2787,7 +2787,7 @@ static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,\n \t\treturn ECORE_IO;\n \t}\n \n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);\n \twr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;\n \tecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);\n \n@@ -5499,9 +5499,9 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,\n \tu32 tmp;\n \n \t/* Read Vendor Id / Device Id */\n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID,\n \t\t\t\t &p_dev->vendor_id);\n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID,\n \t\t\t\t &p_dev->device_id);\n \n \t/* Determine type */\ndiff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c\nindex e60257e19..dac4cbee8 100644\n--- a/drivers/net/qede/base/ecore_sriov.c\n+++ b/drivers/net/qede/base/ecore_sriov.c\n@@ -417,15 +417,16 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)\n \tint pos = iov->pos;\n \n \tDP_VERBOSE(p_dev, ECORE_MSG_IOV, \"sriov ext pos %d\\n\", pos);\n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_CTRL, &iov->ctrl);\n \n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_TOTAL_VF,\n+\t\t\t\t &iov->total_vfs);\n \tOSAL_PCI_READ_CONFIG_WORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);\n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_INITIAL_VF,\n+\t\t\t\t pos + RTE_PCI_SRIOV_INITIAL_VF,\n \t\t\t\t &iov->initial_vfs);\n \n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_NUM_VF,\n+\t\t\t\t &iov->num_vfs);\n \tif (iov->num_vfs) {\n \t\t/* @@@TODO - in future we might want to add an OSAL here to\n \t\t * allow each OS to decide on its own how to act.\n@@ -437,20 +438,21 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)\n \t}\n \n \tOSAL_PCI_READ_CONFIG_WORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_VF_OFFSET, &iov->offset);\n+\t\t\t\t pos + RTE_PCI_SRIOV_VF_OFFSET, &iov->offset);\n \n \tOSAL_PCI_READ_CONFIG_WORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_VF_STRIDE, &iov->stride);\n+\t\t\t\t pos + RTE_PCI_SRIOV_VF_STRIDE, &iov->stride);\n \n-\tOSAL_PCI_READ_CONFIG_WORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);\n+\tOSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_VF_DID,\n+\t\t\t\t &iov->vf_device_id);\n \n \tOSAL_PCI_READ_CONFIG_DWORD(p_dev,\n-\t\t\t\t pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);\n+\t\t\t\t pos + RTE_PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);\n \n-\tOSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + PCI_SRIOV_CAP, &iov->cap);\n+\tOSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + RTE_PCI_SRIOV_CAP, &iov->cap);\n \n-\tOSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);\n+\tOSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + RTE_PCI_SRIOV_FUNC_LINK,\n+\t\t\t\t &iov->link);\n \n \tDP_VERBOSE(p_dev, ECORE_MSG_IOV, \"IOV info: nres %d, cap 0x%x,\"\n \t\t \"ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d,\"\n@@ -669,7 +671,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn)\n \n \t/* Learn the PCI configuration */\n \tpos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev,\n-\t\t\t\t\t PCI_EXT_CAP_ID_SRIOV);\n+\t\t\t\t\t RTE_PCI_EXT_CAP_ID_SRIOV);\n \tif (!pos) {\n \t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV, \"No PCIe IOV support\\n\");\n \t\treturn ECORE_SUCCESS;\ndiff --git a/drivers/net/qede/base/meson.build b/drivers/net/qede/base/meson.build\nindex 59b41c895..03a6c44f5 100644\n--- a/drivers/net/qede/base/meson.build\n+++ b/drivers/net/qede/base/meson.build\n@@ -52,6 +52,6 @@ foreach flag: error_cflags\n endforeach\n \n base_lib = static_library('qede_base', sources,\n-\tdependencies: static_rte_net,\n+\tdependencies: [static_rte_net, static_rte_bus_pci],\n \tc_args: c_args)\n base_objs = base_lib.extract_all_objects()\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 987a6f1e1..d919f9f11 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)\n \tedev->regview = pci_dev->mem_resource[0].addr;\n \tedev->doorbells = pci_dev->mem_resource[2].addr;\n \tedev->db_size = pci_dev->mem_resource[2].len;\n+\tedev->pci_dev = pci_dev;\n }\n \n static int\ndiff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h\nindex fec51e15a..a018a6e9a 100644\n--- a/lib/librte_pci/rte_pci.h\n+++ b/lib/librte_pci/rte_pci.h\n@@ -31,12 +31,31 @@ extern \"C\" {\n #define RTE_PCI_CFG_SPACE_SIZE\t\t256\n #define RTE_PCI_CFG_SPACE_EXP_SIZE\t4096\n \n+#define RTE_PCI_VENDOR_ID\t0x00\t/* 16 bits */\n+#define RTE_PCI_DEVICE_ID\t0x02\t/* 16 bits */\n+\n+/* PCI Express capability registers */\n+#define RTE_PCI_EXP_DEVCTL\t8\t/* Device Control */\n+\n /* Extended Capabilities (PCI-X 2.0 and Express) */\n #define RTE_PCI_EXT_CAP_ID(header)\t(header & 0x0000ffff)\n #define RTE_PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n \n-#define RTE_PCI_EXT_CAP_ID_ERR\t0x01\t/* Advanced Error Reporting */\n-#define RTE_PCI_EXT_CAP_ID_DSN\t0x03\t/* Device Serial Number */\n+#define RTE_PCI_EXT_CAP_ID_ERR\t\t0x01\t/* Advanced Error Reporting */\n+#define RTE_PCI_EXT_CAP_ID_DSN\t\t0x03\t/* Device Serial Number */\n+#define RTE_PCI_EXT_CAP_ID_SRIOV\t0x10\t/* SR-IOV*/\n+\n+/* Single Root I/O Virtualization */\n+#define RTE_PCI_SRIOV_CAP\t\t0x04\t/* SR-IOV Capabilities */\n+#define RTE_PCI_SRIOV_CTRL\t\t0x08\t/* SR-IOV Control */\n+#define RTE_PCI_SRIOV_INITIAL_VF\t0x0c\t/* Initial VFs */\n+#define RTE_PCI_SRIOV_TOTAL_VF\t\t0x0e\t/* Total VFs */\n+#define RTE_PCI_SRIOV_NUM_VF\t\t0x10\t/* Number of VFs */\n+#define RTE_PCI_SRIOV_FUNC_LINK\t\t0x12\t/* Function Dependency Link */\n+#define RTE_PCI_SRIOV_VF_OFFSET\t\t0x14\t/* First VF Offset */\n+#define RTE_PCI_SRIOV_VF_STRIDE\t\t0x16\t/* Following VF Stride */\n+#define RTE_PCI_SRIOV_VF_DID\t\t0x1a\t/* VF Device ID */\n+#define RTE_PCI_SRIOV_SUP_PGSIZE\t0x1c\t/* Supported Page Sizes */\n \n /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */\n #define PCI_PRI_FMT \"%.4\" PRIx32 \":%.2\" PRIx8 \":%.2\" PRIx8 \".%\" PRIx8\n", "prefixes": [ "v4", "2/6" ] }