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GET /api/patches/74879/?format=api
{ "id": 74879, "url": "http://patches.dpdk.org/api/patches/74879/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-2-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200727220341.29084-2-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200727220341.29084-2-manishc@marvell.com", "date": "2020-07-27T22:03:36", "name": "[v4,1/6] drivers: add generic API to find PCI extended cap", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "244e78b45be71f02c6b7b26113f294262c375db0", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-2-manishc@marvell.com/mbox/", "series": [ { "id": 11335, "url": "http://patches.dpdk.org/api/series/11335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11335", "date": "2020-07-27T22:03:35", "name": "qede: SR-IOV PF driver support", "version": 4, "mbox": "http://patches.dpdk.org/series/11335/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74879/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74879/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 61865A052B;\n\tTue, 28 Jul 2020 00:04:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3E6201BFC9;\n\tTue, 28 Jul 2020 00:04:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A415E1BFC8\n for <dev@dpdk.org>; Tue, 28 Jul 2020 00:04:34 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06RLkMTi021442; Mon, 27 Jul 2020 15:04:34 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 32gm8ngkdb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 27 Jul 2020 15:04:33 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 27 Jul 2020 15:04:32 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 27 Jul 2020 15:04:32 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id 1B1563F703F;\n Mon, 27 Jul 2020 15:04:32 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06RM4VE1029134;\n Mon, 27 Jul 2020 15:04:31 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06RM4V8U029124;\n Mon, 27 Jul 2020 15:04:31 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=A5Ag8xWrbJpyFa1Q+XbnivXNYiUQuhh9cMODM3cXUhA=;\n b=Y7yXmudIuJNWA+cnZKVDqCkCsDPqb9pNloszFKMh9RkILGmGx+jLF7IKs+d3pe+aobpk\n yYkOTfP4KxGrohgJLQYwww5dCiPh2i2u2z0/ZtT35g+3+BuiZzh809YwLU7E6z+4sc71\n eemL8UGCd6lPS02LKMuap/G4Z6ydHzbeohC3XFqEHBIPPBPjqNdH2YotNrlb7OmA/+TO\n 3SyWGyNKaPwqt/6GwX/ghOVsc2qm9xh3NhdkWWjO224WBlQ13+jJ5UhkkIF6ZAk6wOiQ\n tPWcxWoWRVFXBJzuU1kUCbvsXaNlDagN5o6EpZTZy2C58eV5NxwMdWUVyiNkyy199/2D oA==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <rosen.xu@intel.com>,\n <tianfei.zhang@intel.com>, <heinrich.kuhn@netronome.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>", "Date": "Mon, 27 Jul 2020 15:03:36 -0700", "Message-ID": "<20200727220341.29084-2-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200727220341.29084-1-manishc@marvell.com>", "References": "<20200727220341.29084-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-27_15:2020-07-27,\n 2020-07-27 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 1/6] drivers: add generic API to find PCI\n\textended cap", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "By adding generic API, this patch removes individual\nfunctions/defines implemented by drivers to find extended\nPCI capabilities.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/bus/pci/pci_common.c | 43 ++++++++++++++++++\n drivers/bus/pci/rte_bus_pci.h | 20 +++++++++\n drivers/bus/pci/rte_bus_pci_version.map | 6 +++\n drivers/net/ice/ice_ethdev.c | 51 +---------------------\n drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 +-------------------\n drivers/raw/ifpga/ifpga_rawdev.c | 6 ---\n lib/librte_pci/rte_pci.h | 16 +++++++\n 7 files changed, 89 insertions(+), 101 deletions(-)", "diff": "diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c\nindex a8e5fd52c..98c1f8155 100644\n--- a/drivers/bus/pci/pci_common.c\n+++ b/drivers/bus/pci/pci_common.c\n@@ -665,6 +665,49 @@ rte_pci_get_iommu_class(void)\n \treturn iova_mode;\n }\n \n+off_t\n+rte_pci_find_next_ext_capability(struct rte_pci_device *dev, uint32_t cap)\n+{\n+\toff_t offset = RTE_PCI_CFG_SPACE_SIZE;\n+\tuint32_t header;\n+\tint ttl;\n+\n+\t/* minimum 8 bytes per capability */\n+\tttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;\n+\n+\tif (rte_pci_read_config(dev, &header, 4, offset) < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"error in reading extended capabilities\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/*\n+\t * If we have no capabilities, this is indicated by cap ID,\n+\t * cap version and next pointer all being 0.\n+\t */\n+\tif (header == 0)\n+\t\treturn 0;\n+\n+\twhile (ttl != 0) {\n+\t\tif (RTE_PCI_EXT_CAP_ID(header) == cap)\n+\t\t\treturn offset;\n+\n+\t\toffset = RTE_PCI_EXT_CAP_NEXT(header);\n+\n+\t\tif (offset < RTE_PCI_CFG_SPACE_SIZE)\n+\t\t\tbreak;\n+\n+\t\tif (rte_pci_read_config(dev, &header, 4, offset) < 0) {\n+\t\t\tRTE_LOG(ERR, EAL,\n+\t\t\t\t\"error in reading extended capabilities\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tttl--;\n+\t}\n+\n+\treturn 0;\n+}\n+\n struct rte_pci_bus rte_pci_bus = {\n \t.bus = {\n \t\t.scan = rte_pci_scan,\ndiff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h\nindex 29bea6d70..f11af3762 100644\n--- a/drivers/bus/pci/rte_bus_pci.h\n+++ b/drivers/bus/pci/rte_bus_pci.h\n@@ -224,6 +224,26 @@ void rte_pci_unmap_device(struct rte_pci_device *dev);\n */\n void rte_pci_dump(FILE *f);\n \n+/**\n+ * Find device's extended PCI capability.\n+ *\n+ * @param dev\n+ * A pointer to rte_pci_device structure.\n+ *\n+ * @param cap\n+ * Extended capability to be found, which can be any from\n+ * RTE_PCI_EXT_CAP_ID_*, defined in librte_pci.\n+ *\n+ * @return\n+ * > 0: The offset of the next matching extended capability structure\n+ * within the device's PCI configuration space.\n+ * < 0: An error in PCI config space read.\n+ * = 0: Device does not support it.\n+ */\n+__rte_experimental\n+off_t rte_pci_find_next_ext_capability(struct rte_pci_device *dev,\n+\t\t\t\t uint32_t cap);\n+\n /**\n * Register a PCI driver.\n *\ndiff --git a/drivers/bus/pci/rte_bus_pci_version.map b/drivers/bus/pci/rte_bus_pci_version.map\nindex 012d817e1..b5322660d 100644\n--- a/drivers/bus/pci/rte_bus_pci_version.map\n+++ b/drivers/bus/pci/rte_bus_pci_version.map\n@@ -16,3 +16,9 @@ DPDK_20.0 {\n \n \tlocal: *;\n };\n+\n+EXPERIMENTAL {\n+\tglobal:\n+\n+\trte_pci_find_next_ext_capability;\n+};\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 7dd3fcd27..6c8cbea5c 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -1730,53 +1730,6 @@ ice_pf_setup(struct ice_pf *pf)\n \treturn 0;\n }\n \n-/* PCIe configuration space setting */\n-#define PCI_CFG_SPACE_SIZE 256\n-#define PCI_CFG_SPACE_EXP_SIZE 4096\n-#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)\n-#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)\n-#define PCI_EXT_CAP_ID_DSN 0x03\n-\n-static int\n-ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n-{\n-\tuint32_t header;\n-\tint ttl;\n-\tint pos = PCI_CFG_SPACE_SIZE;\n-\n-\t/* minimum 8 bytes per capability */\n-\tttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;\n-\n-\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\tPMD_INIT_LOG(ERR, \"ice error reading extended capabilities\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\t/*\n-\t * If we have no capabilities, this is indicated by cap ID,\n-\t * cap version and next pointer all being 0.\n-\t */\n-\tif (header == 0)\n-\t\treturn 0;\n-\n-\twhile (ttl-- > 0) {\n-\t\tif (PCI_EXT_CAP_ID(header) == cap)\n-\t\t\treturn pos;\n-\n-\t\tpos = PCI_EXT_CAP_NEXT(header);\n-\n-\t\tif (pos < PCI_CFG_SPACE_SIZE)\n-\t\t\tbreak;\n-\n-\t\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\t\tPMD_INIT_LOG(ERR, \"ice error reading extended capabilities\\n\");\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n /*\n * Extract device serial number from PCIe Configuration Space and\n * determine the pkg file path according to the DSN.\n@@ -1784,12 +1737,12 @@ ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n static int\n ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)\n {\n-\tint pos;\n+\toff_t pos;\n \tchar opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];\n \tuint32_t dsn_low, dsn_high;\n \tmemset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);\n \n-\tpos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);\n+\tpos = rte_pci_find_next_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);\n \n \tif (pos) {\n \t\trte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\nindex 0b9db974e..dbab4f8cb 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n+++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c\n@@ -746,59 +746,15 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)\n \treturn 0;\n }\n \n-#define PCI_CFG_SPACE_SIZE\t256\n-#define PCI_CFG_SPACE_EXP_SIZE\t4096\n-#define PCI_EXT_CAP_ID(header)\t\t(int)(header & 0x0000ffff)\n-#define PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n-#define PCI_EXT_CAP_ID_DSN\t0x03\n-static int\n-nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)\n-{\n-\tuint32_t header;\n-\tint ttl;\n-\tint pos = PCI_CFG_SPACE_SIZE;\n-\n-\t/* minimum 8 bytes per capability */\n-\tttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;\n-\n-\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\tprintf(\"nfp error reading extended capabilities\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\t/*\n-\t * If we have no capabilities, this is indicated by cap ID,\n-\t * cap version and next pointer all being 0.\n-\t */\n-\tif (header == 0)\n-\t\treturn 0;\n-\n-\twhile (ttl-- > 0) {\n-\t\tif (PCI_EXT_CAP_ID(header) == cap)\n-\t\t\treturn pos;\n-\n-\t\tpos = PCI_EXT_CAP_NEXT(header);\n-\t\tif (pos < PCI_CFG_SPACE_SIZE)\n-\t\t\tbreak;\n-\n-\t\tif (rte_pci_read_config(dev, &header, 4, pos) < 0) {\n-\t\t\tprintf(\"nfp error reading extended capabilities\\n\");\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n static int\n nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)\n {\n \tuint16_t tmp;\n \tuint8_t serial[6];\n \tint serial_len = 6;\n-\tint pos;\n+\toff_t pos;\n \n-\tpos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);\n+\tpos = rte_pci_find_next_ext_capability(dev, RTE_PCI_EXT_CAP_ID_DSN);\n \tif (pos <= 0) {\n \t\tprintf(\"PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\\n\");\n \t\treturn -1;\ndiff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c\nindex cc25c662b..f8205a3c7 100644\n--- a/drivers/raw/ifpga/ifpga_rawdev.c\n+++ b/drivers/raw/ifpga/ifpga_rawdev.c\n@@ -41,12 +41,6 @@\n #include \"ifpga_rawdev.h\"\n #include \"ipn3ke_rawdev_api.h\"\n \n-#define RTE_PCI_EXT_CAP_ID_ERR 0x01\t/* Advanced Error Reporting */\n-#define RTE_PCI_CFG_SPACE_SIZE 256\n-#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096\n-#define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)\n-#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)\n-\n #define PCI_VENDOR_ID_INTEL 0x8086\n /* PCI Device ID */\n #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD\ndiff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h\nindex a03235da1..fec51e15a 100644\n--- a/lib/librte_pci/rte_pci.h\n+++ b/lib/librte_pci/rte_pci.h\n@@ -22,6 +22,22 @@ extern \"C\" {\n #include <inttypes.h>\n #include <sys/types.h>\n \n+\n+/*\n+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of\n+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of\n+ * configuration space.\n+ */\n+#define RTE_PCI_CFG_SPACE_SIZE\t\t256\n+#define RTE_PCI_CFG_SPACE_EXP_SIZE\t4096\n+\n+/* Extended Capabilities (PCI-X 2.0 and Express) */\n+#define RTE_PCI_EXT_CAP_ID(header)\t(header & 0x0000ffff)\n+#define RTE_PCI_EXT_CAP_NEXT(header)\t((header >> 20) & 0xffc)\n+\n+#define RTE_PCI_EXT_CAP_ID_ERR\t0x01\t/* Advanced Error Reporting */\n+#define RTE_PCI_EXT_CAP_ID_DSN\t0x03\t/* Device Serial Number */\n+\n /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */\n #define PCI_PRI_FMT \"%.4\" PRIx32 \":%.2\" PRIx8 \":%.2\" PRIx8 \".%\" PRIx8\n #define PCI_PRI_STR_SIZE sizeof(\"XXXXXXXX:XX:XX.X\")\n", "prefixes": [ "v4", "1/6" ] }