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GET /api/patches/74428/?format=api
{ "id": 74428, "url": "http://patches.dpdk.org/api/patches/74428/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200719101816.16406-3-ophirmu@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200719101816.16406-3-ophirmu@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200719101816.16406-3-ophirmu@mellanox.com", "date": "2020-07-19T10:18:10", "name": "[v3,2/8] net/mlx5: replace Linux specific calls with rte API", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e98e54085e653eeb137c99e2ce20772149b000c0", "submitter": { "id": 793, "url": "http://patches.dpdk.org/api/people/793/?format=api", "name": "Ophir Munk", "email": "ophirmu@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200719101816.16406-3-ophirmu@mellanox.com/mbox/", "series": [ { "id": 11146, "url": "http://patches.dpdk.org/api/series/11146/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11146", "date": "2020-07-19T10:18:08", "name": "mlx5 PMD multi OS support - part #3", "version": 3, "mbox": "http://patches.dpdk.org/series/11146/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74428/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74428/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=+F5jJCtnY9WGMZ6qmeA9OlY8OabVv4UvBk+4GugFrg0=;\n b=Jn2EgzzCXYzas4u7KvdMLNHhieE6x5TO+l/vPNDKqEGk88MFtzybVPPNJ2zT2taw44U1+LgIKbvzXh0dnMISB1Zq7mDs4jKrUFz8Feo6p+Yqca2JChZ4z8bvTIPSqCkrniIAnfuFjpRK1iBmaEaGLQEM813vksKbxh5ZLuXm16XCRGEcSuZykVYSoHGymXmhOBLl6u3By9D9BUXGQaGB6Jy2YpKcwENsfFPl3uaiXaR+ZIkZD5Ly01QA2YIXZ0LwulyDtYW2y89e1TsidflYZGHYfaHJCG0QUea7h2MzjO+5SLEr3/xPzJq4TIgXvuXYL4g+ERDjBajGMAFRPUpdHg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=mellanox.com; dmarc=pass action=none header.from=mellanox.com;\n dkim=pass header.d=mellanox.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=+F5jJCtnY9WGMZ6qmeA9OlY8OabVv4UvBk+4GugFrg0=;\n b=j829PtmPGINE5mp0D3ZrdG117lXGLVlhT+7iqjyD/1dPvZ4pnuaLBS2wkqvCgsfEuhq4x5IrMHRJbOv/gMLWc6yKYO9NC9kW8gEyv8r0aazADsbenxhue24YJLv8e2DVdEFs1TTtm6J6ym8FpUzKrQPh0ySEeCgsSaADYIDPmcs=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com;", "From": "Ophir Munk <ophirmu@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Raslan Darawsheh <rasland@mellanox.com>,\n Ophir Munk <ophirmu@mellanox.com>,\n Matan Azrad <matan@mellanox.com>", "Date": "Sun, 19 Jul 2020 10:18:10 +0000", "Message-Id": "<20200719101816.16406-3-ophirmu@mellanox.com>", "X-Mailer": [ "git-send-email 2.8.4", "git-send-email 2.8.4" ], "In-Reply-To": "<20200719101816.16406-1-ophirmu@mellanox.com>", "References": "<20200719071112.8540-9-ophirmu@mellanox.com>\n <20200719101816.16406-1-ophirmu@mellanox.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "AM0PR05CA0090.eurprd05.prod.outlook.com\n (2603:10a6:208:136::30) To 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I1fdXrXE/D2UPQ6SV3HXw54eGJlr8CW9ld1HcQpyi1AO5G4Q4kObjCB9JMdjykYCqqmeBrtU5VS97Q69vcecsUPh9ovg29kbGKY6dPn+j5Zi7RQIxSzdQ+is7F0TUBzxvWXEBoYbWL7gRXUuuleizkJT3afrFzkqZ44/vYimC3dVYk0XONzdbKaWxzzztp7cln7mFSAc6O1u+blbJRCV6nrVjNKWAb4Z7cF2hAuhqB6mhyyiRpB8HaqXlGgCjeOhd4ndBnydQMtvWkaQDLjCCV0tSD7joZjQ8rg9OGhcZ4554dlKSsF4wrnB2ivKNLFaHZD2ZeAp2DgGKF7Nbo5Mzw==", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:AM0PR05MB4209.eurprd05.prod.outlook.com; PTR:; CAT:NONE;\n SFTY:;\n SFS:(4636009)(396003)(346002)(376002)(136003)(39860400002)(366004)(5660300002)(316002)(2906002)(36756003)(54906003)(186003)(2616005)(6666004)(16526019)(4326008)(83380400001)(956004)(30864003)(6916009)(26005)(478600001)(52116002)(7696005)(107886003)(66556008)(86362001)(66476007)(66946007)(1076003)(55016002)(8936002)(8676002)(8886007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData": "\n S1J2aPI+H1clQWAFqowuP2k77DWeZFXM48i922Ml4E9+wvzl5JtgaIwcRNTTVPRtWZDSned5OHF1CUbxOazsq7ZHisQ0iOuG4SHymB+q9GPsC5yQoIAPwyX4BJtjOn8HwheDnoaN2lgmzQev6S7twnZa4GwyrXwoMdnyVrREYb+QE1keaNeqWAMCqjy0x2sR7y71nO51mGaIt4xPdESQ1wn7vyM48nH4LFUOdRZ27AR78uN2pnCVPjC5NvIAbKSRaFiCpcHqHnqqJifXi03j88hvhie79npMc5lB17t5HYhZOFaN0gCveQlYjfi2UGWTDUfVLeU/EfzllfXnx3Dk5K0g/QxKqfMTxXg/sXn7j1QCYDBx40IXdmEjKD1CYxhSFD3JJOqmRkRzhp5Cu8uzCKxlXFMNXMGmXmh5yj0YBzOY5dwJfBGQleb7xTnw0JfE6jOD50IuqSs544l8qyp1ZxCwn4Ks2682kg/5aUqwKdYEaW9tHnAfuJdU8ZhJ0trh", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ea04e5a5-2662-4f33-099d-08d82bcd13b9", "X-MS-Exchange-CrossTenant-AuthSource": "AM0PR05MB4209.eurprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Jul 2020 10:18:27.4847 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n VM9naOaB/ZzkhPHvPEDUxtAWJoKFJCDQTOlz+ZeB7TMQMzn9DNEH/dSH5a4ETUKX5xmEpoFkgOHD3yMJgc6h3g==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM0PR05MB6324", "Subject": "[dpdk-dev] [PATCH v3 2/8] net/mlx5: replace Linux specific calls\n\twith rte API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The following Linux calls are replaced by their matching rte APIs.\n\nmmap ==> rte_mem_map()\nmunmap == >rte_mem_unmap()\nsysconf(_SC_PAGESIZE) ==> rte_mem_page_size()\n\nSigned-off-by: Ophir Munk <ophirmu@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 9 ++++++-\n drivers/common/mlx5/mlx5_prm.h | 4 ++--\n drivers/net/mlx5/linux/mlx5_os.c | 11 ++++++---\n drivers/net/mlx5/linux/mlx5_verbs.c | 1 -\n drivers/net/mlx5/mlx5_flow_dv.c | 9 ++++++-\n drivers/net/mlx5/mlx5_rxq.c | 9 ++++++-\n drivers/net/mlx5/mlx5_txpp.c | 15 ++++++++++--\n drivers/net/mlx5/mlx5_txq.c | 46 ++++++++++++++++++++++++++++--------\n 8 files changed, 83 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 757c55e..972f804 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -5,6 +5,7 @@\n \n #include <rte_errno.h>\n #include <rte_malloc.h>\n+#include <rte_eal_paging.h>\n \n #include \"mlx5_prm.h\"\n #include \"mlx5_devx_cmds.h\"\n@@ -222,7 +223,13 @@ mlx5_devx_cmd_mkey_create(void *ctx,\n \t\treturn NULL;\n \t}\n \tmemset(in, 0, in_size_dw * 4);\n-\tpgsize = sysconf(_SC_PAGESIZE);\n+\tpgsize = rte_mem_page_size();\n+\tif (pgsize == (size_t)-1) {\n+\t\tmlx5_free(mkey);\n+\t\tDRV_LOG(ERR, \"Failed to get page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n \tMLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);\n \tmkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);\n \tif (klm_num > 0) {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex d7d6cf8..4847c6e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -267,10 +267,10 @@\n #define MLX5_MAX_LOG_RQ_SEGS 5u\n \n /* The alignment needed for WQ buffer. */\n-#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)\n+#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()\n \n /* The alignment needed for CQ buffer. */\n-#define MLX5_CQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)\n+#define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()\n \n /* Completion mode. */\n enum mlx5_completion_mode {\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 7c29a29..68420af 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -10,7 +10,6 @@\n #include <stdlib.h>\n #include <errno.h>\n #include <net/if.h>\n-#include <sys/mman.h>\n #include <linux/rtnetlink.h>\n #include <linux/sockios.h>\n #include <linux/ethtool.h>\n@@ -37,6 +36,7 @@\n #include <rte_spinlock.h>\n #include <rte_string_fns.h>\n #include <rte_alarm.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -134,7 +134,7 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)\n * Verbs callback to allocate a memory. This function should allocate the space\n * according to the size provided residing inside a huge page.\n * Please note that all allocation must respect the alignment from libmlx5\n- * (i.e. currently sysconf(_SC_PAGESIZE)).\n+ * (i.e. currently rte_mem_page_size()).\n *\n * @param[in] size\n * The size in bytes of the memory to allocate.\n@@ -149,8 +149,13 @@ mlx5_alloc_verbs_buf(size_t size, void *data)\n {\n \tstruct mlx5_priv *priv = data;\n \tvoid *ret;\n-\tsize_t alignment = sysconf(_SC_PAGESIZE);\n \tunsigned int socket = SOCKET_ID_ANY;\n+\tsize_t alignment = rte_mem_page_size();\n+\tif (alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n \n \tif (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {\n \t\tconst struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 6b59fa1..5ac6982 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -7,7 +7,6 @@\n #include <string.h>\n #include <stdint.h>\n #include <unistd.h>\n-#include <sys/mman.h>\n #include <inttypes.h>\n \n /* Verbs header. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 3ab2931..68dff23 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -29,6 +29,7 @@\n #include <rte_gre.h>\n #include <rte_vxlan.h>\n #include <rte_gtp.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_devx_cmds.h>\n #include <mlx5_prm.h>\n@@ -4182,7 +4183,13 @@ flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)\n \t\t\tMLX5_COUNTERS_PER_POOL +\n \t\t\tsizeof(struct mlx5_counter_stats_raw)) * raws_n +\n \t\t\tsizeof(struct mlx5_counter_stats_mem_mng);\n-\tuint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, sysconf(_SC_PAGESIZE),\n+\tsize_t pgsize = rte_mem_page_size();\n+\tif (pgsize == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tuint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,\n \t\t\t\t SOCKET_ID_ANY);\n \tint i;\n \ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 67d996c..9e7df8e 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -28,6 +28,7 @@\n #include <rte_interrupts.h>\n #include <rte_debug.h>\n #include <rte_io.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -1233,8 +1234,14 @@ mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)\n \t/* Calculate and allocate WQ memory space. */\n \twqe_size = 1 << log_wqe_size; /* round up power of two.*/\n \twq_size = wqe_n * wqe_size;\n+\tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n+\tif (alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n \tbuf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,\n-\t\t\t MLX5_WQE_BUF_ALIGNMENT, rxq_ctrl->socket);\n+\t\t\t alignment, rxq_ctrl->socket);\n \tif (!buf)\n \t\treturn NULL;\n \trxq_data->wqes = buf;\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex f840551..14d4a66 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -10,6 +10,7 @@\n #include <rte_alarm.h>\n #include <rte_malloc.h>\n #include <rte_cycles.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_malloc.h>\n \n@@ -249,10 +250,15 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n \tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n-\tsize_t page_size = sysconf(_SC_PAGESIZE);\n+\tsize_t page_size;\n \tuint32_t umem_size, umem_dbrec;\n \tint ret;\n \n+\tpage_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\treturn -ENOMEM;\n+\t}\n \t/* Allocate memory buffer for CQEs and doorbell record. */\n \tumem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_REARM_CQ_SIZE;\n \tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n@@ -472,10 +478,15 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n \tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n-\tsize_t page_size = sysconf(_SC_PAGESIZE);\n+\tsize_t page_size;\n \tuint32_t umem_size, umem_dbrec;\n \tint ret;\n \n+\tpage_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\treturn -ENOMEM;\n+\t}\n \tsh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\t\t\t MLX5_TXPP_REARM_SQ_SIZE *\n \t\t\t\t sizeof(struct mlx5_txpp_ts),\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 4a73299..d245a54 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -8,7 +8,6 @@\n #include <string.h>\n #include <stdint.h>\n #include <unistd.h>\n-#include <sys/mman.h>\n #include <inttypes.h>\n \n /* Verbs header. */\n@@ -26,6 +25,7 @@\n #include <rte_malloc.h>\n #include <rte_ethdev_driver.h>\n #include <rte_common.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -344,10 +344,14 @@ txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)\n {\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n \tstruct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));\n-\tconst size_t page_size = sysconf(_SC_PAGESIZE);\n #ifndef RTE_ARCH_64\n \tunsigned int lock_idx;\n #endif\n+\tconst size_t page_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t}\n \n \tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\treturn;\n@@ -386,7 +390,12 @@ txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)\n \tvoid *addr;\n \tuintptr_t uar_va;\n \tuintptr_t offset;\n-\tconst size_t page_size = sysconf(_SC_PAGESIZE);\n+\tconst size_t page_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n \n \tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\treturn 0;\n@@ -397,9 +406,9 @@ txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)\n \t */\n \tuar_va = (uintptr_t)txq_ctrl->bf_reg;\n \toffset = uar_va & (page_size - 1); /* Offset in page. */\n-\taddr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,\n-\t\t\ttxq_ctrl->uar_mmap_offset);\n-\tif (addr == MAP_FAILED) {\n+\taddr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,\n+\t\t\t fd, txq_ctrl->uar_mmap_offset);\n+\tif (!addr) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"port %u mmap failed for BF reg of txq %u\",\n \t\t\ttxq->port_id, txq->idx);\n@@ -422,13 +431,17 @@ static void\n txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)\n {\n \tstruct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));\n-\tconst size_t page_size = sysconf(_SC_PAGESIZE);\n \tvoid *addr;\n+\tconst size_t page_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t}\n \n \tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\treturn;\n \taddr = ppriv->uar_table[txq_ctrl->txq.idx];\n-\tmunmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);\n+\trte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);\n }\n \n /**\n@@ -642,13 +655,20 @@ mlx5_txq_obj_devx_new(struct rte_eth_dev *dev, uint16_t idx)\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n \tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n \tstruct mlx5_txq_obj *txq_obj = NULL;\n-\tsize_t page_size = sysconf(_SC_PAGESIZE);\n+\tsize_t page_size;\n \tstruct mlx5_cqe *cqe;\n \tuint32_t i, nqe;\n+\tsize_t alignment = (size_t)-1;\n \tint ret = 0;\n \n \tMLX5_ASSERT(txq_data);\n \tMLX5_ASSERT(!txq_ctrl->obj);\n+\tpage_size = rte_mem_page_size();\n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n \ttxq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\t\t sizeof(struct mlx5_txq_obj), 0,\n \t\t\t txq_ctrl->socket);\n@@ -674,9 +694,15 @@ mlx5_txq_obj_devx_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\tgoto error;\n \t}\n \t/* Allocate memory buffer for CQEs. */\n+\talignment = MLX5_CQE_BUF_ALIGNMENT;\n+\tif (alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n \ttxq_obj->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\t\t\t nqe * sizeof(struct mlx5_cqe),\n-\t\t\t\t MLX5_CQE_BUF_ALIGNMENT,\n+\t\t\t\t alignment,\n \t\t\t\t sh->numa_node);\n \tif (!txq_obj->cq_buf) {\n \t\tDRV_LOG(ERR,\n", "prefixes": [ "v3", "2/8" ] }