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GET /api/patches/74351/?format=api
{ "id": 74351, "url": "http://patches.dpdk.org/api/patches/74351/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594984263-89741-12-git-send-email-orika@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594984263-89741-12-git-send-email-orika@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594984263-89741-12-git-send-email-orika@mellanox.com", "date": "2020-07-17T11:11:01", "name": "[v4,11/13] regex/mlx5: add enqueue implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4454ca9de847896c46d62b1e5b389e91419d0f91", "submitter": { "id": 795, "url": "http://patches.dpdk.org/api/people/795/?format=api", "name": "Ori Kam", "email": "orika@mellanox.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594984263-89741-12-git-send-email-orika@mellanox.com/mbox/", "series": [ { "id": 11128, "url": "http://patches.dpdk.org/api/series/11128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11128", "date": "2020-07-17T11:10:50", "name": "add Mellanox RegEx PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/11128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74351/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/74351/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 36C54A053D;\n\tFri, 17 Jul 2020 13:13:27 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 316A41C0B6;\n\tFri, 17 Jul 2020 13:12:05 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id CF8FF1C12B\n for <dev@dpdk.org>; Fri, 17 Jul 2020 13:11:57 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 17 Jul 2020 14:11:55 +0300", "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06HBB6L2025276;\n Fri, 17 Jul 2020 14:11:55 +0300" ], "From": "Ori Kam <orika@mellanox.com>", "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com", "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com,\n alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com,\n nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com,\n Yuval Avnery <yuvalav@mellanox.com>", "Date": "Fri, 17 Jul 2020 11:11:01 +0000", "Message-Id": "<1594984263-89741-12-git-send-email-orika@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594984263-89741-1-git-send-email-orika@mellanox.com>", "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1594984263-89741-1-git-send-email-orika@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v4 11/13] regex/mlx5: add enqueue implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Yuval Avnery <yuvalav@mellanox.com>\n\nWill look for a free SQ to send the job on.\ndoorbell will be given when sq is full, or no more jobs on the burst.\n\nSigned-off-by: Yuval Avnery <yuvalav@mellanox.com>\nAcked-by: Ori Kam <orika@mellanox.com>\n---\n drivers/regex/mlx5/mlx5_regex.c | 1 +\n drivers/regex/mlx5/mlx5_regex.h | 6 ++\n drivers/regex/mlx5/mlx5_regex_control.c | 2 +\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 126 ++++++++++++++++++++++++++++++-\n 4 files changed, 131 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex f8a9562..ac6b4b1 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -165,6 +165,7 @@\n \t\tgoto error;\n \t}\n \tpriv->regexdev->dev_ops = &mlx5_regexdev_ops;\n+\tpriv->regexdev->enqueue = mlx5_regexdev_enqueue;\n \tpriv->regexdev->device = (struct rte_device *)pci_dev;\n \tpriv->regexdev->data->dev_private = priv;\n \tpriv->regexdev->state = RTE_REGEXDEV_READY;\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 21bb02b..fb81cb8 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -21,6 +21,9 @@ struct mlx5_regex_sq {\n \tuint32_t dbr_umem; /* Door bell record umem id. */\n \tuint8_t *wqe; /* The SQ ring buffer. */\n \tstruct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */\n+\tsize_t pi, db_pi;\n+\tsize_t ci;\n+\tuint32_t sqn;\n \tuint32_t *dbr;\n };\n \n@@ -45,6 +48,7 @@ struct mlx5_regex_qp {\n \tstruct ibv_mr *metadata;\n \tstruct ibv_mr *inputs;\n \tstruct ibv_mr *outputs;\n+\tsize_t ci, pi;\n };\n \n struct mlx5_regex_db {\n@@ -99,4 +103,6 @@ int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,\n \n /* mlx5_regex_fastpath.c */\n int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id);\n+uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,\n+\t\t struct rte_regex_ops **ops, uint16_t nb_ops);\n #endif /* MLX5_REGEX_H */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex 9b3f39e..c2d080f 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -216,6 +216,8 @@\n \tsq->wqe = buf;\n \tsq->wqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf, 64 * sq_size,\n \t\t\t\t\t\t7);\n+\tsq->ci = 0;\n+\tsq->pi = 0;\n \tif (!sq->wqe_umem) {\n \t\tDRV_LOG(ERR, \"Can't register wqe mem.\");\n \t\trte_errno = ENOMEM;\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex 23809c9..9f93b73 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -33,10 +33,14 @@\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n \n-#define MAX_WQE_INDEX 0xffff\n+#define MLX5_REGEX_MAX_WQE_INDEX 0xffff\n #define MLX5_REGEX_METADATA_SIZE 64\n-#define MLX5_REGEX_MAX_INPUT (1<<14)\n-#define MLX5_REGEX_MAX_OUTPUT (1<<11)\n+#define MLX5_REGEX_MAX_INPUT (1 << 14)\n+#define MLX5_REGEX_MAX_OUTPUT (1 << 11)\n+#define MLX5_REGEX_WQE_CTRL_OFFSET 12\n+#define MLX5_REGEX_WQE_METADATA_OFFSET 16\n+#define MLX5_REGEX_WQE_GATHER_OFFSET 32\n+#define MLX5_REGEX_WQE_SCATTER_OFFSET 48\n \n #define MLX5_REGEX_WQE_METADATA_OFFSET 16\n #define MLX5_REGEX_WQE_GATHER_OFFSET 32\n@@ -80,6 +84,120 @@ struct mlx5_regex_job {\n \tseg->addr = rte_cpu_to_be_64(address);\n }\n \n+static inline void\n+set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0,\n+\t\t uint16_t subset_id1, uint16_t subset_id2,\n+\t\t uint16_t subset_id3, uint8_t ctrl)\n+{\n+\tMLX5_SET(regexp_mmo_control, seg, le, le);\n+\tMLX5_SET(regexp_mmo_control, seg, ctrl, ctrl);\n+\tMLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0);\n+\tMLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1);\n+\tMLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2);\n+\tMLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3);\n+}\n+\n+static inline void\n+set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode,\n+\t\t uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds,\n+\t\t uint8_t signature, uint32_t imm)\n+{\n+\tseg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) |\n+\t\t\t\t\t\t ((uint32_t)pi << 8) |\n+\t\t\t\t\t\t opcode);\n+\tseg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds);\n+\tseg->fm_ce_se = fm_ce_se;\n+\tseg->signature = signature;\n+\tseg->imm = imm;\n+}\n+\n+static inline void\n+prep_one(struct mlx5_regex_sq *sq, struct rte_regex_ops *op,\n+\t struct mlx5_regex_job *job)\n+{\n+\tsize_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB;\n+\tuint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset;\n+\tint ds = 4; /* ctrl + meta + input + output */\n+\n+\tmemcpy(job->input,\n+\t\trte_pktmbuf_mtod(op->mbuf, void *),\n+\t\trte_pktmbuf_data_len(op->mbuf));\n+\tset_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi,\n+\t\t\t MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, sq->obj->id,\n+\t\t\t 0, ds, 0, 0);\n+\tset_regex_ctrl_seg(wqe + 12, 0, op->group_id0, op->group_id1,\n+\t\t\t op->group_id2,\n+\t\t\t op->group_id3, 0);\n+\tstruct mlx5_wqe_data_seg *input_seg =\n+\t\t(struct mlx5_wqe_data_seg *)(wqe +\n+\t\t\t\t\t MLX5_REGEX_WQE_GATHER_OFFSET);\n+\tinput_seg->byte_count =\n+\t\trte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf));\n+\tjob->user_id = op->user_id;\n+\tsq->db_pi = sq->pi;\n+\tsq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX;\n+}\n+\n+static inline void\n+send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq)\n+{\n+\tsize_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) *\n+\t\tMLX5_SEND_WQE_BB;\n+\tuint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset;\n+\t((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;\n+\tuint64_t *doorbell_addr =\n+\t\t(uint64_t *)((uint8_t *)uar->base_addr + 0x800);\n+\trte_cio_wmb();\n+\tsq->dbr[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) &\n+\t\t\t\t\t\t MLX5_REGEX_MAX_WQE_INDEX);\n+\trte_wmb();\n+\t*doorbell_addr = *(volatile uint64_t *)wqe;\n+\trte_wmb();\n+}\n+\n+static inline int\n+can_send(struct mlx5_regex_sq *sq) {\n+\treturn unlikely(sq->ci > sq->pi) ?\n+\t\t\tMLX5_REGEX_MAX_WQE_INDEX + sq->pi - sq->ci <\n+\t\t\tsq_size_get(sq) :\n+\t\t\tsq->pi - sq->ci < sq_size_get(sq);\n+}\n+\n+static inline uint32_t\n+job_id_get(uint32_t qid, size_t sq_size, size_t index) {\n+\treturn qid*sq_size + index % sq_size;\n+}\n+\n+uint16_t\n+mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,\n+\t\t struct rte_regex_ops **ops, uint16_t nb_ops)\n+{\n+\tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_regex_qp *queue = &priv->qps[qp_id];\n+\tstruct mlx5_regex_sq *sq;\n+\tsize_t sqid, job_id, i = 0;\n+\n+\twhile ((sqid = ffs(queue->free_sqs))) {\n+\t\tsqid--; /* ffs returns 1 for bit 0 */\n+\t\tsq = &queue->sqs[sqid];\n+\t\twhile (can_send(sq)) {\n+\t\t\tjob_id = job_id_get(sqid, sq_size_get(sq), sq->pi);\n+\t\t\tprep_one(sq, ops[i], &queue->jobs[job_id]);\n+\t\t\ti++;\n+\t\t\tif (unlikely(i == nb_ops)) {\n+\t\t\t\tsend_doorbell(priv->uar, sq);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t}\n+\t\tqueue->free_sqs &= ~(1 << sqid);\n+\t\tsend_doorbell(priv->uar, sq);\n+\t}\n+\n+out:\n+\tqueue->pi += i;\n+\treturn i;\n+}\n+\n static void\n setup_sqs(struct mlx5_regex_qp *queue)\n {\n@@ -155,7 +273,7 @@ struct mlx5_regex_job {\n \t\tgoto err_output;\n \t}\n \tqp->outputs = mlx5_glue->reg_mr(pd, ptr,\n-\t\t\t\t\tMLX5_REGEX_MAX_OUTPUT*qp->nb_desc,\n+\t\t\t\t\tMLX5_REGEX_MAX_OUTPUT * qp->nb_desc,\n \t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n \tif (!qp->outputs) {\n \t\trte_free(ptr);\n", "prefixes": [ "v4", "11/13" ] }