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GET /api/patches/74286/?format=api
{ "id": 74286, "url": "http://patches.dpdk.org/api/patches/74286/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594969911-105341-5-git-send-email-bingz@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594969911-105341-5-git-send-email-bingz@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594969911-105341-5-git-send-email-bingz@mellanox.com", "date": "2020-07-17T07:11:48", "name": "[v4,4/7] common/mlx5: adding DevX command for flex parsers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6bd48a9a7d0d5c9990c017567adce5fb268979f1", "submitter": { "id": 1357, "url": "http://patches.dpdk.org/api/people/1357/?format=api", "name": "Bing Zhao", "email": "bingz@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594969911-105341-5-git-send-email-bingz@mellanox.com/mbox/", "series": [ { "id": 11119, "url": "http://patches.dpdk.org/api/series/11119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11119", "date": "2020-07-17T07:11:44", "name": "add eCPRI support in mlx5 driver", "version": 4, "mbox": "http://patches.dpdk.org/series/11119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74286/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74286/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A31BA0528;\n\tFri, 17 Jul 2020 09:12:37 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 651E91BF71;\n\tFri, 17 Jul 2020 09:12:09 +0200 (CEST)", "from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130])\n by dpdk.org (Postfix) with ESMTP id 01EF71BF60\n for <dev@dpdk.org>; Fri, 17 Jul 2020 09:12:06 +0200 (CEST)" ], "From": "Bing Zhao <bingz@mellanox.com>", "To": "orika@mellanox.com,\n\tviacheslavo@mellanox.com", "Cc": "rasland@mellanox.com, matan@mellanox.com, dev@dpdk.org,\n netanelg@mellanox.com", "Date": "Fri, 17 Jul 2020 15:11:48 +0800", "Message-Id": "<1594969911-105341-5-git-send-email-bingz@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594969911-105341-1-git-send-email-bingz@mellanox.com>", "References": "<1594909426-64843-1-git-send-email-bingz@mellanox.com>\n <1594969911-105341-1-git-send-email-bingz@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v4 4/7] common/mlx5: adding DevX command for flex\n\tparsers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In order to use dynamic flex parser to parse protocols that is not\nsupported natively, two steps are needed.\n\nFirstly, creating the parse graph node. There are three parts of the\nflex parser: node, arc and sample. Node is the whole structure of a\nflex parser, when creating, the length of the protocol should be\nspecified. Then the input arc(s) is(are) mandatory, it will tell the\nHW when to use this parser to parse the packet. For a single parser\nnode, up to 8 input arcs could be supported and it gives SW ability\nto support this protocol over multiple layers. The output arc is\noptional and also up to 8 arcs could be supported. If the protocol\nis the last header of the stack, then output arc should be NULL. Or\nelse it should be specified. The protocol type in the arc is used to\nindicate the parser pointing to or from this flex parser node. For\noutput arc, the next header type field offset and size should be set\nin the node structure, then the HW could get the proper type of the\nnext header and decide which parser to point to.\nNote: the parsers have two types now, native parser and flex parser.\nThe arc between two flex parsers are not supported in this stage.\n\nSecondly, querying the sample IDs. If the protocol header parsed\nwith flex parser needs to used in flow rule offloading, the DW\nsamples are needed when creating the parse graph node. The offset\nof bytes starting from the header needs to be set. After creating\nthe node successfully, a general object handle will be returned.\nThis object could be queryed with Devx command to get the sample\nIDs.\nWhen creating a flow, sample IDs could be used to sample a DW from\nthe parsed header - 4 continuous bytes starting from the offset. The\nflow entry could specify some mask to use part of this DW for\nmatching. Up to 8 samples could be supported for a single parse\ngraph node. The offset should not exceed the header length.\n\nThe HW resources have some limitation, low layer driver error should\nbe checked once there is a failure of creating parse graph node.\n\nSigned-off-by: Netanel Gonen <netanelg@mellanox.com>\nSigned-off-by: Bing Zhao <bingz@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 170 +++++++++++++++++++++++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 8 ++\n drivers/common/mlx5/mlx5_prm.h | 69 +++++++++-\n drivers/common/mlx5/rte_common_mlx5_version.map | 2 +\n 4 files changed, 242 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 13cd76a..0cfa4dc 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -456,6 +456,167 @@ struct mlx5_devx_obj *\n \t}\n }\n \n+int\n+mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n+\t\t\t\t uint32_t ids[], uint32_t num)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};\n+\tvoid *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);\n+\tvoid *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);\n+\tvoid *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);\n+\tint ret;\n+\tuint32_t idx = 0;\n+\tuint32_t i;\n+\n+\tif (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {\n+\t\trte_errno = EINVAL;\n+\t\tDRV_LOG(ERR, \"Too many sample IDs to be fetched.\");\n+\t\treturn -rte_errno;\n+\t}\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_QUERY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);\n+\tret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),\n+\t\t\t\t\tout, sizeof(out));\n+\tif (ret) {\n+\t\trte_errno = ret;\n+\t\tDRV_LOG(ERR, \"Failed to query sample IDs with object %p.\",\n+\t\t\t(void *)flex_obj);\n+\t\treturn -rte_errno;\n+\t}\n+\tfor (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n+\t\tvoid *s_off = (void *)((char *)sample + i *\n+\t\t\t MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));\n+\t\tuint32_t en;\n+\n+\t\ten = MLX5_GET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_en);\n+\t\tif (!en)\n+\t\t\tcontinue;\n+\t\tids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,\n+\t\t\t\t flow_match_sample_field_id);\n+\t}\n+\tif (num != idx) {\n+\t\trte_errno = EINVAL;\n+\t\tDRV_LOG(ERR, \"Number of sample IDs are not as expected.\");\n+\t\treturn -rte_errno;\n+\t}\n+\treturn ret;\n+}\n+\n+\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_flex_parser(void *ctx,\n+\t\t\t struct mlx5_devx_graph_node_attr *data)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tvoid *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);\n+\tvoid *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);\n+\tvoid *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);\n+\tvoid *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);\n+\tvoid *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);\n+\tstruct mlx5_devx_obj *parse_flex_obj = NULL;\n+\tuint32_t i;\n+\n+\tparse_flex_obj = rte_calloc(__func__, 1, sizeof(*parse_flex_obj), 0);\n+\tif (!parse_flex_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate flex parser data\");\n+\t\trte_errno = ENOMEM;\n+\t\trte_free(in);\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);\n+\tMLX5_SET(parse_graph_flex, flex, header_length_mode,\n+\t\t data->header_length_mode);\n+\tMLX5_SET(parse_graph_flex, flex, header_length_base_value,\n+\t\t data->header_length_base_value);\n+\tMLX5_SET(parse_graph_flex, flex, header_length_field_offset,\n+\t\t data->header_length_field_offset);\n+\tMLX5_SET(parse_graph_flex, flex, header_length_field_shift,\n+\t\t data->header_length_field_shift);\n+\tMLX5_SET(parse_graph_flex, flex, header_length_field_mask,\n+\t\t data->header_length_field_mask);\n+\tfor (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n+\t\tstruct mlx5_devx_match_sample_attr *s = &data->sample[i];\n+\t\tvoid *s_off = (void *)((char *)sample + i *\n+\t\t\t MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));\n+\n+\t\tif (!s->flow_match_sample_en)\n+\t\t\tcontinue;\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_en, !!s->flow_match_sample_en);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_field_offset,\n+\t\t\t s->flow_match_sample_field_offset);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_offset_mode,\n+\t\t\t s->flow_match_sample_offset_mode);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_field_offset_mask,\n+\t\t\t s->flow_match_sample_field_offset_mask);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_field_offset_shift,\n+\t\t\t s->flow_match_sample_field_offset_shift);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_field_base_offset,\n+\t\t\t s->flow_match_sample_field_base_offset);\n+\t\tMLX5_SET(parse_graph_flow_match_sample, s_off,\n+\t\t\t flow_match_sample_tunnel_mode,\n+\t\t\t s->flow_match_sample_tunnel_mode);\n+\t}\n+\tfor (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {\n+\t\tstruct mlx5_devx_graph_arc_attr *ia = &data->in[i];\n+\t\tstruct mlx5_devx_graph_arc_attr *oa = &data->out[i];\n+\t\tvoid *in_off = (void *)((char *)in_arc + i *\n+\t\t\t MLX5_ST_SZ_BYTES(parse_graph_arc));\n+\t\tvoid *out_off = (void *)((char *)out_arc + i *\n+\t\t\t MLX5_ST_SZ_BYTES(parse_graph_arc));\n+\n+\t\tif (ia->arc_parse_graph_node != 0) {\n+\t\t\tMLX5_SET(parse_graph_arc, in_off,\n+\t\t\t\t compare_condition_value,\n+\t\t\t\t ia->compare_condition_value);\n+\t\t\tMLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,\n+\t\t\t\t ia->start_inner_tunnel);\n+\t\t\tMLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,\n+\t\t\t\t ia->arc_parse_graph_node);\n+\t\t\tMLX5_SET(parse_graph_arc, in_off,\n+\t\t\t\t parse_graph_node_handle,\n+\t\t\t\t ia->parse_graph_node_handle);\n+\t\t}\n+\t\tif (oa->arc_parse_graph_node != 0) {\n+\t\t\tMLX5_SET(parse_graph_arc, out_off,\n+\t\t\t\t compare_condition_value,\n+\t\t\t\t oa->compare_condition_value);\n+\t\t\tMLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,\n+\t\t\t\t oa->start_inner_tunnel);\n+\t\t\tMLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,\n+\t\t\t\t oa->arc_parse_graph_node);\n+\t\t\tMLX5_SET(parse_graph_arc, out_off,\n+\t\t\t\t parse_graph_node_handle,\n+\t\t\t\t oa->parse_graph_node_handle);\n+\t\t}\n+\t}\n+\tparse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t\t\t out, sizeof(out));\n+\tif (!parse_flex_obj->obj) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create FLEX PARSE GRAPH object \"\n+\t\t\t\"by using DevX.\");\n+\t\trte_free(parse_flex_obj);\n+\t\treturn NULL;\n+\t}\n+\tparse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\treturn parse_flex_obj;\n+}\n+\n /**\n * Query HCA attributes.\n * Using those attributes we can check on run time if the device\n@@ -527,6 +688,9 @@ struct mlx5_devx_obj *\n \tattr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t\tgeneral_obj_types) &\n \t\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);\n+\tattr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);\n \tattr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t wqe_index_ignore_cap);\n \tattr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);\n@@ -1098,7 +1262,7 @@ struct mlx5_devx_obj *\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to modify SQ using DevX\");\n \t\trte_errno = errno;\n-\t\treturn -errno;\n+\t\treturn -rte_errno;\n \t}\n \treturn ret;\n }\n@@ -1412,7 +1576,7 @@ struct mlx5_devx_obj *\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to modify VIRTQ using DevX.\");\n \t\trte_errno = errno;\n-\t\treturn -errno;\n+\t\treturn -rte_errno;\n \t}\n \treturn ret;\n }\n@@ -1615,7 +1779,7 @@ struct mlx5_devx_obj *\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to modify QP using DevX.\");\n \t\trte_errno = errno;\n-\t\treturn -errno;\n+\t\treturn -rte_errno;\n \t}\n \treturn ret;\n }\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 4811a1a..2b39ad2 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -70,6 +70,7 @@ struct mlx5_hca_attr {\n \tuint32_t eswitch_manager:1;\n \tuint32_t flow_counters_dump:1;\n \tuint32_t log_max_rqt_size:5;\n+\tuint32_t parse_graph_flex_node:1;\n \tuint8_t flow_counter_bulk_alloc_bitmap;\n \tuint32_t eth_net_offloads:1;\n \tuint32_t eth_virt:1;\n@@ -426,6 +427,13 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,\n __rte_internal\n int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,\n \t\t\t struct mlx5_devx_rqt_attr *rqt_attr);\n+__rte_internal\n+int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,\n+\t\t\t\t uint32_t ids[], uint32_t num);\n+\n+__rte_internal\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,\n+\t\t\t\t\tstruct mlx5_devx_graph_node_attr *data);\n \n __rte_internal\n int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 81ff3d0..ec3b600 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -994,10 +994,9 @@ enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n };\n \n-enum {\n-\tMLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),\n-\tMLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),\n-};\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q\t\t\t(1ULL << 0xd)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS\t\t(1ULL << 0x1c)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE\t(1ULL << 0x22)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -2068,6 +2067,7 @@ struct mlx5_ifc_create_cq_in_bits {\n enum {\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n+\tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n@@ -2611,6 +2611,67 @@ struct mlx5_ifc_register_mtutc_bits {\n #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0\n #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1\n \n+struct mlx5_ifc_parse_graph_arc_bits {\n+\tu8 start_inner_tunnel[0x1];\n+\tu8 reserved_at_1[0x7];\n+\tu8 arc_parse_graph_node[0x8];\n+\tu8 compare_condition_value[0x10];\n+\tu8 parse_graph_node_handle[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_parse_graph_flow_match_sample_bits {\n+\tu8 flow_match_sample_en[0x1];\n+\tu8 reserved_at_1[0x3];\n+\tu8 flow_match_sample_offset_mode[0x4];\n+\tu8 reserved_at_5[0x8];\n+\tu8 flow_match_sample_field_offset[0x10];\n+\tu8 reserved_at_32[0x4];\n+\tu8 flow_match_sample_field_offset_shift[0x4];\n+\tu8 flow_match_sample_field_base_offset[0x8];\n+\tu8 reserved_at_48[0xd];\n+\tu8 flow_match_sample_tunnel_mode[0x3];\n+\tu8 flow_match_sample_field_offset_mask[0x20];\n+\tu8 flow_match_sample_field_id[0x20];\n+};\n+\n+struct mlx5_ifc_parse_graph_flex_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_64[0x20];\n+\tu8 header_length_base_value[0x10];\n+\tu8 reserved_at_112[0x4];\n+\tu8 header_length_field_shift[0x4];\n+\tu8 reserved_at_120[0x4];\n+\tu8 header_length_mode[0x4];\n+\tu8 header_length_field_offset[0x10];\n+\tu8 next_header_field_offset[0x10];\n+\tu8 reserved_at_160[0x1b];\n+\tu8 next_header_field_size[0x5];\n+\tu8 header_length_field_mask[0x20];\n+\tu8 reserved_at_224[0x20];\n+\tstruct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];\n+\tstruct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];\n+\tstruct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];\n+};\n+\n+struct mlx5_ifc_create_flex_parser_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_parse_graph_flex_bits flex;\n+};\n+\n+struct mlx5_ifc_create_flex_parser_out_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_parse_graph_flex_bits flex;\n+};\n+\n+struct mlx5_ifc_parse_graph_flex_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tstruct mlx5_ifc_parse_graph_flex_bits capability;\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex 68007ef..5aad219 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -11,6 +11,7 @@ INTERNAL {\n \tmlx5_dev_to_pci_addr;\n \n \tmlx5_devx_cmd_create_cq;\n+\tmlx5_devx_cmd_create_flex_parser;\n \tmlx5_devx_cmd_create_qp;\n \tmlx5_devx_cmd_create_rq;\n \tmlx5_devx_cmd_create_rqt;\n@@ -32,6 +33,7 @@ INTERNAL {\n \tmlx5_devx_cmd_modify_virtq;\n \tmlx5_devx_cmd_qp_query_tis_td;\n \tmlx5_devx_cmd_query_hca_attr;\n+\tmlx5_devx_cmd_query_parse_samples;\n \tmlx5_devx_cmd_query_virtio_q_counters;\n \tmlx5_devx_cmd_query_virtq;\n \tmlx5_devx_cmd_register_read;\n", "prefixes": [ "v4", "4/7" ] }