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GET /api/patches/74059/?format=api
{ "id": 74059, "url": "http://patches.dpdk.org/api/patches/74059/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-18-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-18-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-18-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:54", "name": "[v2,17/17] net/mlx5: convert Rx timestamps in realtime format", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "012edb0617c3f578ee5aad9719a8dcf5c7754883", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-18-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74059/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/74059/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 73DA1A0540;\n\tWed, 15 Jul 2020 08:24:56 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8A5EB1C1DF;\n\tWed, 15 Jul 2020 08:22:34 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id D217B1C19F\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:22 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:20 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MKNR007092;\n Wed, 15 Jul 2020 09:22:20 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MKpV016472;\n Wed, 15 Jul 2020 06:22:20 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MKSK016471;\n Wed, 15 Jul 2020 06:22:20 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:54 +0000", "Message-Id": "<1594794114-16313-18-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 17/17] net/mlx5: convert Rx timestamps in\n\trealtime format", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The ConnectX-6DX supports the timestamps in various formats,\nthe new realtime format is introduced - the upper 32-bit word\nof timestamp contains the UTC seconds and the lower 32-bit word\ncontains the nanoseconds. This patch detects what format is\nconfigured in the NIC and performs the conversion accordingly.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 21 +++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_rxq.c | 24 ++++++++++++++\n drivers/net/mlx5/mlx5_rxtx.c | 6 +++-\n drivers/net/mlx5/mlx5_rxtx.h | 4 +++\n drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 34 +++++++++++++++-----\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 54 ++++++++++++++++++++++----------\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 34 +++++++++++++++-----\n drivers/net/mlx5/mlx5_trigger.c | 6 ++--\n 9 files changed, 149 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex e7241d8..f228bab 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -936,6 +936,27 @@\n \t\tgoto error;\n #endif\n \t}\n+\tif (config.devx) {\n+\t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n+\n+\t\terr = mlx5_devx_cmd_register_read\n+\t\t\t(sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n+\t\t\treg, MLX5_ST_SZ_DW(register_mtutc));\n+\t\tif (!err) {\n+\t\t\tuint32_t ts_mode;\n+\n+\t\t\t/* MTUTC register is read successfully. */\n+\t\t\tts_mode = MLX5_GET(register_mtutc, reg,\n+\t\t\t\t\t time_stamp_mode);\n+\t\t\tif (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)\n+\t\t\t\tconfig.rt_timestamp = 1;\n+\t\t} else {\n+\t\t\t/* Kernel does not support register reading. */\n+\t\t\tif (config.hca_attr.dev_freq_khz ==\n+\t\t\t\t\t\t (NS_PER_S / MS_PER_S))\n+\t\t\t\tconfig.rt_timestamp = 1;\n+\t\t}\n+\t}\n \tif (config.mprq.enabled && mprq) {\n \t\tif (config.mprq.stride_num_n &&\n \t\t (config.mprq.stride_num_n > mprq_max_stride_num_n ||\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 97a14fb..34e2bc1 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -216,6 +216,7 @@ struct mlx5_dev_config {\n \tunsigned int devx:1; /* Whether devx interface is available or not. */\n \tunsigned int dest_tir:1; /* Whether advanced DR API is available. */\n \tunsigned int reclaim_mode:2; /* Memory reclaim mode. */\n+\tunsigned int rt_timestamp:1; /* realtime timestamp format. */\n \tstruct {\n \t\tunsigned int enabled:1; /* Whether MPRQ is enabled. */\n \t\tunsigned int stride_num_n; /* Number of strides. */\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 2681322..7dd06e8 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2972,3 +2972,27 @@ struct mlx5_hrxq *\n \t\tpriv->drop_queue.hrxq = NULL;\n \t}\n }\n+\n+\n+/**\n+ * Set the Rx queue timestamp conversion parameters\n+ *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n+ */\n+void\n+mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_rxq_data *data;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i != priv->rxqs_n; ++i) {\n+\t\tif (!(*priv->rxqs)[i])\n+\t\t\tcontinue;\n+\t\tdata = (*priv->rxqs)[i];\n+\t\tdata->sh = sh;\n+\t\tdata->rt_timestamp = priv->config.rt_timestamp;\n+\t}\n+}\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex e511142..65239f9 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -1389,7 +1389,11 @@ enum mlx5_txcmp_code {\n \t\tpkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);\n \t}\n \tif (rxq->hw_timestamp) {\n-\t\tpkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);\n+\t\tuint64_t ts = rte_be_to_cpu_64(cqe->timestamp);\n+\n+\t\tif (rxq->rt_timestamp)\n+\t\t\tts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);\n+\t\tpkt->timestamp = ts;\n \t\tpkt->ol_flags |= PKT_RX_TIMESTAMP;\n \t}\n }\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex d082cd7..5116a15 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -109,6 +109,7 @@ enum mlx5_rxq_err_state {\n struct mlx5_rxq_data {\n \tunsigned int csum:1; /* Enable checksum offloading. */\n \tunsigned int hw_timestamp:1; /* Enable HW timestamp. */\n+\tunsigned int rt_timestamp:1; /* Realtime timestamp format. */\n \tunsigned int vlan_strip:1; /* Enable VLAN stripping. */\n \tunsigned int crc_present:1; /* CRC must be subtracted. */\n \tunsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */\n@@ -148,6 +149,7 @@ struct mlx5_rxq_data {\n \tstruct rte_mempool *mp;\n \tstruct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */\n \tstruct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */\n+\tstruct mlx5_dev_ctx_shared *sh; /* Shared context. */\n \tuint16_t idx; /* Queue index. */\n \tstruct mlx5_rxq_stats stats;\n \trte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */\n@@ -442,6 +444,8 @@ uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,\n void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);\n uint64_t mlx5_get_rx_port_offloads(void);\n uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);\n+void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);\n+\n \n /* mlx5_txq.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\nindex b55138a..f5414ee 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n@@ -1024,14 +1024,32 @@\n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n \t\tif (rxq->hw_timestamp) {\n-\t\t\tpkts[pos]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos].timestamp);\n-\t\t\tpkts[pos + 1]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p1].timestamp);\n-\t\t\tpkts[pos + 2]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p2].timestamp);\n-\t\t\tpkts[pos + 3]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p3].timestamp);\n+\t\t\tif (rxq->rt_timestamp) {\n+\t\t\t\tstruct mlx5_dev_ctx_shared *sh = rxq->sh;\n+\t\t\t\tuint64_t ts;\n+\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos].timestamp);\n+\t\t\t\tpkts[pos]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p1].timestamp);\n+\t\t\t\tpkts[pos + 1]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p2].timestamp);\n+\t\t\t\tpkts[pos + 2]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p3].timestamp);\n+\t\t\t\tpkts[pos + 3]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t} else {\n+\t\t\t\tpkts[pos]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos].timestamp);\n+\t\t\t\tpkts[pos + 1]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p1].timestamp);\n+\t\t\t\tpkts[pos + 2]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p2].timestamp);\n+\t\t\t\tpkts[pos + 3]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p3].timestamp);\n+\t\t\t}\n \t\t}\n \t\tif (rxq->dynf_meta) {\n \t\t\tuint64_t flag = rxq->flow_meta_mask;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex 3007c03..555c342 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -694,22 +694,44 @@\n \t\trxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,\n \t\t\t\t\t opcode, &elts[pos]);\n \t\tif (rxq->hw_timestamp) {\n-\t\t\telts[pos]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(\n-\t\t\t\t\tcontainer_of(p0, struct mlx5_cqe,\n-\t\t\t\t\t\t pkt_info)->timestamp);\n-\t\t\telts[pos + 1]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(\n-\t\t\t\t\tcontainer_of(p1, struct mlx5_cqe,\n-\t\t\t\t\t\t pkt_info)->timestamp);\n-\t\t\telts[pos + 2]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(\n-\t\t\t\t\tcontainer_of(p2, struct mlx5_cqe,\n-\t\t\t\t\t\t pkt_info)->timestamp);\n-\t\t\telts[pos + 3]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(\n-\t\t\t\t\tcontainer_of(p3, struct mlx5_cqe,\n-\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\tif (rxq->rt_timestamp) {\n+\t\t\t\tstruct mlx5_dev_ctx_shared *sh = rxq->sh;\n+\t\t\t\tuint64_t ts;\n+\n+\t\t\t\tts = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p0, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p1, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 1]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p2, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 2]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p3, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 3]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t} else {\n+\t\t\t\telts[pos]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p0, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 1]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p1, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 2]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p2, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t\telts[pos + 3]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t(container_of(p3, struct mlx5_cqe,\n+\t\t\t\t\t\t pkt_info)->timestamp);\n+\t\t\t}\n \t\t}\n \t\tif (!!rxq->flow_meta_mask) {\n \t\t\t/* This code is subject for futher optimization. */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex da5960a..34e3397 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -655,14 +655,32 @@\n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n \t\tif (rxq->hw_timestamp) {\n-\t\t\tpkts[pos]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos].timestamp);\n-\t\t\tpkts[pos + 1]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p1].timestamp);\n-\t\t\tpkts[pos + 2]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p2].timestamp);\n-\t\t\tpkts[pos + 3]->timestamp =\n-\t\t\t\trte_be_to_cpu_64(cq[pos + p3].timestamp);\n+\t\t\tif (rxq->rt_timestamp) {\n+\t\t\t\tstruct mlx5_dev_ctx_shared *sh = rxq->sh;\n+\t\t\t\tuint64_t ts;\n+\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos].timestamp);\n+\t\t\t\tpkts[pos]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p1].timestamp);\n+\t\t\t\tpkts[pos + 1]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p2].timestamp);\n+\t\t\t\tpkts[pos + 2]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t\tts = rte_be_to_cpu_64(cq[pos + p3].timestamp);\n+\t\t\t\tpkts[pos + 3]->timestamp =\n+\t\t\t\t\tmlx5_txpp_convert_rx_ts(sh, ts);\n+\t\t\t} else {\n+\t\t\t\tpkts[pos]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos].timestamp);\n+\t\t\t\tpkts[pos + 1]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p1].timestamp);\n+\t\t\t\tpkts[pos + 2]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p2].timestamp);\n+\t\t\t\tpkts[pos + 3]->timestamp = rte_be_to_cpu_64\n+\t\t\t\t\t\t(cq[pos + p3].timestamp);\n+\t\t\t}\n \t\t}\n \t\tif (rxq->dynf_meta) {\n \t\t\t/* This code is subject for futher optimization. */\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 29aef54..6e5a730 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -329,9 +329,11 @@\n \t\t\tdev->data->port_id);\n \t\tgoto error;\n \t}\n-\t/* Set a mask and offset of dynamic metadata flows into Rx queues*/\n+\t/* Set a mask and offset of dynamic metadata flows into Rx queues. */\n \tmlx5_flow_rxq_dynf_metadata_set(dev);\n-\t/* Set a mask and offset of scheduling on timestamp into Tx queues*/\n+\t/* Set flags and context to convert Rx timestamps. */\n+\tmlx5_rxq_timestamp_set(dev);\n+\t/* Set a mask and offset of scheduling on timestamp into Tx queues. */\n \tmlx5_txq_dynf_timestamp_set(dev);\n \t/*\n \t * In non-cached mode, it only needs to start the default mreg copy\n", "prefixes": [ "v2", "17/17" ] }